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drm/amd/pm: correct platformcaps setup

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Correct Polaris10 platformcaps setup.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Evan Quan 2020-09-25 14:17:01 +08:00 committed by Alex Deucher
parent 55411d1623
commit 326d0ff7aa
3 changed files with 19 additions and 4 deletions
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5
drivers/gpu/drm/amd/pm/powerplay/hwmgr/hwmgr.c
View File

@ -486,9 +486,10 @@ int polaris_set_asic_special_caps(struct pp_hwmgr *hwmgr)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_AutomaticDCTransition);
if (hwmgr->chip_id != CHIP_POLARIS10)
if (((hwmgr->chip_id == CHIP_POLARIS11) && !hwmgr->is_kicker) ||
(hwmgr->chip_id == CHIP_POLARIS12))
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SPLLShutdownSupport);
PHM_PlatformCaps_SPLLShutdownSupport);
if (hwmgr->chip_id != CHIP_POLARIS11) {
phm_cap_set(hwmgr->platform_descriptor.platformCaps,

11
drivers/gpu/drm/amd/pm/powerplay/hwmgr/smu7_hwmgr.c
View File

@ -1823,6 +1823,17 @@ static void smu7_init_dpm_defaults(struct pp_hwmgr *hwmgr)
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_EngineSpreadSpectrumSupport);
}
if ((adev->pdev->device == 0x699F) &&
(adev->pdev->revision == 0xCF)) {
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_PowerContainment);
data->enable_tdc_limit_feature = false;
data->enable_pkg_pwr_tracking_feature = false;
data->disable_edc_leakage_controller = true;
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ClockStretcher);
}
}
static int smu7_calculate_ro_range(struct pp_hwmgr *hwmgr)

7
drivers/gpu/drm/amd/pm/powerplay/smumgr/polaris10_smumgr.c
View File

@ -2041,8 +2041,11 @@ static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr)
if (atomctrl_get_pp_assign_pin(hwmgr, PP_AC_DC_SWITCH_GPIO_PINID,
&gpio_pin)) {
table->AcDcGpio = gpio_pin.uc_gpio_pin_bit_shift;
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_AutomaticDCTransition);
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_AutomaticDCTransition) &&
!smum_send_msg_to_smc(hwmgr, PPSMC_MSG_UseNewGPIOScheme, NULL))
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SMCtoPPLIBAcdcGpioScheme);
} else {
table->AcDcGpio = SMU7_UNUSED_GPIO_PIN;
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,