forked from Minki/linux
ARM: OMAP4+: Reset CPU1 properly for kexec
We need to reset CPU1 properly for kexec when booting different kernel versions. Otherwise CPU1 will attempt to boot the the previous kernel's start_secondary(). Note that the restctrl register is different from the low-power mode wakeup register CPU1_WAKEUP_NS_PA_ADDR. We need to configure both. Let's fix the issue by defining SoC specific data to initialize things in a more generic way. And let's also standardize omap-smp.c to use soc_is instead of cpu_is while at it. Acked-by: Santosh Shilimkar <ssantosh@kernel.org> Tested-by: Keerthy <j-keerthy@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -40,14 +40,35 @@
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#define OMAP5_CORE_COUNT 0x2
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/* SCU base address */
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static void __iomem *scu_base;
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struct omap_smp_config {
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unsigned long cpu1_rstctrl_pa;
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void __iomem *cpu1_rstctrl_va;
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void __iomem *scu_base;
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void *startup_addr;
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};
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static struct omap_smp_config cfg;
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static const struct omap_smp_config omap443x_cfg __initconst = {
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.cpu1_rstctrl_pa = 0x4824380c,
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.startup_addr = omap4_secondary_startup,
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};
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static const struct omap_smp_config omap446x_cfg __initconst = {
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.cpu1_rstctrl_pa = 0x4824380c,
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.startup_addr = omap4460_secondary_startup,
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};
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static const struct omap_smp_config omap5_cfg __initconst = {
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.cpu1_rstctrl_pa = 0x48243810,
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.startup_addr = omap5_secondary_startup,
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};
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static DEFINE_SPINLOCK(boot_lock);
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void __iomem *omap4_get_scu_base(void)
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{
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return scu_base;
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return cfg.scu_base;
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}
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#ifdef CONFIG_OMAP5_ERRATA_801819
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@ -93,7 +114,7 @@ static void omap4_secondary_init(unsigned int cpu)
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* OMAP443X GP devices- SMP bit isn't accessible.
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* OMAP446X GP devices - SMP bit access is enabled on both CPUs.
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*/
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if (cpu_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
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if (soc_is_omap443x() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
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omap_secure_dispatcher(OMAP4_PPA_CPU_ACTRL_SMP_INDEX,
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4, 0, 0, 0, 0, 0);
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@ -222,9 +243,9 @@ static void __init omap4_smp_init_cpus(void)
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* Currently we can't call ioremap here because
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* SoC detection won't work until after init_early.
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*/
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scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
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BUG_ON(!scu_base);
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ncores = scu_get_core_count(scu_base);
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cfg.scu_base = OMAP2_L4_IO_ADDRESS(scu_a9_get_base());
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BUG_ON(!cfg.scu_base);
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ncores = scu_get_core_count(cfg.scu_base);
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} else if (cpu_id == CPU_CORTEX_A15) {
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ncores = OMAP5_CORE_COUNT;
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}
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@ -242,20 +263,51 @@ static void __init omap4_smp_init_cpus(void)
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static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
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{
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void *startup_addr = omap4_secondary_startup;
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void __iomem *base = omap_get_wakeupgen_base();
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const struct omap_smp_config *c = NULL;
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if (soc_is_omap443x())
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c = &omap443x_cfg;
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else if (soc_is_omap446x())
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c = &omap446x_cfg;
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else if (soc_is_dra74x() || soc_is_omap54xx())
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c = &omap5_cfg;
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if (!c) {
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pr_err("%s Unknown SMP SoC?\n", __func__);
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return;
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}
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/* Must preserve cfg.scu_base set earlier */
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cfg.cpu1_rstctrl_pa = c->cpu1_rstctrl_pa;
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cfg.startup_addr = c->startup_addr;
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if (soc_is_dra74x() || soc_is_omap54xx()) {
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if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
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cfg.startup_addr = omap5_secondary_hyp_startup;
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omap5_erratum_workaround_801819();
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}
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cfg.cpu1_rstctrl_va = ioremap(cfg.cpu1_rstctrl_pa, 4);
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if (!cfg.cpu1_rstctrl_va)
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return;
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/*
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* Initialise the SCU and wake up the secondary core using
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* wakeup_secondary().
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*/
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if (scu_base)
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scu_enable(scu_base);
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if (cfg.scu_base)
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scu_enable(cfg.scu_base);
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if (cpu_is_omap446x())
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startup_addr = omap4460_secondary_startup;
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if (soc_is_dra74x() || soc_is_omap54xx())
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omap5_erratum_workaround_801819();
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/*
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* Reset CPU1 before configuring, otherwise kexec will
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* end up trying to use old kernel startup address.
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*/
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if (cfg.cpu1_rstctrl_va) {
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writel_relaxed(1, cfg.cpu1_rstctrl_va);
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readl_relaxed(cfg.cpu1_rstctrl_va);
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writel_relaxed(0, cfg.cpu1_rstctrl_va);
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}
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/*
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* Write the address of secondary startup routine into the
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@ -264,19 +316,10 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
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* A barrier is added to ensure that write buffer is drained
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*/
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if (omap_secure_apis_support())
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omap_auxcoreboot_addr(virt_to_phys(startup_addr));
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omap_auxcoreboot_addr(virt_to_phys(cfg.startup_addr));
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else
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/*
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* If the boot CPU is in HYP mode then start secondary
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* CPU in HYP mode as well.
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*/
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if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
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writel_relaxed(virt_to_phys(omap5_secondary_hyp_startup),
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base + OMAP_AUX_CORE_BOOT_1);
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else
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writel_relaxed(virt_to_phys(omap5_secondary_startup),
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base + OMAP_AUX_CORE_BOOT_1);
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writel_relaxed(virt_to_phys(cfg.startup_addr),
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base + OMAP_AUX_CORE_BOOT_1);
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}
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const struct smp_operations omap4_smp_ops __initconst = {
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@ -286,5 +329,6 @@ const struct smp_operations omap4_smp_ops __initconst = {
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.smp_boot_secondary = omap4_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_die = omap4_cpu_die,
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.cpu_kill = omap4_cpu_kill,
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#endif
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};
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