arm64: dts: exynos: add initial support for exynosautov9 SoC
Add minimal support for ExynosAuto v9 SoC[1]. - Enumarate all pinctrl nodes - UART with exynos850 compatible - UFS0 HCI + Phy Like exynos850, this also uses fixed-rate clock nodes until clock driver has been supported. The clock nodes are initialized on bootloader stage thus we don't need to control them so far. [1]: https://www.samsung.com/semiconductor/minisite/exynos/products/automotiveprocessor/exynos-auto-v9/ Signed-off-by: Chanho Park <chanho61.park@samsung.com> Link: https://lore.kernel.org/r/20211012002314.38965-3-chanho61.park@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
This commit is contained in:
Chanho Park
Krzysztof Kozlowski
parent
6de3cc6db0
commit
31bbac5263
arch/arm64/boot/dts/exynos
1189
arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi
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1189
arch/arm64/boot/dts/exynos/exynosautov9-pinctrl.dtsi
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Load Diff
301
arch/arm64/boot/dts/exynos/exynosautov9.dtsi
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arch/arm64/boot/dts/exynos/exynosautov9.dtsi
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Samsung's ExynosAuto v9 SoC device tree source
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*
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* Copyright (c) 2021 Samsung Electronics Co., Ltd.
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*
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "samsung,exynosautov9";
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#address-cells = <2>;
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#size-cells = <1>;
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interrupt-parent = <&gic>;
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aliases {
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pinctrl0 = &pinctrl_alive;
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pinctrl1 = &pinctrl_aud;
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pinctrl2 = &pinctrl_fsys0;
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pinctrl3 = &pinctrl_fsys1;
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pinctrl4 = &pinctrl_fsys2;
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pinctrl5 = &pinctrl_peric0;
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pinctrl6 = &pinctrl_peric1;
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};
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arm-pmu {
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compatible = "arm,cortex-a76-pmu";
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
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<&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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core2 {
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cpu = <&cpu2>;
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};
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core3 {
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cpu = <&cpu3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu4>;
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};
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core1 {
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cpu = <&cpu5>;
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};
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core2 {
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cpu = <&cpu6>;
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};
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core3 {
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cpu = <&cpu7>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x0>;
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enable-method = "psci";
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};
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cpu1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x100>;
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enable-method = "psci";
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};
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cpu2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x200>;
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enable-method = "psci";
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};
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cpu3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x300>;
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enable-method = "psci";
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};
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cpu4: cpu@10000 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x10000>;
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enable-method = "psci";
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};
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cpu5: cpu@10100 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x10100>;
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enable-method = "psci";
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};
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cpu6: cpu@10200 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x10200>;
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enable-method = "psci";
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};
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cpu7: cpu@10300 {
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device_type = "cpu";
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compatible = "arm,cortex-a76";
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reg = <0x10300>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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cpu_suspend = <0xc4000001>;
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cpu_off = <0x84000002>;
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cpu_on = <0xc4000003>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
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};
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fixed-rate-clocks {
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xtcxo: clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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clock-output-names = "oscclk";
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};
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/*
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* Keep the stub clock for serial driver, until proper clock
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* driver is implemented.
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*/
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uart_clock: uart-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <133250000>;
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clock-output-names = "uart";
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};
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/*
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* Keep the stub clock for ufs driver, until proper clock
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* driver is implemented.
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*/
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ufs_core_clock: ufs-core-clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <166562500>;
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};
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};
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soc: soc@0 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0x0 0x20000000>;
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gic: interrupt-controller@10101000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x10101000 0x1000>,
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<0x10102000 0x2000>,
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<0x10104000 0x2000>,
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<0x10106000 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) |
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IRQ_TYPE_LEVEL_HIGH)>;
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};
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pinctrl_alive: pinctrl@10450000 {
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compatible = "samsung,exynosautov9-pinctrl";
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reg = <0x10450000 0x1000>;
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wakeup-interrupt-controller {
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compatible = "samsung,exynos7-wakeup-eint";
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};
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};
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pinctrl_aud: pinctrl@19c60000{
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compatible = "samsung,exynosautov9-pinctrl";
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reg = <0x19c60000 0x1000>;
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};
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pinctrl_fsys0: pinctrl@17740000 {
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compatible = "samsung,exynosautov9-pinctrl";
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reg = <0x17740000 0x1000>;
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interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_fsys1: pinctrl@17060000 {
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compatible = "samsung,exynosautov9-pinctrl";
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reg = <0x17060000 0x1000>;
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interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_fsys2: pinctrl@17c30000 {
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compatible = "samsung,exynosautov9-pinctrl";
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reg = <0x17c30000 0x1000>;
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interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_peric0: pinctrl@10230000 {
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compatible = "samsung,exynosautov9-pinctrl";
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reg = <0x10230000 0x1000>;
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interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>;
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};
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pinctrl_peric1: pinctrl@10830000 {
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compatible = "samsung,exynosautov9-pinctrl";
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reg = <0x10830000 0x1000>;
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interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu_system_controller: system-controller@10460000 {
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compatible = "samsung,exynos7-pmu", "syscon";
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reg = <0x10460000 0x10000>;
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};
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syscon_fsys2: syscon@17c20000 {
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compatible = "samsung,exynosautov9-sysreg", "syscon";
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reg = <0x17c20000 0x1000>;
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};
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/* USI: UART */
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serial_0: uart@10300000 {
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compatible = "samsung,exynos850-uart";
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reg = <0x10300000 0x100>;
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interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_bus_dual>;
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clocks = <&uart_clock>, <&uart_clock>;
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clock-names = "uart", "clk_uart_baud0";
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status = "disabled";
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};
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ufs_0_phy: ufs0-phy@17e04000 {
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compatible = "samsung,exynosautov9-ufs-phy";
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reg = <0x17e04000 0xc00>;
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reg-names = "phy-pma";
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samsung,pmu-syscon = <&pmu_system_controller>;
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#phy-cells = <0>;
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clocks = <&xtcxo>;
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clock-names = "ref_clk";
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status = "disabled";
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};
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ufs_0: ufs0@17e00000 {
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compatible ="samsung,exynosautov9-ufs";
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reg = <0x17e00000 0x100>, /* 0: HCI standard */
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<0x17e01100 0x410>, /* 1: Vendor-specific */
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<0x17e80000 0x8000>, /* 2: UNIPRO */
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<0x17dc0000 0x2200>; /* 3: UFS protector */
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reg-names = "hci", "vs_hci", "unipro", "ufsp";
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interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ufs_core_clock>,
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<&ufs_core_clock>;
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clock-names = "core_clk", "sclk_unipro_main";
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freq-table-hz = <0 0>, <0 0>;
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pinctrl-names = "default";
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pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
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phys = <&ufs_0_phy>;
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phy-names = "ufs-phy";
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samsung,sysreg = <&syscon_fsys2>;
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samsung,ufs-shareability-reg-offset = <0x710>;
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status = "disabled";
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};
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};
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};
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#include "exynosautov9-pinctrl.dtsi"
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