forked from Minki/linux
Merge branch 'remotes/lorenzo/pci/aardvark'
- Use LTSSM state to build link training flag since Aardvark doesn't
implement the Link Training bit (Remi Pommarel)
- Delay before training Aardvark link in case PERST# was asserted before
the driver probe (Remi Pommarel)
- Fix Aardvark issues with Root Control reads and writes (Remi Pommarel)
- Don't rely on jiffies in Aardvark config access path since interrupts
may be disabled (Remi Pommarel)
- Fix Aardvark big-endian support (Grzegorz Jaszczyk)
- Fix bridge emulation big-endian support (Grzegorz Jaszczyk)
* remotes/lorenzo/pci/aardvark:
PCI: pci-bridge-emul: Fix big-endian support
PCI: aardvark: Fix big endian support
PCI: aardvark: Don't rely on jiffies while holding spinlock
PCI: aardvark: Fix PCI_EXP_RTCTL register configuration
PCI: aardvark: Wait for endpoint to be ready before training link
PCI: aardvark: Use LTSSM state to build link training flag
This commit is contained in:
Bjorn Helgaas
commit
318ed91f36
@ -176,11 +176,14 @@
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(PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn)) | \
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PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
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#define PIO_TIMEOUT_MS 1
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#define PIO_RETRY_CNT 500
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#define PIO_RETRY_DELAY 2 /* 2 us*/
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#define LINK_WAIT_MAX_RETRIES 10
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#define LINK_WAIT_USLEEP_MIN 90000
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#define LINK_WAIT_USLEEP_MAX 100000
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#define RETRAIN_WAIT_MAX_RETRIES 10
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#define RETRAIN_WAIT_USLEEP_US 2000
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#define MSI_IRQ_NUM 32
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@ -240,6 +243,17 @@ static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
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return -ETIMEDOUT;
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}
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static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie)
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{
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size_t retries;
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for (retries = 0; retries < RETRAIN_WAIT_MAX_RETRIES; ++retries) {
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if (!advk_pcie_link_up(pcie))
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break;
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udelay(RETRAIN_WAIT_USLEEP_US);
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}
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}
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static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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{
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u32 reg;
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@ -325,6 +339,14 @@ static void advk_pcie_setup_hw(struct advk_pcie *pcie)
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reg |= PIO_CTRL_ADDR_WIN_DISABLE;
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advk_writel(pcie, reg, PIO_CTRL);
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/*
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* PERST# signal could have been asserted by pinctrl subsystem before
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* probe() callback has been called, making the endpoint going into
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* fundamental reset. As required by PCI Express spec a delay for at
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* least 100ms after such a reset before link training is needed.
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*/
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msleep(PCI_PM_D3COLD_WAIT);
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/* Start link training */
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reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
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reg |= PCIE_CORE_LINK_TRAINING;
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@ -384,17 +406,16 @@ static void advk_pcie_check_pio_status(struct advk_pcie *pcie)
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static int advk_pcie_wait_pio(struct advk_pcie *pcie)
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{
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struct device *dev = &pcie->pdev->dev;
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unsigned long timeout;
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int i;
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timeout = jiffies + msecs_to_jiffies(PIO_TIMEOUT_MS);
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while (time_before(jiffies, timeout)) {
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for (i = 0; i < PIO_RETRY_CNT; i++) {
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u32 start, isr;
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start = advk_readl(pcie, PIO_START);
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isr = advk_readl(pcie, PIO_ISR);
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if (!start && isr)
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return 0;
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udelay(PIO_RETRY_DELAY);
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}
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dev_err(dev, "config read/write timed out\n");
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@ -416,7 +437,7 @@ advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
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case PCI_EXP_RTCTL: {
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u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);
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*value = (val & PCIE_MSG_PM_PME_MASK) ? PCI_EXP_RTCTL_PMEIE : 0;
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*value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE;
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return PCI_BRIDGE_EMUL_HANDLED;
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}
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@ -427,11 +448,20 @@ advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
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return PCI_BRIDGE_EMUL_HANDLED;
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}
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case PCI_EXP_LNKCTL: {
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/* u32 contains both PCI_EXP_LNKCTL and PCI_EXP_LNKSTA */
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u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) &
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~(PCI_EXP_LNKSTA_LT << 16);
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if (!advk_pcie_link_up(pcie))
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val |= (PCI_EXP_LNKSTA_LT << 16);
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*value = val;
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return PCI_BRIDGE_EMUL_HANDLED;
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}
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case PCI_CAP_LIST_ID:
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case PCI_EXP_DEVCAP:
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case PCI_EXP_DEVCTL:
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case PCI_EXP_LNKCAP:
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case PCI_EXP_LNKCTL:
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*value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
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return PCI_BRIDGE_EMUL_HANDLED;
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default:
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@ -448,15 +478,25 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
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switch (reg) {
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case PCI_EXP_DEVCTL:
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case PCI_EXP_LNKCTL:
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advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
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break;
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case PCI_EXP_RTCTL:
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new = (new & PCI_EXP_RTCTL_PMEIE) << 3;
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advk_writel(pcie, new, PCIE_ISR0_MASK_REG);
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case PCI_EXP_LNKCTL:
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advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
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if (new & PCI_EXP_LNKCTL_RL)
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advk_pcie_wait_for_retrain(pcie);
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break;
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case PCI_EXP_RTCTL: {
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/* Only mask/unmask PME interrupt */
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u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) &
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~PCIE_MSG_PM_PME_MASK;
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if ((new & PCI_EXP_RTCTL_PMEIE) == 0)
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val |= PCIE_MSG_PM_PME_MASK;
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advk_writel(pcie, val, PCIE_ISR0_MASK_REG);
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break;
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}
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case PCI_EXP_RTSTA:
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new = (new & PCI_EXP_RTSTA_PME) >> 9;
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advk_writel(pcie, new, PCIE_ISR0_REG);
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@ -480,18 +520,20 @@ static void advk_sw_pci_bridge_init(struct advk_pcie *pcie)
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{
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struct pci_bridge_emul *bridge = &pcie->bridge;
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bridge->conf.vendor = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff;
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bridge->conf.device = advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16;
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bridge->conf.vendor =
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cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff);
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bridge->conf.device =
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cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16);
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bridge->conf.class_revision =
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advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff;
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cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff);
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/* Support 32 bits I/O addressing */
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bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
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bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
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/* Support 64 bits memory pref */
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bridge->conf.pref_mem_base = PCI_PREF_RANGE_TYPE_64;
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bridge->conf.pref_mem_limit = PCI_PREF_RANGE_TYPE_64;
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bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
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bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
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/* Support interrupt A for MSI feature */
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bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
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@ -270,10 +270,10 @@ static const struct pci_bridge_reg_behavior pcie_cap_regs_behavior[] = {
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int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
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unsigned int flags)
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{
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bridge->conf.class_revision |= PCI_CLASS_BRIDGE_PCI << 16;
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bridge->conf.class_revision |= cpu_to_le32(PCI_CLASS_BRIDGE_PCI << 16);
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bridge->conf.header_type = PCI_HEADER_TYPE_BRIDGE;
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bridge->conf.cache_line_size = 0x10;
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bridge->conf.status = PCI_STATUS_CAP_LIST;
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bridge->conf.status = cpu_to_le16(PCI_STATUS_CAP_LIST);
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bridge->pci_regs_behavior = kmemdup(pci_regs_behavior,
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sizeof(pci_regs_behavior),
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GFP_KERNEL);
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@ -284,8 +284,9 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
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bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
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bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
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/* Set PCIe v2, root port, slot support */
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bridge->pcie_conf.cap = PCI_EXP_TYPE_ROOT_PORT << 4 | 2 |
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PCI_EXP_FLAGS_SLOT;
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bridge->pcie_conf.cap =
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cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4 | 2 |
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PCI_EXP_FLAGS_SLOT);
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bridge->pcie_cap_regs_behavior =
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kmemdup(pcie_cap_regs_behavior,
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sizeof(pcie_cap_regs_behavior),
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@ -327,7 +328,7 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
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int reg = where & ~3;
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pci_bridge_emul_read_status_t (*read_op)(struct pci_bridge_emul *bridge,
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int reg, u32 *value);
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u32 *cfgspace;
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__le32 *cfgspace;
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const struct pci_bridge_reg_behavior *behavior;
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if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) {
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@ -343,11 +344,11 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
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if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
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reg -= PCI_CAP_PCIE_START;
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read_op = bridge->ops->read_pcie;
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cfgspace = (u32 *) &bridge->pcie_conf;
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cfgspace = (__le32 *) &bridge->pcie_conf;
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behavior = bridge->pcie_cap_regs_behavior;
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} else {
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read_op = bridge->ops->read_base;
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cfgspace = (u32 *) &bridge->conf;
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cfgspace = (__le32 *) &bridge->conf;
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behavior = bridge->pci_regs_behavior;
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}
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@ -357,7 +358,7 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
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ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
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if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED)
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*value = cfgspace[reg / 4];
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*value = le32_to_cpu(cfgspace[reg / 4]);
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/*
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* Make sure we never return any reserved bit with a value
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@ -387,7 +388,7 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
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int mask, ret, old, new, shift;
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void (*write_op)(struct pci_bridge_emul *bridge, int reg,
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u32 old, u32 new, u32 mask);
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u32 *cfgspace;
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__le32 *cfgspace;
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const struct pci_bridge_reg_behavior *behavior;
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if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END)
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@ -414,11 +415,11 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
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if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
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reg -= PCI_CAP_PCIE_START;
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write_op = bridge->ops->write_pcie;
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cfgspace = (u32 *) &bridge->pcie_conf;
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cfgspace = (__le32 *) &bridge->pcie_conf;
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behavior = bridge->pcie_cap_regs_behavior;
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} else {
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write_op = bridge->ops->write_base;
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cfgspace = (u32 *) &bridge->conf;
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cfgspace = (__le32 *) &bridge->conf;
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behavior = bridge->pci_regs_behavior;
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}
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@ -431,7 +432,7 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
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/* Clear the W1C bits */
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new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
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cfgspace[reg / 4] = new;
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cfgspace[reg / 4] = cpu_to_le32(new);
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if (write_op)
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write_op(bridge, reg, old, new, mask);
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@ -6,65 +6,65 @@
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/* PCI configuration space of a PCI-to-PCI bridge. */
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struct pci_bridge_emul_conf {
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u16 vendor;
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u16 device;
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u16 command;
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u16 status;
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u32 class_revision;
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__le16 vendor;
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__le16 device;
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__le16 command;
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__le16 status;
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__le32 class_revision;
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u8 cache_line_size;
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u8 latency_timer;
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u8 header_type;
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u8 bist;
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u32 bar[2];
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__le32 bar[2];
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u8 primary_bus;
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u8 secondary_bus;
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u8 subordinate_bus;
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u8 secondary_latency_timer;
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u8 iobase;
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u8 iolimit;
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u16 secondary_status;
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u16 membase;
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u16 memlimit;
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u16 pref_mem_base;
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u16 pref_mem_limit;
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u32 prefbaseupper;
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u32 preflimitupper;
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u16 iobaseupper;
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u16 iolimitupper;
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__le16 secondary_status;
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__le16 membase;
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__le16 memlimit;
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__le16 pref_mem_base;
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__le16 pref_mem_limit;
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__le32 prefbaseupper;
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__le32 preflimitupper;
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__le16 iobaseupper;
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__le16 iolimitupper;
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u8 capabilities_pointer;
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u8 reserve[3];
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u32 romaddr;
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__le32 romaddr;
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u8 intline;
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u8 intpin;
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u16 bridgectrl;
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__le16 bridgectrl;
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};
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/* PCI configuration space of the PCIe capabilities */
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struct pci_bridge_emul_pcie_conf {
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u8 cap_id;
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u8 next;
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u16 cap;
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u32 devcap;
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u16 devctl;
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u16 devsta;
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u32 lnkcap;
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u16 lnkctl;
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u16 lnksta;
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u32 slotcap;
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u16 slotctl;
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u16 slotsta;
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u16 rootctl;
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u16 rsvd;
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u32 rootsta;
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u32 devcap2;
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u16 devctl2;
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u16 devsta2;
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u32 lnkcap2;
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u16 lnkctl2;
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u16 lnksta2;
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u32 slotcap2;
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u16 slotctl2;
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u16 slotsta2;
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__le16 cap;
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__le32 devcap;
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__le16 devctl;
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__le16 devsta;
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__le32 lnkcap;
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__le16 lnkctl;
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__le16 lnksta;
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__le32 slotcap;
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__le16 slotctl;
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__le16 slotsta;
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__le16 rootctl;
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__le16 rsvd;
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__le32 rootsta;
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__le32 devcap2;
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__le16 devctl2;
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__le16 devsta2;
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__le32 lnkcap2;
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__le16 lnkctl2;
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__le16 lnksta2;
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__le32 slotcap2;
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__le16 slotctl2;
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__le16 slotsta2;
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};
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struct pci_bridge_emul;
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|
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Loading…
Reference in New Issue
Block a user