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ARM: dts: hisilicon: fix errors detected by snps-dw-apb-uart.yaml

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1. Change node name to match '^serial(@[0-9a-f,]+)*$'
2. Change clock-names to "baudclk", "apb_pclk". Both of them use the same
   clock.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This commit is contained in:
Zhen Lei
2020-10-12 14:12:16 +08:00
committed by Wei Xu
parent 3650b228f8
commit 30ea026e33
3 changed files with 16 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
arch/arm/boot/dts/hip01.dtsi
View File

@@ -41,41 +41,41 @@
compatible = "simple-bus"; compatible = "simple-bus";
ranges; ranges;
uart0: uart@10001000 { uart0: serial@10001000 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x10001000 0x1000>; reg = <0x10001000 0x1000>;
clocks = <&hisi_refclk144mhz>; clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
clock-names = "apb_pclk"; clock-names = "baudclk", "apb_pclk";
reg-shift = <2>; reg-shift = <2>;
interrupts = <0 32 4>; interrupts = <0 32 4>;
status = "disabled"; status = "disabled";
}; };
uart1: uart@10002000 { uart1: serial@10002000 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x10002000 0x1000>; reg = <0x10002000 0x1000>;
clocks = <&hisi_refclk144mhz>; clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
clock-names = "apb_pclk"; clock-names = "baudclk", "apb_pclk";
reg-shift = <2>; reg-shift = <2>;
interrupts = <0 33 4>; interrupts = <0 33 4>;
status = "disabled"; status = "disabled";
}; };
uart2: uart@10003000 { uart2: serial@10003000 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x10003000 0x1000>; reg = <0x10003000 0x1000>;
clocks = <&hisi_refclk144mhz>; clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
clock-names = "apb_pclk"; clock-names = "baudclk", "apb_pclk";
reg-shift = <2>; reg-shift = <2>;
interrupts = <0 34 4>; interrupts = <0 34 4>;
status = "disabled"; status = "disabled";
}; };
uart3: uart@10006000 { uart3: serial@10006000 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x10006000 0x1000>; reg = <0x10006000 0x1000>;
clocks = <&hisi_refclk144mhz>; clocks = <&hisi_refclk144mhz>, <&hisi_refclk144mhz>;
clock-names = "apb_pclk"; clock-names = "baudclk", "apb_pclk";
reg-shift = <2>; reg-shift = <2>;
interrupts = <0 4 4>; interrupts = <0 4 4>;
status = "disabled"; status = "disabled";

2
arch/arm/boot/dts/hip04-d01.dts
View File

@@ -22,7 +22,7 @@
}; };
soc { soc {
uart0: uart@4007000 { uart0: serial@4007000 {
status = "ok"; status = "ok";
}; };
}; };

6
arch/arm/boot/dts/hip04.dtsi
View File

@@ -250,12 +250,12 @@
<0 79 4>; <0 79 4>;
}; };
uart0: uart@4007000 { uart0: serial@4007000 {
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x4007000 0x1000>; reg = <0x4007000 0x1000>;
interrupts = <0 381 4>; interrupts = <0 381 4>;
clocks = <&clk_168m>; clocks = <&clk_168m>, <&clk_168m>;
clock-names = "uartclk"; clock-names = "baudclk", "apb_pclk";
reg-shift = <2>; reg-shift = <2>;
status = "disabled"; status = "disabled";
}; };