forked from Minki/linux
Renesas ARM based SoC boot cleanup for v3.11
Work by Magnus Damm and others to clean up the boot of and move things closer to supporting multi-arch. As a side effect of this work it was decided to remove support for two boards, Bonito and AP4EVB. Those patches are included in this series as they depend on earlier patches in the series. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJRvsCNAAoJENfPZGlqN0++JDAP/ROJOKamUa2/b34ebTVq53Os 4u9twxIGRQ/HJzpFZSV4ak/M9G4sl19+V8s46qaKnCwoKlc7GZW/qNqIEgN9cDrz ht9mbcJ8BTtinUo1nxzIFMOWB0WltSvmlxNeKm6OxG+BXu/lJ6BoPrhoO/qc49kc eHYAHdVDYIlr+kMlAw8HIbpJqsMiQviq8b8S8aqoW1QSHHlTgL2GNoQH/tli/r8m XNei4RrTABUq1r04oOBN+0FQKyn5lWgq5hMtdWsP8VvhaW6kwX3Hwl7f+dn/xDna XB6J3z+/jFTs6aR0Njm8LlJv2Q4SFJE595z/6j9upWS+e7pG+et+SMVSwPCeKzr2 pcCfFpce9e8KIPVUdKlZqMw1BMO/ok1BnpTtdBuAZW2zriW0EeUe0SgFk8GzHC3E p+JqgeEcbN0lO6WKJ9YfPH6WSt8JUYDse3ldxBlf3pGezaV8G/hccZFnOc0BHXV+ 5cTGeJpFEdFcNWvxKvJytehQLTl05KvGyE52AnDLrjq1aIVflYUzTlccm14PpSAC kTNqEpUd3qIcINi6Udt5WPRIMj6gIXl6zLAkqxufcIhYW86E2DejnWcxo5UbLXyH 30K0BbY90oVc2hJKu32HBu11kI6RlIa9qjBHYI8WAZ+uGplHqD2WaBmXojFElrbH JVDkg2BtreVa5q4Xot0L =1+Oa -----END PGP SIGNATURE----- Merge tag 'renesas-cleanup-boot-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc From Simon Horman: Renesas ARM based SoC boot cleanup for v3.11 Work by Magnus Damm and others to clean up the boot of and move things closer to supporting multi-arch. As a side effect of this work it was decided to remove support for two boards, Bonito and AP4EVB. Those patches are included in this series as they depend on earlier patches in the series. * tag 'renesas-cleanup-boot-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: Remove Bonito board support ARM: shmobile: Remove AP4EVB board support ARM: shmobile: Remove mach/memory.h ARM: shmobile: Remove MEMORY_START/SIZE ARM: shmobile: Enable ARM_PATCH_PHYS_VIRT ARM: shmobile: Remove old SCU boot code ARM: shmobile: EMEV2 SMP with SCU boot fn and args ARM: shmobile: sh73a0 SMP with SCU boot fn and args ARM: shmobile: r8a7779 SMP with SCU boot fn and args ARM: shmobile: Add SCU boot function using argument ARM: shmobile: Add SMP boot function and argument ARM: shmobile: Rework sh7372 sleep code to use virt_to_phys() ARM: shmobile: Remove romImage CONFIG_MEMORY_START ARM: shmobile: Let romImage rely on default ATAGS ARM: shmobile: uImage load address rework Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
30e544612c
@ -636,6 +636,7 @@ config ARCH_MSM
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config ARCH_SHMOBILE
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bool "Renesas SH-Mobile / R-Mobile"
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select ARM_PATCH_PHYS_VIRT
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select CLKDEV_LOOKUP
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select GENERIC_CLOCKEVENTS
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select HAVE_ARM_SCU if SMP
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@ -645,7 +646,6 @@ config ARCH_SHMOBILE
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select HAVE_SMP
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select MIGHT_HAVE_CACHE_L2X0
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select MULTI_IRQ_HANDLER
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select NEED_MACH_MEMORY_H
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select NO_IOPORT
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select PINCTRL
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select PM_GENERIC_DOMAINS if PM
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@ -46,7 +46,7 @@ __image_start:
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__image_end:
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.long _got_end
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__load_base:
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.long CONFIG_MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM
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.long MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM
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__loaded:
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.long __continue
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.align
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@ -55,26 +55,9 @@ __tmp_stack:
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__continue:
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#endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */
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b 1f
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__atags:@ tag #1
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.long 12 @ tag->hdr.size = tag_size(tag_core);
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.long 0x54410001 @ tag->hdr.tag = ATAG_CORE;
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.long 0 @ tag->u.core.flags = 0;
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.long 0 @ tag->u.core.pagesize = 0;
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.long 0 @ tag->u.core.rootdev = 0;
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@ tag #2
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.long 8 @ tag->hdr.size = tag_size(tag_mem32);
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.long 0x54410002 @ tag->hdr.tag = ATAG_MEM;
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.long CONFIG_MEMORY_SIZE @ tag->u.mem.size = CONFIG_MEMORY_SIZE;
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.long CONFIG_MEMORY_START @ @ tag->u.mem.start = CONFIG_MEMORY_START;
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@ tag #3
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.long 0 @ tag->hdr.size = 0
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.long 0 @ tag->hdr.tag = ATAG_NONE;
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1:
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/* Set board ID necessary for boot */
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ldr r7, 1f @ Set machine type register
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adr r8, __atags @ Set atag register
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mov r8, #0 @ pass null pointer as atag
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b 2f
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1 : .long MACH_TYPE
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@ -1,56 +0,0 @@
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CONFIG_EXPERIMENTAL=y
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CONFIG_SYSVIPC=y
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CONFIG_IKCONFIG=y
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CONFIG_IKCONFIG_PROC=y
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CONFIG_LOG_BUF_SHIFT=16
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_SLAB=y
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# CONFIG_BLK_DEV_BSG is not set
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# CONFIG_IOSCHED_DEADLINE is not set
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# CONFIG_IOSCHED_CFQ is not set
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CONFIG_ARCH_SHMOBILE=y
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CONFIG_ARCH_SH7372=y
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CONFIG_MACH_AP4EVB=y
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CONFIG_AEABI=y
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# CONFIG_OABI_COMPAT is not set
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CONFIG_ZBOOT_ROM_TEXT=0x0
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CONFIG_ZBOOT_ROM_BSS=0x0
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CONFIG_CMDLINE="console=ttySC0,115200 earlyprintk=sh-sci.0,115200"
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CONFIG_KEXEC=y
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CONFIG_PM=y
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# CONFIG_SUSPEND is not set
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CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
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# CONFIG_FIRMWARE_IN_KERNEL is not set
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CONFIG_MTD=y
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CONFIG_MTD_CONCAT=y
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CONFIG_MTD_PARTITIONS=y
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CONFIG_MTD_CHAR=y
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CONFIG_MTD_BLOCK=y
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CONFIG_MTD_CFI=y
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CONFIG_MTD_CFI_INTELEXT=y
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_NAND=y
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# CONFIG_BLK_DEV is not set
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# CONFIG_MISC_DEVICES is not set
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# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
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# CONFIG_INPUT_KEYBOARD is not set
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# CONFIG_INPUT_MOUSE is not set
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# CONFIG_SERIO is not set
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CONFIG_SERIAL_SH_SCI=y
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CONFIG_SERIAL_SH_SCI_NR_UARTS=8
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CONFIG_SERIAL_SH_SCI_CONSOLE=y
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# CONFIG_LEGACY_PTYS is not set
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# CONFIG_HW_RANDOM is not set
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# CONFIG_HWMON is not set
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# CONFIG_VGA_CONSOLE is not set
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# CONFIG_HID_SUPPORT is not set
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# CONFIG_USB_SUPPORT is not set
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# CONFIG_DNOTIFY is not set
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CONFIG_TMPFS=y
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# CONFIG_MISC_FILESYSTEMS is not set
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CONFIG_MAGIC_SYSRQ=y
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CONFIG_DEBUG_KERNEL=y
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# CONFIG_DETECT_SOFTLOCKUP is not set
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# CONFIG_RCU_CPU_STALL_DETECTOR is not set
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# CONFIG_FTRACE is not set
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# CONFIG_CRC32 is not set
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@ -1,72 +0,0 @@
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CONFIG_EXPERIMENTAL=y
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CONFIG_SYSVIPC=y
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CONFIG_IKCONFIG=y
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CONFIG_IKCONFIG_PROC=y
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CONFIG_LOG_BUF_SHIFT=16
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# CONFIG_UTS_NS is not set
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# CONFIG_IPC_NS is not set
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# CONFIG_USER_NS is not set
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# CONFIG_PID_NS is not set
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_INITRAMFS_SOURCE=""
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CONFIG_CC_OPTIMIZE_FOR_SIZE=y
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CONFIG_SLAB=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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CONFIG_MODULE_FORCE_UNLOAD=y
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# CONFIG_BLK_DEV_BSG is not set
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# CONFIG_IOSCHED_DEADLINE is not set
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# CONFIG_IOSCHED_CFQ is not set
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CONFIG_ARCH_SHMOBILE=y
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CONFIG_ARCH_R8A7740=y
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CONFIG_MACH_BONITO=y
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# CONFIG_SH_TIMER_TMU is not set
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CONFIG_AEABI=y
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# CONFIG_OABI_COMPAT is not set
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CONFIG_FORCE_MAX_ZONEORDER=12
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CONFIG_ZBOOT_ROM_TEXT=0x0
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CONFIG_ZBOOT_ROM_BSS=0x0
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CONFIG_CMDLINE="console=ttySC5,115200 earlyprintk=sh-sci.5,115200 ignore_loglevel"
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CONFIG_KEXEC=y
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# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
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# CONFIG_SUSPEND is not set
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CONFIG_PM_RUNTIME=y
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CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
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# CONFIG_FIRMWARE_IN_KERNEL is not set
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CONFIG_MTD=y
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CONFIG_MTD_CHAR=y
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CONFIG_MTD_BLOCK=y
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CONFIG_MTD_CFI=y
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CONFIG_MTD_CFI_ADV_OPTIONS=y
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CONFIG_MTD_CFI_INTELEXT=y
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CONFIG_MTD_PHYSMAP=y
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CONFIG_MTD_ARM_INTEGRATOR=y
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CONFIG_MTD_BLOCK2MTD=y
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CONFIG_SCSI=y
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CONFIG_BLK_DEV_SD=y
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# CONFIG_SCSI_LOWLEVEL is not set
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# CONFIG_INPUT_KEYBOARD is not set
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# CONFIG_INPUT_MOUSE is not set
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# CONFIG_LEGACY_PTYS is not set
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CONFIG_SERIAL_SH_SCI=y
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CONFIG_SERIAL_SH_SCI_NR_UARTS=9
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CONFIG_SERIAL_SH_SCI_CONSOLE=y
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# CONFIG_HW_RANDOM is not set
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CONFIG_I2C=y
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CONFIG_I2C_CHARDEV=y
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CONFIG_I2C_SH_MOBILE=y
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CONFIG_GPIO_SYSFS=y
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# CONFIG_HWMON is not set
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# CONFIG_MFD_SUPPORT is not set
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# CONFIG_HID_SUPPORT is not set
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# CONFIG_USB_SUPPORT is not set
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CONFIG_UIO=y
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CONFIG_UIO_PDRV=y
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CONFIG_UIO_PDRV_GENIRQ=y
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# CONFIG_DNOTIFY is not set
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# CONFIG_INOTIFY_USER is not set
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CONFIG_TMPFS=y
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# CONFIG_MISC_FILESYSTEMS is not set
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# CONFIG_ENABLE_WARN_DEPRECATED is not set
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# CONFIG_ENABLE_MUST_CHECK is not set
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# CONFIG_ARM_UNWIND is not set
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@ -71,27 +71,6 @@ config ARCH_EMEV2
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comment "SH-Mobile Board Type"
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config MACH_AP4EVB
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bool "AP4EVB board"
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depends on ARCH_SH7372
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select ARCH_REQUIRE_GPIOLIB
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select REGULATOR_FIXED_VOLTAGE if REGULATOR
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select SH_LCD_MIPI_DSI
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select SND_SOC_AK4642 if SND_SIMPLE_CARD
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choice
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prompt "AP4EVB LCD panel selection"
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default AP4EVB_QHD
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depends on MACH_AP4EVB
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config AP4EVB_QHD
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bool "MIPI-DSI QHD (960x540)"
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config AP4EVB_WVGA
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bool "Parallel WVGA (800x480)"
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endchoice
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config MACH_AG5EVM
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bool "AG5EVM board"
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depends on ARCH_SH73A0
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@ -118,12 +97,6 @@ config MACH_KOTA2
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select ARCH_REQUIRE_GPIOLIB
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select REGULATOR_FIXED_VOLTAGE if REGULATOR
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config MACH_BONITO
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bool "bonito board"
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depends on ARCH_R8A7740
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select ARCH_REQUIRE_GPIOLIB
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select REGULATOR_FIXED_VOLTAGE if REGULATOR
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config MACH_ARMADILLO800EVA
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bool "Armadillo-800 EVA board"
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depends on ARCH_R8A7740
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@ -199,37 +172,6 @@ config CPU_HAS_INTEVT
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bool
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default y
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menu "Memory configuration"
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config MEMORY_START
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hex "Physical memory start address"
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default "0x40000000" if MACH_AP4EVB || MACH_AG5EVM || \
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MACH_MACKEREL || MACH_BONITO || \
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MACH_ARMADILLO800EVA || MACH_APE6EVM || \
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MACH_LAGER
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default "0x41000000" if MACH_KOTA2
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default "0x00000000"
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---help---
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Tweak this only when porting to a new machine which does not
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already have a defconfig. Changing it from the known correct
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value on any of the known systems will only lead to disaster.
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config MEMORY_SIZE
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hex "Physical memory size"
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default "0x80000000" if MACH_LAGER
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default "0x40000000" if MACH_APE6EVM
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default "0x20000000" if MACH_AG5EVM || MACH_BONITO || \
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MACH_ARMADILLO800EVA
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default "0x1e000000" if MACH_KOTA2
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default "0x10000000" if MACH_AP4EVB || MACH_MACKEREL
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default "0x04000000"
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help
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This sets the default memory size assumed by your kernel. It can
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be overridden as normal by the 'mem=' argument on the kernel command
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line.
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endmenu
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menu "Timer and clock configuration"
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config SHMOBILE_TIMER_HZ
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@ -35,12 +35,10 @@ obj-$(CONFIG_ARCH_R8A7779) += pm-r8a7779.o
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obj-$(CONFIG_ARCH_SH73A0) += pm-sh73a0.o
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# Board objects
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obj-$(CONFIG_MACH_AP4EVB) += board-ap4evb.o
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obj-$(CONFIG_MACH_AG5EVM) += board-ag5evm.o
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obj-$(CONFIG_MACH_APE6EVM) += board-ape6evm.o
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obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
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obj-$(CONFIG_MACH_KOTA2) += board-kota2.o
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obj-$(CONFIG_MACH_BONITO) += board-bonito.o
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obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
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obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
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obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o
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@ -1,6 +1,20 @@
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__ZRELADDR := $(shell /bin/bash -c 'printf "0x%08x" \
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$$[$(CONFIG_MEMORY_START) + 0x8000]')
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# per-board load address for uImage
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loadaddr-y :=
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loadaddr-$(CONFIG_MACH_AG5EVM) += 0x40008000
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loadaddr-$(CONFIG_MACH_APE6EVM) += 0x40008000
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loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000
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loadaddr-$(CONFIG_MACH_ARMADILLO800EVA_REFERENCE) += 0x40008000
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loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
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loadaddr-$(CONFIG_MACH_KOTA2) += 0x41008000
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loadaddr-$(CONFIG_MACH_KZM9D) += 0x40008000
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loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
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loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
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loadaddr-$(CONFIG_MACH_LAGER) += 0x40008000
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loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000
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loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
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loadaddr-$(CONFIG_MACH_MARZEN_REFERENCE) += 0x60008000
|
||||
|
||||
__ZRELADDR := $(sort $(loadaddr-y))
|
||||
zreladdr-y += $(__ZRELADDR)
|
||||
|
||||
# Unsupported legacy stuff
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,502 +0,0 @@
|
||||
/*
|
||||
* bonito board support
|
||||
*
|
||||
* Copyright (C) 2011 Renesas Solutions Corp.
|
||||
* Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/smsc911x.h>
|
||||
#include <linux/videodev2.h>
|
||||
#include <mach/common.h>
|
||||
#include <asm/mach-types.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
#include <mach/r8a7740.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <video/sh_mobile_lcdc.h>
|
||||
|
||||
/*
|
||||
* CS Address device note
|
||||
*----------------------------------------------------------------
|
||||
* 0 0x0000_0000 NOR Flash (64MB) SW12 : bit3 = OFF
|
||||
* 2 0x0800_0000 ExtNOR (64MB) SW12 : bit3 = OFF
|
||||
* 4 -
|
||||
* 5A -
|
||||
* 5B 0x1600_0000 SRAM (8MB)
|
||||
* 6 0x1800_0000 FPGA (64K)
|
||||
* 0x1801_0000 Ether (4KB)
|
||||
* 0x1801_1000 USB (4KB)
|
||||
*/
|
||||
|
||||
/*
|
||||
* SW12
|
||||
*
|
||||
* bit1 bit2 bit3
|
||||
*----------------------------------------------------------------------------
|
||||
* ON NOR WriteProtect NAND WriteProtect CS0 ExtNOR / CS2 NOR
|
||||
* OFF NOR Not WriteProtect NAND Not WriteProtect CS0 NOR / CS2 ExtNOR
|
||||
*/
|
||||
|
||||
/*
|
||||
* SCIFA5 (CN42)
|
||||
*
|
||||
* S38.3 = ON
|
||||
* S39.6 = ON
|
||||
* S43.1 = ON
|
||||
*/
|
||||
|
||||
/*
|
||||
* LCDC0 (CN3/CN4/CN7)
|
||||
*
|
||||
* S38.1 = OFF
|
||||
* S38.2 = OFF
|
||||
*/
|
||||
|
||||
/* Dummy supplies, where voltage doesn't matter */
|
||||
static struct regulator_consumer_supply dummy_supplies[] = {
|
||||
REGULATOR_SUPPLY("vddvario", "smsc911x"),
|
||||
REGULATOR_SUPPLY("vdd33a", "smsc911x"),
|
||||
};
|
||||
|
||||
/*
|
||||
* FPGA
|
||||
*/
|
||||
#define IRQSR0 0x0020
|
||||
#define IRQSR1 0x0022
|
||||
#define IRQMR0 0x0030
|
||||
#define IRQMR1 0x0032
|
||||
#define BUSSWMR1 0x0070
|
||||
#define BUSSWMR2 0x0072
|
||||
#define BUSSWMR3 0x0074
|
||||
#define BUSSWMR4 0x0076
|
||||
|
||||
#define LCDCR 0x10B4
|
||||
#define DEVRSTCR1 0x10D0
|
||||
#define DEVRSTCR2 0x10D2
|
||||
#define A1MDSR 0x10E0
|
||||
#define BVERR 0x1100
|
||||
|
||||
/* FPGA IRQ */
|
||||
#define FPGA_IRQ_BASE (512)
|
||||
#define FPGA_IRQ0 (FPGA_IRQ_BASE)
|
||||
#define FPGA_IRQ1 (FPGA_IRQ_BASE + 16)
|
||||
#define FPGA_ETH_IRQ (FPGA_IRQ0 + 15)
|
||||
static u16 bonito_fpga_read(u32 offset)
|
||||
{
|
||||
return __raw_readw(IOMEM(0xf0003000) + offset);
|
||||
}
|
||||
|
||||
static void bonito_fpga_write(u32 offset, u16 val)
|
||||
{
|
||||
__raw_writew(val, IOMEM(0xf0003000) + offset);
|
||||
}
|
||||
|
||||
static void bonito_fpga_irq_disable(struct irq_data *data)
|
||||
{
|
||||
unsigned int irq = data->irq;
|
||||
u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
|
||||
int shift = irq % 16;
|
||||
|
||||
bonito_fpga_write(addr, bonito_fpga_read(addr) | (1 << shift));
|
||||
}
|
||||
|
||||
static void bonito_fpga_irq_enable(struct irq_data *data)
|
||||
{
|
||||
unsigned int irq = data->irq;
|
||||
u32 addr = (irq < 1016) ? IRQMR0 : IRQMR1;
|
||||
int shift = irq % 16;
|
||||
|
||||
bonito_fpga_write(addr, bonito_fpga_read(addr) & ~(1 << shift));
|
||||
}
|
||||
|
||||
static struct irq_chip bonito_fpga_irq_chip __read_mostly = {
|
||||
.name = "bonito FPGA",
|
||||
.irq_mask = bonito_fpga_irq_disable,
|
||||
.irq_unmask = bonito_fpga_irq_enable,
|
||||
};
|
||||
|
||||
static void bonito_fpga_irq_demux(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
u32 val = bonito_fpga_read(IRQSR1) << 16 |
|
||||
bonito_fpga_read(IRQSR0);
|
||||
u32 mask = bonito_fpga_read(IRQMR1) << 16 |
|
||||
bonito_fpga_read(IRQMR0);
|
||||
|
||||
int i;
|
||||
|
||||
val &= ~mask;
|
||||
|
||||
for (i = 0; i < 32; i++) {
|
||||
if (!(val & (1 << i)))
|
||||
continue;
|
||||
|
||||
generic_handle_irq(FPGA_IRQ_BASE + i);
|
||||
}
|
||||
}
|
||||
|
||||
static void bonito_fpga_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
bonito_fpga_write(IRQMR0, 0xffff); /* mask all */
|
||||
bonito_fpga_write(IRQMR1, 0xffff); /* mask all */
|
||||
|
||||
/* Device reset */
|
||||
bonito_fpga_write(DEVRSTCR1,
|
||||
(1 << 2)); /* Eth */
|
||||
|
||||
/* FPGA irq require special handling */
|
||||
for (i = FPGA_IRQ_BASE; i < FPGA_IRQ_BASE + 32; i++) {
|
||||
irq_set_chip_and_handler_name(i, &bonito_fpga_irq_chip,
|
||||
handle_level_irq, "level");
|
||||
set_irq_flags(i, IRQF_VALID); /* yuck */
|
||||
}
|
||||
|
||||
irq_set_chained_handler(evt2irq(0x0340), bonito_fpga_irq_demux);
|
||||
irq_set_irq_type(evt2irq(0x0340), IRQ_TYPE_LEVEL_LOW);
|
||||
}
|
||||
|
||||
/*
|
||||
* PMIC settings
|
||||
*
|
||||
* FIXME
|
||||
*
|
||||
* bonito board needs some settings by pmic which use i2c access.
|
||||
* pmic settings use device_initcall() here for use it.
|
||||
*/
|
||||
static __u8 *pmic_settings = NULL;
|
||||
static __u8 pmic_do_2A[] = {
|
||||
0x1C, 0x09,
|
||||
0x1A, 0x80,
|
||||
0xff, 0xff,
|
||||
};
|
||||
|
||||
static int __init pmic_init(void)
|
||||
{
|
||||
struct i2c_adapter *a = i2c_get_adapter(0);
|
||||
struct i2c_msg msg;
|
||||
__u8 buf[2];
|
||||
int i, ret;
|
||||
|
||||
if (!pmic_settings)
|
||||
return 0;
|
||||
if (!a)
|
||||
return 0;
|
||||
|
||||
msg.addr = 0x46;
|
||||
msg.buf = buf;
|
||||
msg.len = 2;
|
||||
msg.flags = 0;
|
||||
|
||||
for (i = 0; ; i += 2) {
|
||||
buf[0] = pmic_settings[i + 0];
|
||||
buf[1] = pmic_settings[i + 1];
|
||||
|
||||
if ((0xff == buf[0]) && (0xff == buf[1]))
|
||||
break;
|
||||
|
||||
ret = i2c_transfer(a, &msg, 1);
|
||||
if (ret < 0) {
|
||||
pr_err("i2c transfer fail\n");
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
device_initcall(pmic_init);
|
||||
|
||||
/*
|
||||
* LCDC0
|
||||
*/
|
||||
static const struct fb_videomode lcdc0_mode = {
|
||||
.name = "WVGA Panel",
|
||||
.xres = 800,
|
||||
.yres = 480,
|
||||
.left_margin = 88,
|
||||
.right_margin = 40,
|
||||
.hsync_len = 128,
|
||||
.upper_margin = 20,
|
||||
.lower_margin = 5,
|
||||
.vsync_len = 5,
|
||||
.sync = 0,
|
||||
};
|
||||
|
||||
static struct sh_mobile_lcdc_info lcdc0_info = {
|
||||
.clock_source = LCDC_CLK_BUS,
|
||||
.ch[0] = {
|
||||
.chan = LCDC_CHAN_MAINLCD,
|
||||
.fourcc = V4L2_PIX_FMT_RGB565,
|
||||
.interface_type = RGB24,
|
||||
.clock_divider = 5,
|
||||
.flags = 0,
|
||||
.lcd_modes = &lcdc0_mode,
|
||||
.num_modes = 1,
|
||||
.panel_cfg = {
|
||||
.width = 152,
|
||||
.height = 91,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource lcdc0_resources[] = {
|
||||
[0] = {
|
||||
.name = "LCDC0",
|
||||
.start = 0xfe940000,
|
||||
.end = 0xfe943fff,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = intcs_evt2irq(0x0580),
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device lcdc0_device = {
|
||||
.name = "sh_mobile_lcdc_fb",
|
||||
.id = 0,
|
||||
.resource = lcdc0_resources,
|
||||
.num_resources = ARRAY_SIZE(lcdc0_resources),
|
||||
.dev = {
|
||||
.platform_data = &lcdc0_info,
|
||||
.coherent_dma_mask = ~0,
|
||||
},
|
||||
};
|
||||
|
||||
static const struct pinctrl_map lcdc0_pinctrl_map[] = {
|
||||
/* LCD0 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
|
||||
"lcd0_data24_1", "lcd0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
|
||||
"lcd0_lclk_1", "lcd0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
|
||||
"lcd0_sync", "lcd0"),
|
||||
};
|
||||
|
||||
/*
|
||||
* SMSC 9221
|
||||
*/
|
||||
static struct resource smsc_resources[] = {
|
||||
[0] = {
|
||||
.start = 0x18010000,
|
||||
.end = 0x18011000 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = FPGA_ETH_IRQ,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static struct smsc911x_platform_config smsc_platdata = {
|
||||
.flags = SMSC911X_USE_16BIT,
|
||||
.phy_interface = PHY_INTERFACE_MODE_MII,
|
||||
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
|
||||
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
|
||||
};
|
||||
|
||||
static struct platform_device smsc_device = {
|
||||
.name = "smsc911x",
|
||||
.dev = {
|
||||
.platform_data = &smsc_platdata,
|
||||
},
|
||||
.resource = smsc_resources,
|
||||
.num_resources = ARRAY_SIZE(smsc_resources),
|
||||
};
|
||||
|
||||
/*
|
||||
* base board devices
|
||||
*/
|
||||
static struct platform_device *bonito_base_devices[] __initdata = {
|
||||
&lcdc0_device,
|
||||
&smsc_device,
|
||||
};
|
||||
|
||||
/*
|
||||
* map I/O
|
||||
*/
|
||||
static struct map_desc bonito_io_desc[] __initdata = {
|
||||
/*
|
||||
* for FPGA (0x1800000-0x19ffffff)
|
||||
* 0x18000000-0x18002000 -> 0xf0003000-0xf0005000
|
||||
*/
|
||||
{
|
||||
.virtual = 0xf0003000,
|
||||
.pfn = __phys_to_pfn(0x18000000),
|
||||
.length = PAGE_SIZE * 2,
|
||||
.type = MT_DEVICE_NONSHARED
|
||||
}
|
||||
};
|
||||
|
||||
static void __init bonito_map_io(void)
|
||||
{
|
||||
r8a7740_map_io();
|
||||
iotable_init(bonito_io_desc, ARRAY_SIZE(bonito_io_desc));
|
||||
}
|
||||
|
||||
/*
|
||||
* board init
|
||||
*/
|
||||
#define BIT_ON(sw, bit) (sw & (1 << bit))
|
||||
#define BIT_OFF(sw, bit) (!(sw & (1 << bit)))
|
||||
|
||||
#define VCCQ1CR IOMEM(0xE6058140)
|
||||
#define VCCQ1LCDCR IOMEM(0xE6058186)
|
||||
|
||||
/*
|
||||
* HACK: The FPGA mappings should be associated with the FPGA device, but we
|
||||
* don't have one at the moment. Associate them with the PFC device to make
|
||||
* sure they will be applied.
|
||||
*/
|
||||
static const struct pinctrl_map fpga_pinctrl_map[] = {
|
||||
/* FPGA */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
|
||||
"bsc_cs5a_0", "bsc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
|
||||
"bsc_cs5b", "bsc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
|
||||
"bsc_cs6a", "bsc"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("pfc-r8a7740", "pfc-r8a7740",
|
||||
"intc_irq10", "intc"),
|
||||
};
|
||||
|
||||
static const struct pinctrl_map scifa5_pinctrl_map[] = {
|
||||
/* SCIFA5 */
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.5", "pfc-r8a7740",
|
||||
"scifa5_data_2", "scifa5"),
|
||||
};
|
||||
|
||||
static void __init bonito_init(void)
|
||||
{
|
||||
u16 val;
|
||||
|
||||
regulator_register_fixed(0, dummy_supplies, ARRAY_SIZE(dummy_supplies));
|
||||
|
||||
pinctrl_register_mappings(fpga_pinctrl_map,
|
||||
ARRAY_SIZE(fpga_pinctrl_map));
|
||||
r8a7740_pinmux_init();
|
||||
bonito_fpga_init();
|
||||
|
||||
pmic_settings = pmic_do_2A;
|
||||
|
||||
/*
|
||||
* core board settings
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
/* Early BRESP enable, Shared attribute override enable, 32K*8way */
|
||||
l2x0_init(IOMEM(0xf0002000), 0x40440000, 0x82000fff);
|
||||
#endif
|
||||
|
||||
r8a7740_add_standard_devices();
|
||||
|
||||
/*
|
||||
* base board settings
|
||||
*/
|
||||
gpio_request_one(176, GPIOF_IN, NULL);
|
||||
if (!gpio_get_value(176)) {
|
||||
u16 bsw2;
|
||||
u16 bsw3;
|
||||
u16 bsw4;
|
||||
|
||||
val = bonito_fpga_read(BVERR);
|
||||
pr_info("bonito version: cpu %02x, base %02x\n",
|
||||
((val >> 8) & 0xFF),
|
||||
((val >> 0) & 0xFF));
|
||||
|
||||
bsw2 = bonito_fpga_read(BUSSWMR2);
|
||||
bsw3 = bonito_fpga_read(BUSSWMR3);
|
||||
bsw4 = bonito_fpga_read(BUSSWMR4);
|
||||
|
||||
/*
|
||||
* SCIFA5 (CN42)
|
||||
*/
|
||||
if (BIT_OFF(bsw2, 1) && /* S38.3 = ON */
|
||||
BIT_OFF(bsw3, 9) && /* S39.6 = ON */
|
||||
BIT_OFF(bsw4, 4)) { /* S43.1 = ON */
|
||||
pinctrl_register_mappings(scifa5_pinctrl_map,
|
||||
ARRAY_SIZE(scifa5_pinctrl_map));
|
||||
}
|
||||
|
||||
/*
|
||||
* LCDC0 (CN3)
|
||||
*/
|
||||
if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
|
||||
BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
|
||||
pinctrl_register_mappings(lcdc0_pinctrl_map,
|
||||
ARRAY_SIZE(lcdc0_pinctrl_map));
|
||||
|
||||
gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
|
||||
NULL); /* LCDDON */
|
||||
|
||||
/* backlight on */
|
||||
bonito_fpga_write(LCDCR, 1);
|
||||
|
||||
/* drivability Max */
|
||||
__raw_writew(0x00FF , VCCQ1LCDCR);
|
||||
__raw_writew(0xFFFF , VCCQ1CR);
|
||||
}
|
||||
|
||||
platform_add_devices(bonito_base_devices,
|
||||
ARRAY_SIZE(bonito_base_devices));
|
||||
}
|
||||
}
|
||||
|
||||
static void __init bonito_earlytimer_init(void)
|
||||
{
|
||||
u16 val;
|
||||
u8 md_ck = 0;
|
||||
|
||||
/* read MD_CK value */
|
||||
val = bonito_fpga_read(A1MDSR);
|
||||
if (val & (1 << 10))
|
||||
md_ck |= MD_CK2;
|
||||
if (val & (1 << 9))
|
||||
md_ck |= MD_CK1;
|
||||
if (val & (1 << 8))
|
||||
md_ck |= MD_CK0;
|
||||
|
||||
r8a7740_clock_init(md_ck);
|
||||
shmobile_earlytimer_init();
|
||||
}
|
||||
|
||||
static void __init bonito_add_early_devices(void)
|
||||
{
|
||||
r8a7740_add_early_devices();
|
||||
}
|
||||
|
||||
MACHINE_START(BONITO, "bonito")
|
||||
.map_io = bonito_map_io,
|
||||
.init_early = bonito_add_early_devices,
|
||||
.init_irq = r8a7740_init_irq,
|
||||
.handle_irq = shmobile_handle_irq_intc,
|
||||
.init_machine = bonito_init,
|
||||
.init_late = shmobile_init_late,
|
||||
.init_time = bonito_earlytimer_init,
|
||||
MACHINE_END
|
||||
@ -25,31 +25,24 @@
|
||||
|
||||
__CPUINIT
|
||||
/*
|
||||
* Reset vector for secondary CPUs.
|
||||
* Boot code for secondary CPUs.
|
||||
*
|
||||
* First we turn on L1 cache coherency for our CPU. Then we jump to
|
||||
* shmobile_invalidate_start that invalidates the cache and hands over control
|
||||
* to the common ARM startup code.
|
||||
* This function will be mapped to address 0 by the SBAR register.
|
||||
* A normal branch is out of range here so we need a long jump. We jump to
|
||||
* the physical address as the MMU is still turned off.
|
||||
*/
|
||||
.align 12
|
||||
ENTRY(shmobile_secondary_vector_scu)
|
||||
mrc p15, 0, r0, c0, c0, 5 @ read MIPDR
|
||||
and r0, r0, #3 @ mask out cpu ID
|
||||
lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits
|
||||
ldr r1, 2f
|
||||
ldr r1, [r1] @ SCU base address
|
||||
ldr r2, [r1, #8] @ SCU Power Status Register
|
||||
ENTRY(shmobile_boot_scu)
|
||||
@ r0 = SCU base address
|
||||
mrc p15, 0, r1, c0, c0, 5 @ read MIPDR
|
||||
and r1, r1, #3 @ mask out cpu ID
|
||||
lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits
|
||||
ldr r2, [r0, #8] @ SCU Power Status Register
|
||||
mov r3, #3
|
||||
bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode)
|
||||
str r2, [r1, #8] @ write back
|
||||
bic r2, r2, r3, lsl r1 @ Clear bits of our CPU (Run Mode)
|
||||
str r2, [r0, #8] @ write back
|
||||
|
||||
ldr pc, 1f
|
||||
1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
|
||||
2: .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET
|
||||
ENDPROC(shmobile_secondary_vector_scu)
|
||||
b shmobile_invalidate_start
|
||||
ENDPROC(shmobile_boot_scu)
|
||||
|
||||
.text
|
||||
.globl shmobile_scu_base
|
||||
|
||||
@ -27,7 +27,14 @@ ENDPROC(shmobile_invalidate_start)
|
||||
* We need _long_ jump to the physical address.
|
||||
*/
|
||||
.align 12
|
||||
ENTRY(shmobile_secondary_vector)
|
||||
ENTRY(shmobile_boot_vector)
|
||||
ldr r0, 2f
|
||||
ldr pc, 1f
|
||||
1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
|
||||
ENDPROC(shmobile_secondary_vector)
|
||||
ENDPROC(shmobile_boot_vector)
|
||||
|
||||
.globl shmobile_boot_fn
|
||||
shmobile_boot_fn:
|
||||
1: .space 4
|
||||
.globl shmobile_boot_arg
|
||||
shmobile_boot_arg:
|
||||
2: .space 4
|
||||
|
||||
@ -7,8 +7,10 @@ extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
|
||||
unsigned int mult, unsigned int div);
|
||||
struct twd_local_timer;
|
||||
extern void shmobile_setup_console(void);
|
||||
extern void shmobile_secondary_vector(void);
|
||||
extern void shmobile_secondary_vector_scu(void);
|
||||
extern void shmobile_boot_vector(void);
|
||||
extern unsigned long shmobile_boot_fn;
|
||||
extern unsigned long shmobile_boot_arg;
|
||||
extern void shmobile_boot_scu(void);
|
||||
struct clk;
|
||||
extern int shmobile_clk_init(void);
|
||||
extern void shmobile_handle_irq_intc(struct pt_regs *);
|
||||
|
||||
@ -1,93 +0,0 @@
|
||||
LIST "partner-jet-setup.txt"
|
||||
LIST "(C) Copyright 2010 Renesas Solutions Corp"
|
||||
LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"
|
||||
|
||||
LIST "RWT Setting"
|
||||
EW 0xE6020004, 0xA500
|
||||
EW 0xE6030004, 0xA500
|
||||
|
||||
LIST "GPIO Setting"
|
||||
EB 0xE6051013, 0xA2
|
||||
|
||||
LIST "CPG"
|
||||
ED 0xE61500C0, 0x00000002
|
||||
|
||||
WAIT 1, 0xFE40009C
|
||||
|
||||
LIST "FRQCR"
|
||||
ED 0xE6150000, 0x2D1305C3
|
||||
ED 0xE61500E0, 0x9E40358E
|
||||
ED 0xE6150004, 0x80331050
|
||||
|
||||
WAIT 1, 0xFE40009C
|
||||
|
||||
ED 0xE61500E4, 0x00002000
|
||||
|
||||
WAIT 1, 0xFE40009C
|
||||
|
||||
LIST "PLL"
|
||||
ED 0xE6150028, 0x00004000
|
||||
|
||||
WAIT 1, 0xFE40009C
|
||||
|
||||
ED 0xE615002C, 0x93000040
|
||||
|
||||
WAIT 1, 0xFE40009C
|
||||
|
||||
LIST "SUB/USBClk"
|
||||
ED 0xE6150080, 0x00000180
|
||||
|
||||
LIST "BSC"
|
||||
ED 0xFEC10000, 0x00E0001B
|
||||
|
||||
LIST "SBSC1"
|
||||
ED 0xFE400354, 0x01AD8000
|
||||
ED 0xFE400354, 0x01AD8001
|
||||
|
||||
WAIT 5, 0xFE40009C
|
||||
|
||||
ED 0xFE400008, 0xBCC90151
|
||||
ED 0xFE400040, 0x41774113
|
||||
ED 0xFE400044, 0x2712E229
|
||||
ED 0xFE400048, 0x20C18505
|
||||
ED 0xFE40004C, 0x00110209
|
||||
ED 0xFE400010, 0x00000087
|
||||
|
||||
WAIT 30, 0xFE40009C
|
||||
|
||||
ED 0xFE400084, 0x0000003F
|
||||
EB 0xFE500000, 0x00
|
||||
|
||||
WAIT 5, 0xFE40009C
|
||||
|
||||
ED 0xFE400084, 0x0000FF0A
|
||||
EB 0xFE500000, 0x00
|
||||
|
||||
WAIT 1, 0xFE40009C
|
||||
|
||||
ED 0xFE400084, 0x00002201
|
||||
EB 0xFE500000, 0x00
|
||||
ED 0xFE400084, 0x00000302
|
||||
EB 0xFE500000, 0x00
|
||||
EB 0xFE5C0000, 0x00
|
||||
ED 0xFE400008, 0xBCC90159
|
||||
ED 0xFE40008C, 0x88800004
|
||||
ED 0xFE400094, 0x00000004
|
||||
ED 0xFE400028, 0xA55A0032
|
||||
ED 0xFE40002C, 0xA55A000C
|
||||
ED 0xFE400020, 0xA55A2048
|
||||
ED 0xFE400008, 0xBCC90959
|
||||
|
||||
LIST "Change CPGA setting"
|
||||
ED 0xE61500E0, 0x9E40352E
|
||||
ED 0xE6150004, 0x80331050
|
||||
|
||||
WAIT 1, 0xFE40009C
|
||||
|
||||
ED 0xFE400354, 0x01AD8002
|
||||
|
||||
LIST "SCIF0 - Serial port for earlyprintk"
|
||||
EB 0xE6053098, 0xe1
|
||||
EW 0xE6C40000, 0x0000
|
||||
EB 0xE6C40004, 0x19
|
||||
EW 0xE6C40008, 0x0030
|
||||
@ -1,7 +0,0 @@
|
||||
#ifndef __ASM_MACH_MEMORY_H
|
||||
#define __ASM_MACH_MEMORY_H
|
||||
|
||||
#define PLAT_PHYS_OFFSET UL(CONFIG_MEMORY_START)
|
||||
#define MEM_SIZE UL(CONFIG_MEMORY_SIZE)
|
||||
|
||||
#endif /* __ASM_MACH_MEMORY_H */
|
||||
@ -1,29 +0,0 @@
|
||||
#ifndef MMC_AP4EB_H
|
||||
#define MMC_AP4EB_H
|
||||
|
||||
#define PORT185CR (void __iomem *)0xe60520b9
|
||||
#define PORT186CR (void __iomem *)0xe60520ba
|
||||
#define PORT187CR (void __iomem *)0xe60520bb
|
||||
#define PORT188CR (void __iomem *)0xe60520bc
|
||||
|
||||
#define PORTR191_160DR (void __iomem *)0xe6056014
|
||||
|
||||
static inline void mmc_init_progress(void)
|
||||
{
|
||||
/* Initialise LEDS1-4
|
||||
* registers: PORT185CR-PORT188CR (LED1-LED4 Control)
|
||||
* value: 0x10 - enable output
|
||||
*/
|
||||
__raw_writeb(0x10, PORT185CR);
|
||||
__raw_writeb(0x10, PORT186CR);
|
||||
__raw_writeb(0x10, PORT187CR);
|
||||
__raw_writeb(0x10, PORT188CR);
|
||||
}
|
||||
|
||||
static inline void mmc_update_progress(int n)
|
||||
{
|
||||
__raw_writel((__raw_readl(PORTR191_160DR) & ~(0xf << 25)) |
|
||||
(1 << (25 + n)), PORTR191_160DR);
|
||||
}
|
||||
|
||||
#endif /* MMC_AP4EB_H */
|
||||
@ -7,9 +7,7 @@
|
||||
*
|
||||
**************************************************/
|
||||
|
||||
#ifdef CONFIG_MACH_AP4EVB
|
||||
#include "mach/mmc-ap4eb.h"
|
||||
#elif defined(CONFIG_MACH_MACKEREL)
|
||||
#ifdef CONFIG_MACH_MACKEREL
|
||||
#include "mach/mmc-mackerel.h"
|
||||
#else
|
||||
#error "unsupported board."
|
||||
|
||||
@ -75,6 +75,8 @@ extern void sh7372_intcs_resume(void);
|
||||
extern void sh7372_intca_suspend(void);
|
||||
extern void sh7372_intca_resume(void);
|
||||
|
||||
extern unsigned long sh7372_cpu_resume;
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
extern void __init sh7372_init_pm_domains(void);
|
||||
#else
|
||||
|
||||
@ -10,11 +10,9 @@
|
||||
*
|
||||
**************************************************/
|
||||
|
||||
#ifdef CONFIG_MACH_AP4EVB
|
||||
#define MACH_TYPE MACH_TYPE_AP4EVB
|
||||
#include "mach/head-ap4evb.txt"
|
||||
#elif defined(CONFIG_MACH_MACKEREL)
|
||||
#ifdef CONFIG_MACH_MACKEREL
|
||||
#define MACH_TYPE MACH_TYPE_MACKEREL
|
||||
#define MEMORY_START 0x40000000
|
||||
#include "mach/head-mackerel.txt"
|
||||
#else
|
||||
#error "unsupported board."
|
||||
|
||||
@ -351,6 +351,9 @@ static void sh7372_enter_a4s_common(int pllc0_on)
|
||||
|
||||
static void sh7372_pm_setup_smfram(void)
|
||||
{
|
||||
/* pass physical address of cpu_resume() to assembly resume code */
|
||||
sh7372_cpu_resume = virt_to_phys(cpu_resume);
|
||||
|
||||
memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
|
||||
}
|
||||
#else
|
||||
|
||||
@ -40,7 +40,10 @@
|
||||
.global sh7372_resume_core_standby_sysc
|
||||
sh7372_resume_core_standby_sysc:
|
||||
ldr pc, 1f
|
||||
1: .long cpu_resume - PAGE_OFFSET + PLAT_PHYS_OFFSET
|
||||
|
||||
.globl sh7372_cpu_resume
|
||||
sh7372_cpu_resume:
|
||||
1: .space 4
|
||||
|
||||
#define SPDCR 0xe6180008
|
||||
|
||||
|
||||
@ -40,8 +40,10 @@ static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
scu_enable(shmobile_scu_base);
|
||||
|
||||
/* Tell ROM loader about our vector (in headsmp-scu.S) */
|
||||
emev2_set_boot_vector(__pa(shmobile_secondary_vector_scu));
|
||||
/* Tell ROM loader about our vector (in headsmp-scu.S, headsmp.S) */
|
||||
emev2_set_boot_vector(__pa(shmobile_boot_vector));
|
||||
shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
|
||||
shmobile_boot_arg = (unsigned long)shmobile_scu_base;
|
||||
|
||||
/* enable cache coherency on booting CPU */
|
||||
scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
|
||||
|
||||
@ -101,8 +101,10 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
scu_enable(shmobile_scu_base);
|
||||
|
||||
/* Map the reset vector (in headsmp-scu.S) */
|
||||
__raw_writel(__pa(shmobile_secondary_vector_scu), AVECR);
|
||||
/* Map the reset vector (in headsmp-scu.S, headsmp.S) */
|
||||
__raw_writel(__pa(shmobile_boot_vector), AVECR);
|
||||
shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
|
||||
shmobile_boot_arg = (unsigned long)shmobile_scu_base;
|
||||
|
||||
/* enable cache coherency on booting CPU */
|
||||
scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
|
||||
|
||||
@ -64,9 +64,11 @@ static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
|
||||
{
|
||||
scu_enable(shmobile_scu_base);
|
||||
|
||||
/* Map the reset vector (in headsmp-scu.S) */
|
||||
/* Map the reset vector (in headsmp-scu.S, headsmp.S) */
|
||||
__raw_writel(0, APARMBAREA); /* 4k */
|
||||
__raw_writel(__pa(shmobile_secondary_vector_scu), SBAR);
|
||||
__raw_writel(__pa(shmobile_boot_vector), SBAR);
|
||||
shmobile_boot_fn = virt_to_phys(shmobile_boot_scu);
|
||||
shmobile_boot_arg = (unsigned long)shmobile_scu_base;
|
||||
|
||||
/* enable cache coherency on booting CPU */
|
||||
scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user