forked from Minki/linux
qed: Use enum as per FW 8.59.1.0 in qed_iro_hsi.h
qed_iro_hsi.h contains HSI changes related to storm memories access. Existing code is based on hard-coded index. Use enum as defined for FW HSI 8.59.1.0, instead of hard-coded index. This patch also removes unnecessary header file inclusion. Signed-off-by: Ariel Elior <aelior@marvell.com> Signed-off-by: Omkar Kulkarni <okulkarni@marvell.com> Signed-off-by: Shai Malin <smalin@marvell.com> Signed-off-by: Prabhakar Kushwaha <pkushwaha@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Prabhakar Kushwaha
David S. Miller
parent
fe40a830dc
commit
3091be065f
@ -8,332 +8,465 @@
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#include <linux/types.h>
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/* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
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#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[0].base)
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#define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[0].size)
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enum {
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IRO_YSTORM_FLOW_CONTROL_MODE,
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IRO_TSTORM_PORT_STAT,
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IRO_TSTORM_LL2_PORT_STAT,
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IRO_USTORM_VF_PF_CHANNEL_READY,
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IRO_USTORM_FLR_FINAL_ACK,
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IRO_USTORM_EQE_CONS,
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IRO_USTORM_ETH_QUEUE_ZONE,
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IRO_USTORM_COMMON_QUEUE_CONS,
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IRO_XSTORM_PQ_INFO,
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IRO_XSTORM_INTEG_TEST_DATA,
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IRO_YSTORM_INTEG_TEST_DATA,
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IRO_PSTORM_INTEG_TEST_DATA,
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IRO_TSTORM_INTEG_TEST_DATA,
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IRO_MSTORM_INTEG_TEST_DATA,
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IRO_USTORM_INTEG_TEST_DATA,
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IRO_XSTORM_OVERLAY_BUF_ADDR,
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IRO_YSTORM_OVERLAY_BUF_ADDR,
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IRO_PSTORM_OVERLAY_BUF_ADDR,
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IRO_TSTORM_OVERLAY_BUF_ADDR,
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IRO_MSTORM_OVERLAY_BUF_ADDR,
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IRO_USTORM_OVERLAY_BUF_ADDR,
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IRO_TSTORM_LL2_RX_PRODS,
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IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT,
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IRO_CORE_LL2_USTORM_PER_QUEUE_STAT,
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IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT,
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IRO_MSTORM_QUEUE_STAT,
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IRO_MSTORM_TPA_TIMEOUT_US,
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IRO_MSTORM_ETH_VF_PRODS,
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IRO_MSTORM_ETH_PF_PRODS,
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IRO_MSTORM_ETH_PF_STAT,
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IRO_USTORM_QUEUE_STAT,
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IRO_USTORM_ETH_PF_STAT,
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IRO_PSTORM_QUEUE_STAT,
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IRO_PSTORM_ETH_PF_STAT,
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IRO_PSTORM_CTL_FRAME_ETHTYPE,
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IRO_TSTORM_ETH_PRS_INPUT,
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IRO_ETH_RX_RATE_LIMIT,
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IRO_TSTORM_ETH_RSS_UPDATE,
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IRO_XSTORM_ETH_QUEUE_ZONE,
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IRO_YSTORM_TOE_CQ_PROD,
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IRO_USTORM_TOE_CQ_PROD,
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IRO_USTORM_TOE_GRQ_PROD,
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IRO_TSTORM_SCSI_CMDQ_CONS,
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IRO_TSTORM_SCSI_BDQ_EXT_PROD,
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IRO_MSTORM_SCSI_BDQ_EXT_PROD,
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IRO_TSTORM_ISCSI_RX_STATS,
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IRO_MSTORM_ISCSI_RX_STATS,
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IRO_USTORM_ISCSI_RX_STATS,
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IRO_XSTORM_ISCSI_TX_STATS,
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IRO_YSTORM_ISCSI_TX_STATS,
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IRO_PSTORM_ISCSI_TX_STATS,
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IRO_TSTORM_FCOE_RX_STATS,
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IRO_PSTORM_FCOE_TX_STATS,
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IRO_PSTORM_RDMA_QUEUE_STAT,
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IRO_TSTORM_RDMA_QUEUE_STAT,
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IRO_XSTORM_RDMA_ASSERT_LEVEL,
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IRO_YSTORM_RDMA_ASSERT_LEVEL,
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IRO_PSTORM_RDMA_ASSERT_LEVEL,
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IRO_TSTORM_RDMA_ASSERT_LEVEL,
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IRO_MSTORM_RDMA_ASSERT_LEVEL,
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IRO_USTORM_RDMA_ASSERT_LEVEL,
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IRO_XSTORM_IWARP_RXMIT_STATS,
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IRO_TSTORM_ROCE_EVENTS_STAT,
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IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS,
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IRO_YSTORM_ROCE_ERROR_STATS,
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IRO_PSTORM_ROCE_DCQCN_SENT_STATS,
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IRO_USTORM_ROCE_CQE_STATS,
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};
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/* Tstorm port statistics */
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#define TSTORM_PORT_STAT_OFFSET(port_id) \
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(IRO[1].base + ((port_id) * IRO[1].m1))
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#define TSTORM_PORT_STAT_SIZE (IRO[1].size)
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/* Pstorm LiteL2 queue statistics */
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/* Tstorm ll2 port statistics */
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#define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
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(IRO[2].base + ((port_id) * IRO[2].m1))
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#define TSTORM_LL2_PORT_STAT_SIZE (IRO[2].size)
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/* Ustorm VF-PF Channel ready flag */
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#define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
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(IRO[3].base + ((vf_id) * IRO[3].m1))
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#define USTORM_VF_PF_CHANNEL_READY_SIZE (IRO[3].size)
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/* Ustorm Final flr cleanup ack */
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#define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
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(IRO[4].base + ((pf_id) * IRO[4].m1))
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#define USTORM_FLR_FINAL_ACK_SIZE (IRO[4].size)
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/* Ustorm Event ring consumer */
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#define USTORM_EQE_CONS_OFFSET(pf_id) \
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(IRO[5].base + ((pf_id) * IRO[5].m1))
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#define USTORM_EQE_CONS_SIZE (IRO[5].size)
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/* Ustorm eth queue zone */
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#define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
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(IRO[6].base + ((queue_zone_id) * IRO[6].m1))
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#define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[6].size)
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/* Ustorm Common Queue ring consumer */
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#define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
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(IRO[7].base + ((queue_zone_id) * IRO[7].m1))
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#define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[7].size)
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/* Xstorm common PQ info */
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#define XSTORM_PQ_INFO_OFFSET(pq_id) \
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(IRO[8].base + ((pq_id) * IRO[8].m1))
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#define XSTORM_PQ_INFO_SIZE (IRO[8].size)
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/* Xstorm Integration Test Data */
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#define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[9].base)
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#define XSTORM_INTEG_TEST_DATA_SIZE (IRO[9].size)
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/* Ystorm Integration Test Data */
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#define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[10].base)
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#define YSTORM_INTEG_TEST_DATA_SIZE (IRO[10].size)
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/* Pstorm Integration Test Data */
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#define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[11].base)
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#define PSTORM_INTEG_TEST_DATA_SIZE (IRO[11].size)
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/* Tstorm Integration Test Data */
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#define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[12].base)
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#define TSTORM_INTEG_TEST_DATA_SIZE (IRO[12].size)
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/* Mstorm Integration Test Data */
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#define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[13].base)
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#define MSTORM_INTEG_TEST_DATA_SIZE (IRO[13].size)
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/* Ustorm Integration Test Data */
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#define USTORM_INTEG_TEST_DATA_OFFSET (IRO[14].base)
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#define USTORM_INTEG_TEST_DATA_SIZE (IRO[14].size)
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/* Xstorm overlay buffer host address */
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#define XSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[15].base)
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#define XSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[15].size)
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/* Ystorm overlay buffer host address */
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#define YSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[16].base)
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#define YSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[16].size)
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/* Pstorm overlay buffer host address */
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#define PSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[17].base)
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#define PSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[17].size)
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/* Tstorm overlay buffer host address */
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#define TSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[18].base)
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#define TSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[18].size)
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/* Mstorm overlay buffer host address */
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#define MSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[19].base)
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#define MSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[19].size)
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/* Ustorm overlay buffer host address */
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#define USTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[20].base)
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#define USTORM_OVERLAY_BUF_ADDR_SIZE (IRO[20].size)
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/* Tstorm producers */
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#define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
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(IRO[21].base + ((core_rx_queue_id) * IRO[21].m1))
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#define TSTORM_LL2_RX_PRODS_SIZE (IRO[21].size)
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#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
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(IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].base \
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+ ((core_tx_stats_id) * IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].m1))
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#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE \
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(IRO[IRO_CORE_LL2_PSTORM_PER_QUEUE_STAT].size)
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/* Tstorm LightL2 queue statistics */
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#define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
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(IRO[22].base + ((core_rx_queue_id) * IRO[22].m1))
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#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE (IRO[22].size)
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(IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].base \
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+ ((core_rx_queue_id) * IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].m1))
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#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE \
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(IRO[IRO_CORE_LL2_TSTORM_PER_QUEUE_STAT].size)
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/* Ustorm LiteL2 queue statistics */
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#define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
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(IRO[23].base + ((core_rx_queue_id) * IRO[23].m1))
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#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE (IRO[23].size)
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(IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].base \
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+ ((core_rx_queue_id) * IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].m1))
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#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE \
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(IRO[IRO_CORE_LL2_USTORM_PER_QUEUE_STAT].size)
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/* Pstorm LiteL2 queue statistics */
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#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
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(IRO[24].base + ((core_tx_stats_id) * IRO[24].m1))
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#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE (IRO[24].size)
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/* Mstorm queue statistics */
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#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
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(IRO[25].base + ((stat_counter_id) * IRO[25].m1))
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#define MSTORM_QUEUE_STAT_SIZE (IRO[25].size)
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/* TPA agregation timeout in us resolution (on ASIC) */
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#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[26].base)
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#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[26].size)
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/* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone size
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* mode
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*/
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#define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
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(IRO[27].base + ((vf_id) * IRO[27].m1) + ((vf_queue_id) * IRO[27].m2))
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#define MSTORM_ETH_VF_PRODS_SIZE (IRO[27].size)
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/* Tstorm Eth limit Rx rate */
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#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
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(IRO[IRO_ETH_RX_RATE_LIMIT].base \
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+ ((pf_id) * IRO[IRO_ETH_RX_RATE_LIMIT].m1))
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#define ETH_RX_RATE_LIMIT_SIZE (IRO[IRO_ETH_RX_RATE_LIMIT].size)
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/* Mstorm ETH PF queues producers */
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#define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
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(IRO[28].base + ((queue_id) * IRO[28].m1))
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#define MSTORM_ETH_PF_PRODS_SIZE (IRO[28].size)
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(IRO[IRO_MSTORM_ETH_PF_PRODS].base \
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+ ((queue_id) * IRO[IRO_MSTORM_ETH_PF_PRODS].m1))
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#define MSTORM_ETH_PF_PRODS_SIZE (IRO[IRO_MSTORM_ETH_PF_PRODS].size)
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/* Mstorm pf statistics */
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#define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
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(IRO[29].base + ((pf_id) * IRO[29].m1))
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#define MSTORM_ETH_PF_STAT_SIZE (IRO[29].size)
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#define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
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(IRO[IRO_MSTORM_ETH_PF_STAT].base \
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+ ((pf_id) * IRO[IRO_MSTORM_ETH_PF_STAT].m1))
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#define MSTORM_ETH_PF_STAT_SIZE (IRO[IRO_MSTORM_ETH_PF_STAT].size)
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/* Ustorm queue statistics */
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#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
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(IRO[30].base + ((stat_counter_id) * IRO[30].m1))
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#define USTORM_QUEUE_STAT_SIZE (IRO[30].size)
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/* Ustorm pf statistics */
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#define USTORM_ETH_PF_STAT_OFFSET(pf_id) \
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(IRO[31].base + ((pf_id) * IRO[31].m1))
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#define USTORM_ETH_PF_STAT_SIZE (IRO[31].size)
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/* Pstorm queue statistics */
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#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
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(IRO[32].base + ((stat_counter_id) * IRO[32].m1))
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#define PSTORM_QUEUE_STAT_SIZE (IRO[32].size)
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/* Pstorm pf statistics */
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#define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
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(IRO[33].base + ((pf_id) * IRO[33].m1))
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#define PSTORM_ETH_PF_STAT_SIZE (IRO[33].size)
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/* Control frame's EthType configuration for TX control frame security */
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#define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(eth_type_id) \
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(IRO[34].base + ((eth_type_id) * IRO[34].m1))
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#define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[34].size)
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/* Tstorm last parser message */
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#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[35].base)
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#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[35].size)
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/* Tstorm Eth limit Rx rate */
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#define ETH_RX_RATE_LIMIT_OFFSET(pf_id) \
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(IRO[36].base + ((pf_id) * IRO[36].m1))
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#define ETH_RX_RATE_LIMIT_SIZE (IRO[36].size)
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/* RSS indirection table entry update command per PF offset in TSTORM PF BAR0.
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* Use eth_tstorm_rss_update_data for update
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/* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone
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* size mode.
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*/
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#define TSTORM_ETH_RSS_UPDATE_OFFSET(pf_id) \
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(IRO[37].base + ((pf_id) * IRO[37].m1))
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#define TSTORM_ETH_RSS_UPDATE_SIZE (IRO[37].size)
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#define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
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(IRO[IRO_MSTORM_ETH_VF_PRODS].base \
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+ ((vf_id) * IRO[IRO_MSTORM_ETH_VF_PRODS].m1) \
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+ ((vf_queue_id) * IRO[IRO_MSTORM_ETH_VF_PRODS].m2))
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#define MSTORM_ETH_VF_PRODS_SIZE (IRO[IRO_MSTORM_ETH_VF_PRODS].size)
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/* Xstorm queue zone */
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#define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
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(IRO[38].base + ((queue_id) * IRO[38].m1))
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#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[38].size)
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/* Ystorm cqe producer */
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#define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \
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(IRO[39].base + ((rss_id) * IRO[39].m1))
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#define YSTORM_TOE_CQ_PROD_SIZE (IRO[39].size)
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/* Ustorm cqe producer */
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#define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \
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(IRO[40].base + ((rss_id) * IRO[40].m1))
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#define USTORM_TOE_CQ_PROD_SIZE (IRO[40].size)
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/* Ustorm grq producer */
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#define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \
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(IRO[41].base + ((pf_id) * IRO[41].m1))
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#define USTORM_TOE_GRQ_PROD_SIZE (IRO[41].size)
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/* Tstorm cmdq-cons of given command queue-id */
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#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
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(IRO[42].base + ((cmdq_queue_id) * IRO[42].m1))
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#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[42].size)
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/* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,
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* BDqueue-id
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*/
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#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(storage_func_id, bdq_id) \
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(IRO[43].base + ((storage_func_id) * IRO[43].m1) + \
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((bdq_id) * IRO[43].m2))
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#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[43].size)
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/* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */
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#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(storage_func_id, bdq_id) \
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(IRO[44].base + ((storage_func_id) * IRO[44].m1) + \
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((bdq_id) * IRO[44].m2))
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#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[44].size)
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/* Tstorm iSCSI RX stats */
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#define TSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
|
||||
(IRO[45].base + ((storage_func_id) * IRO[45].m1))
|
||||
#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[45].size)
|
||||
/* Mstorm Integration Test Data */
|
||||
#define MSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_MSTORM_INTEG_TEST_DATA].base)
|
||||
#define MSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_MSTORM_INTEG_TEST_DATA].size)
|
||||
|
||||
/* Mstorm iSCSI RX stats */
|
||||
#define MSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
|
||||
(IRO[46].base + ((storage_func_id) * IRO[46].m1))
|
||||
#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[46].size)
|
||||
(IRO[IRO_MSTORM_ISCSI_RX_STATS].base \
|
||||
+ ((storage_func_id) * IRO[IRO_MSTORM_ISCSI_RX_STATS].m1))
|
||||
#define MSTORM_ISCSI_RX_STATS_SIZE (IRO[IRO_MSTORM_ISCSI_RX_STATS].size)
|
||||
|
||||
/* Ustorm iSCSI RX stats */
|
||||
#define USTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
|
||||
(IRO[47].base + ((storage_func_id) * IRO[47].m1))
|
||||
#define USTORM_ISCSI_RX_STATS_SIZE (IRO[47].size)
|
||||
/* Mstorm overlay buffer host address */
|
||||
#define MSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_MSTORM_OVERLAY_BUF_ADDR].base)
|
||||
#define MSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_MSTORM_OVERLAY_BUF_ADDR].size)
|
||||
|
||||
/* Xstorm iSCSI TX stats */
|
||||
#define XSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
|
||||
(IRO[48].base + ((storage_func_id) * IRO[48].m1))
|
||||
#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[48].size)
|
||||
/* Mstorm queue statistics */
|
||||
#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
|
||||
(IRO[IRO_MSTORM_QUEUE_STAT].base \
|
||||
+ ((stat_counter_id) * IRO[IRO_MSTORM_QUEUE_STAT].m1))
|
||||
#define MSTORM_QUEUE_STAT_SIZ (IRO[IRO_MSTORM_QUEUE_STAT].size)
|
||||
|
||||
/* Ystorm iSCSI TX stats */
|
||||
#define YSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
|
||||
(IRO[49].base + ((storage_func_id) * IRO[49].m1))
|
||||
#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[49].size)
|
||||
/* Mstorm error level for assert */
|
||||
#define MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
|
||||
(IRO[IRO_MSTORM_RDMA_ASSERT_LEVEL].base \
|
||||
+ ((pf_id) * IRO[IRO_MSTORM_RDMA_ASSERT_LEVEL].m1))
|
||||
#define MSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_MSTORM_RDMA_ASSERT_LEVEL].size)
|
||||
|
||||
/* Mstorm bdq-external-producer of given BDQ resource ID, BDqueue-id */
|
||||
#define MSTORM_SCSI_BDQ_EXT_PROD_OFFSET(storage_func_id, bdq_id) \
|
||||
(IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD].base \
|
||||
+ ((storage_func_id) * IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD].m1) \
|
||||
+ ((bdq_id) * IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD].m2))
|
||||
#define MSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[IRO_MSTORM_SCSI_BDQ_EXT_PROD].size)
|
||||
|
||||
/* TPA agregation timeout in us resolution (on ASIC) */
|
||||
#define MSTORM_TPA_TIMEOUT_US_OFFSET (IRO[IRO_MSTORM_TPA_TIMEOUT_US].base)
|
||||
#define MSTORM_TPA_TIMEOUT_US_SIZE (IRO[IRO_MSTORM_TPA_TIMEOUT_US].size)
|
||||
|
||||
/* Control frame's EthType configuration for TX control frame security */
|
||||
#define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(ethtype_id) \
|
||||
(IRO[IRO_PSTORM_CTL_FRAME_ETHTYPE].base \
|
||||
+ ((ethtype_id) * IRO[IRO_PSTORM_CTL_FRAME_ETHTYPE].m1))
|
||||
#define PSTORM_CTL_FRAME_ETHTYPE_SIZE (IRO[IRO_PSTORM_CTL_FRAME_ETHTYPE].size)
|
||||
|
||||
/* Pstorm pf statistics */
|
||||
#define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
|
||||
(IRO[IRO_PSTORM_ETH_PF_STAT].base \
|
||||
+ ((pf_id) * IRO[IRO_PSTORM_ETH_PF_STAT].m1))
|
||||
#define PSTORM_ETH_PF_STAT_SIZE (IRO[IRO_PSTORM_ETH_PF_STAT].size)
|
||||
|
||||
/* Pstorm FCoE TX stats */
|
||||
#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
|
||||
(IRO[IRO_PSTORM_FCOE_TX_STATS].base \
|
||||
+ ((pf_id) * IRO[IRO_PSTORM_FCOE_TX_STATS].m1))
|
||||
#define PSTORM_FCOE_TX_STATS_SIZE (IRO[IRO_PSTORM_FCOE_TX_STATS].size)
|
||||
|
||||
/* Pstorm Integration Test Data */
|
||||
#define PSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_PSTORM_INTEG_TEST_DATA].base)
|
||||
#define PSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_PSTORM_INTEG_TEST_DATA].size)
|
||||
|
||||
/* Pstorm iSCSI TX stats */
|
||||
#define PSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
|
||||
(IRO[50].base + ((storage_func_id) * IRO[50].m1))
|
||||
#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[50].size)
|
||||
(IRO[IRO_PSTORM_ISCSI_TX_STATS].base \
|
||||
+ ((storage_func_id) * IRO[IRO_PSTORM_ISCSI_TX_STATS].m1))
|
||||
#define PSTORM_ISCSI_TX_STATS_SIZE (IRO[IRO_PSTORM_ISCSI_TX_STATS].size)
|
||||
|
||||
/* Tstorm FCoE RX stats */
|
||||
#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
|
||||
(IRO[51].base + ((pf_id) * IRO[51].m1))
|
||||
#define TSTORM_FCOE_RX_STATS_SIZE (IRO[51].size)
|
||||
/* Pstorm overlay buffer host address */
|
||||
#define PSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_PSTORM_OVERLAY_BUF_ADDR].base)
|
||||
#define PSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_PSTORM_OVERLAY_BUF_ADDR].size)
|
||||
|
||||
/* Pstorm FCoE TX stats */
|
||||
#define PSTORM_FCOE_TX_STATS_OFFSET(pf_id) \
|
||||
(IRO[52].base + ((pf_id) * IRO[52].m1))
|
||||
#define PSTORM_FCOE_TX_STATS_SIZE (IRO[52].size)
|
||||
/* Pstorm queue statistics */
|
||||
#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
|
||||
(IRO[IRO_PSTORM_QUEUE_STAT].base \
|
||||
+ ((stat_counter_id) * IRO[IRO_PSTORM_QUEUE_STAT].m1))
|
||||
#define PSTORM_QUEUE_STAT_SIZE (IRO[IRO_PSTORM_QUEUE_STAT].size)
|
||||
|
||||
/* Pstorm error level for assert */
|
||||
#define PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
|
||||
(IRO[IRO_PSTORM_RDMA_ASSERT_LEVEL].base \
|
||||
+ ((pf_id) * IRO[IRO_PSTORM_RDMA_ASSERT_LEVEL].m1))
|
||||
#define PSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_PSTORM_RDMA_ASSERT_LEVEL].size)
|
||||
|
||||
/* Pstorm RDMA queue statistics */
|
||||
#define PSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
|
||||
(IRO[53].base + ((rdma_stat_counter_id) * IRO[53].m1))
|
||||
#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[53].size)
|
||||
(IRO[IRO_PSTORM_RDMA_QUEUE_STAT].base \
|
||||
+ ((rdma_stat_counter_id) * IRO[IRO_PSTORM_RDMA_QUEUE_STAT].m1))
|
||||
#define PSTORM_RDMA_QUEUE_STAT_SIZE (IRO[IRO_PSTORM_RDMA_QUEUE_STAT].size)
|
||||
|
||||
/* DCQCN Sent Statistics */
|
||||
#define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) \
|
||||
(IRO[IRO_PSTORM_ROCE_DCQCN_SENT_STATS].base \
|
||||
+ ((roce_pf_id) * IRO[IRO_PSTORM_ROCE_DCQCN_SENT_STATS].m1))
|
||||
#define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE \
|
||||
(IRO[IRO_PSTORM_ROCE_DCQCN_SENT_STATS].size)
|
||||
|
||||
/* Tstorm last parser message */
|
||||
#define TSTORM_ETH_PRS_INPUT_OFFSET (IRO[IRO_TSTORM_ETH_PRS_INPUT].base)
|
||||
#define TSTORM_ETH_PRS_INPUT_SIZE (IRO[IRO_TSTORM_ETH_PRS_INPUT].size)
|
||||
|
||||
/* RSS indirection table entry update command per PF offset in TSTORM PF BAR0.
|
||||
* Use eth_tstorm_rss_update_data for update.
|
||||
*/
|
||||
#define TSTORM_ETH_RSS_UPDATE_OFFSET(pf_id) \
|
||||
(IRO[IRO_TSTORM_ETH_RSS_UPDATE].base \
|
||||
+ ((pf_id) * IRO[IRO_TSTORM_ETH_RSS_UPDATE].m1))
|
||||
#define TSTORM_ETH_RSS_UPDATE_SIZE (IRO[IRO_TSTORM_ETH_RSS_UPDATE].size)
|
||||
|
||||
/* Tstorm FCoE RX stats */
|
||||
#define TSTORM_FCOE_RX_STATS_OFFSET(pf_id) \
|
||||
(IRO[IRO_TSTORM_FCOE_RX_STATS].base \
|
||||
+ ((pf_id) * IRO[IRO_TSTORM_FCOE_RX_STATS].m1))
|
||||
#define TSTORM_FCOE_RX_STATS_SIZE (IRO[IRO_TSTORM_FCOE_RX_STATS].size)
|
||||
|
||||
/* Tstorm Integration Test Data */
|
||||
#define TSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_TSTORM_INTEG_TEST_DATA].base)
|
||||
#define TSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_TSTORM_INTEG_TEST_DATA].size)
|
||||
|
||||
/* Tstorm iSCSI RX stats */
|
||||
#define TSTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
|
||||
(IRO[IRO_TSTORM_ISCSI_RX_STATS].base \
|
||||
+ ((storage_func_id) * IRO[IRO_TSTORM_ISCSI_RX_STATS].m1))
|
||||
#define TSTORM_ISCSI_RX_STATS_SIZE (IRO[IRO_TSTORM_ISCSI_RX_STATS].size)
|
||||
|
||||
/* Tstorm ll2 port statistics */
|
||||
#define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
|
||||
(IRO[IRO_TSTORM_LL2_PORT_STAT].base \
|
||||
+ ((port_id) * IRO[IRO_TSTORM_LL2_PORT_STAT].m1))
|
||||
#define TSTORM_LL2_PORT_STAT_SIZE (IRO[IRO_TSTORM_LL2_PORT_STAT].size)
|
||||
|
||||
/* Tstorm producers */
|
||||
#define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
|
||||
(IRO[IRO_TSTORM_LL2_RX_PRODS].base \
|
||||
+ ((core_rx_queue_id) * IRO[IRO_TSTORM_LL2_RX_PRODS].m1))
|
||||
#define TSTORM_LL2_RX_PRODS_SIZE (IRO[IRO_TSTORM_LL2_RX_PRODS].size)
|
||||
|
||||
/* Tstorm overlay buffer host address */
|
||||
#define TSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_TSTORM_OVERLAY_BUF_ADDR].base)
|
||||
|
||||
#define TSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_TSTORM_OVERLAY_BUF_ADDR].size)
|
||||
|
||||
/* Tstorm port statistics */
|
||||
#define TSTORM_PORT_STAT_OFFSET(port_id) \
|
||||
(IRO[IRO_TSTORM_PORT_STAT].base \
|
||||
+ ((port_id) * IRO[IRO_TSTORM_PORT_STAT].m1))
|
||||
#define TSTORM_PORT_STAT_SIZE (IRO[IRO_TSTORM_PORT_STAT].size)
|
||||
|
||||
/* Tstorm error level for assert */
|
||||
#define TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
|
||||
(IRO[IRO_TSTORM_RDMA_ASSERT_LEVEL].base \
|
||||
+ ((pf_id) * IRO[IRO_TSTORM_RDMA_ASSERT_LEVEL].m1))
|
||||
#define TSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_TSTORM_RDMA_ASSERT_LEVEL].size)
|
||||
|
||||
/* Tstorm RDMA queue statistics */
|
||||
#define TSTORM_RDMA_QUEUE_STAT_OFFSET(rdma_stat_counter_id) \
|
||||
(IRO[54].base + ((rdma_stat_counter_id) * IRO[54].m1))
|
||||
#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[54].size)
|
||||
|
||||
/* Xstorm error level for assert */
|
||||
#define XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
|
||||
(IRO[55].base + ((pf_id) * IRO[55].m1))
|
||||
#define XSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[55].size)
|
||||
|
||||
/* Ystorm error level for assert */
|
||||
#define YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
|
||||
(IRO[56].base + ((pf_id) * IRO[56].m1))
|
||||
#define YSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[56].size)
|
||||
|
||||
/* Pstorm error level for assert */
|
||||
#define PSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
|
||||
(IRO[57].base + ((pf_id) * IRO[57].m1))
|
||||
#define PSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[57].size)
|
||||
|
||||
/* Tstorm error level for assert */
|
||||
#define TSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
|
||||
(IRO[58].base + ((pf_id) * IRO[58].m1))
|
||||
#define TSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[58].size)
|
||||
|
||||
/* Mstorm error level for assert */
|
||||
#define MSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
|
||||
(IRO[59].base + ((pf_id) * IRO[59].m1))
|
||||
#define MSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[59].size)
|
||||
|
||||
/* Ustorm error level for assert */
|
||||
#define USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
|
||||
(IRO[60].base + ((pf_id) * IRO[60].m1))
|
||||
#define USTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[60].size)
|
||||
|
||||
/* Xstorm iWARP rxmit stats */
|
||||
#define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) \
|
||||
(IRO[61].base + ((pf_id) * IRO[61].m1))
|
||||
#define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[61].size)
|
||||
(IRO[IRO_TSTORM_RDMA_QUEUE_STAT].base \
|
||||
+ ((rdma_stat_counter_id) * IRO[IRO_TSTORM_RDMA_QUEUE_STAT].m1))
|
||||
#define TSTORM_RDMA_QUEUE_STAT_SIZE (IRO[IRO_TSTORM_RDMA_QUEUE_STAT].size)
|
||||
|
||||
/* Tstorm RoCE Event Statistics */
|
||||
#define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) \
|
||||
(IRO[62].base + ((roce_pf_id) * IRO[62].m1))
|
||||
#define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[62].size)
|
||||
#define TSTORM_ROCE_EVENTS_STAT_OFFSET(roce_pf_id) \
|
||||
(IRO[IRO_TSTORM_ROCE_EVENTS_STAT].base \
|
||||
+ ((roce_pf_id) * IRO[IRO_TSTORM_ROCE_EVENTS_STAT].m1))
|
||||
#define TSTORM_ROCE_EVENTS_STAT_SIZE (IRO[IRO_TSTORM_ROCE_EVENTS_STAT].size)
|
||||
|
||||
/* DCQCN Received Statistics */
|
||||
#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id)\
|
||||
(IRO[63].base + ((roce_pf_id) * IRO[63].m1))
|
||||
#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE (IRO[63].size)
|
||||
/* Tstorm (reflects M-Storm) bdq-external-producer of given function ID,
|
||||
* BDqueue-id.
|
||||
*/
|
||||
#define TSTORM_SCSI_BDQ_EXT_PROD_OFFSET(storage_func_id, bdq_id) \
|
||||
(IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD].base \
|
||||
+ ((storage_func_id) * IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD].m1) \
|
||||
+ ((bdq_id) * IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD].m2))
|
||||
#define TSTORM_SCSI_BDQ_EXT_PROD_SIZE (IRO[IRO_TSTORM_SCSI_BDQ_EXT_PROD].size)
|
||||
|
||||
/* RoCE Error Statistics */
|
||||
#define YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) \
|
||||
(IRO[64].base + ((roce_pf_id) * IRO[64].m1))
|
||||
#define YSTORM_ROCE_ERROR_STATS_SIZE (IRO[64].size)
|
||||
/* Tstorm cmdq-cons of given command queue-id */
|
||||
#define TSTORM_SCSI_CMDQ_CONS_OFFSET(cmdq_queue_id) \
|
||||
(IRO[IRO_TSTORM_SCSI_CMDQ_CONS].base \
|
||||
+ ((cmdq_queue_id) * IRO[IRO_TSTORM_SCSI_CMDQ_CONS].m1))
|
||||
#define TSTORM_SCSI_CMDQ_CONS_SIZE (IRO[IRO_TSTORM_SCSI_CMDQ_CONS].size)
|
||||
|
||||
/* DCQCN Sent Statistics */
|
||||
#define PSTORM_ROCE_DCQCN_SENT_STATS_OFFSET(roce_pf_id) \
|
||||
(IRO[65].base + ((roce_pf_id) * IRO[65].m1))
|
||||
#define PSTORM_ROCE_DCQCN_SENT_STATS_SIZE (IRO[65].size)
|
||||
/* Ustorm Common Queue ring consumer */
|
||||
#define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
|
||||
(IRO[IRO_USTORM_COMMON_QUEUE_CONS].base \
|
||||
+ ((queue_zone_id) * IRO[IRO_USTORM_COMMON_QUEUE_CONS].m1))
|
||||
#define USTORM_COMMON_QUEUE_CONS_SIZE (IRO[IRO_USTORM_COMMON_QUEUE_CONS].size)
|
||||
|
||||
/* Ustorm Event ring consumer */
|
||||
#define USTORM_EQE_CONS_OFFSET(pf_id) \
|
||||
(IRO[IRO_USTORM_EQE_CONS].base \
|
||||
+ ((pf_id) * IRO[IRO_USTORM_EQE_CONS].m1))
|
||||
#define USTORM_EQE_CONS_SIZE (IRO[IRO_USTORM_EQE_CONS].size)
|
||||
|
||||
/* Ustorm pf statistics */
|
||||
#define USTORM_ETH_PF_STAT_OFFSET(pf_id) \
|
||||
(IRO[IRO_USTORM_ETH_PF_STAT].base \
|
||||
+ ((pf_id) * IRO[IRO_USTORM_ETH_PF_STAT].m1))
|
||||
#define USTORM_ETH_PF_STAT_SIZE (IRO[IRO_USTORM_ETH_PF_STAT].size)
|
||||
|
||||
/* Ustorm eth queue zone */
|
||||
#define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
|
||||
(IRO[IRO_USTORM_ETH_QUEUE_ZONE].base \
|
||||
+ ((queue_zone_id) * IRO[IRO_USTORM_ETH_QUEUE_ZONE].m1))
|
||||
#define USTORM_ETH_QUEUE_ZONE_SIZE (IRO[IRO_USTORM_ETH_QUEUE_ZONE].size)
|
||||
|
||||
/* Ustorm Final flr cleanup ack */
|
||||
#define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
|
||||
(IRO[IRO_USTORM_FLR_FINAL_ACK].base \
|
||||
+ ((pf_id) * IRO[IRO_USTORM_FLR_FINAL_ACK].m1))
|
||||
#define USTORM_FLR_FINAL_ACK_SIZE (IRO[IRO_USTORM_FLR_FINAL_ACK].size)
|
||||
|
||||
/* Ustorm Integration Test Data */
|
||||
#define USTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_USTORM_INTEG_TEST_DATA].base)
|
||||
#define USTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_USTORM_INTEG_TEST_DATA].size)
|
||||
|
||||
/* Ustorm iSCSI RX stats */
|
||||
#define USTORM_ISCSI_RX_STATS_OFFSET(storage_func_id) \
|
||||
(IRO[IRO_USTORM_ISCSI_RX_STATS].base \
|
||||
+ ((storage_func_id) * IRO[IRO_USTORM_ISCSI_RX_STATS].m1))
|
||||
#define USTORM_ISCSI_RX_STATS_SIZE (IRO[IRO_USTORM_ISCSI_RX_STATS].size)
|
||||
|
||||
/* Ustorm overlay buffer host address */
|
||||
#define USTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_USTORM_OVERLAY_BUF_ADDR].base)
|
||||
#define USTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_USTORM_OVERLAY_BUF_ADDR].size)
|
||||
|
||||
/* Ustorm queue statistics */
|
||||
#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
|
||||
(IRO[IRO_USTORM_QUEUE_STAT].base \
|
||||
+ ((stat_counter_id) * IRO[IRO_USTORM_QUEUE_STAT].m1))
|
||||
#define USTORM_QUEUE_STAT_SIZE (IRO[IRO_USTORM_QUEUE_STAT].size)
|
||||
|
||||
/* Ustorm error level for assert */
|
||||
#define USTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
|
||||
(IRO[IRO_USTORM_RDMA_ASSERT_LEVEL].base \
|
||||
+ ((pf_id) * IRO[IRO_USTORM_RDMA_ASSERT_LEVEL].m1))
|
||||
#define USTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_USTORM_RDMA_ASSERT_LEVEL].size)
|
||||
|
||||
/* RoCE CQEs Statistics */
|
||||
#define USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) \
|
||||
(IRO[66].base + ((roce_pf_id) * IRO[66].m1))
|
||||
#define USTORM_ROCE_CQE_STATS_SIZE (IRO[66].size)
|
||||
#define USTORM_ROCE_CQE_STATS_OFFSET(roce_pf_id) \
|
||||
(IRO[IRO_USTORM_ROCE_CQE_STATS].base \
|
||||
+ ((roce_pf_id) * IRO[IRO_USTORM_ROCE_CQE_STATS].m1))
|
||||
#define USTORM_ROCE_CQE_STATS_SIZE (IRO[IRO_USTORM_ROCE_CQE_STATS].size)
|
||||
|
||||
/* Ustorm cqe producer */
|
||||
#define USTORM_TOE_CQ_PROD_OFFSET(rss_id) \
|
||||
(IRO[IRO_USTORM_TOE_CQ_PROD].base \
|
||||
+ ((rss_id) * IRO[IRO_USTORM_TOE_CQ_PROD].m1))
|
||||
#define USTORM_TOE_CQ_PROD_SIZE (IRO[IRO_USTORM_TOE_CQ_PROD].size)
|
||||
|
||||
/* Ustorm grq producer */
|
||||
#define USTORM_TOE_GRQ_PROD_OFFSET(pf_id) \
|
||||
(IRO[IRO_USTORM_TOE_GRQ_PROD].base \
|
||||
+ ((pf_id) * IRO[IRO_USTORM_TOE_GRQ_PROD].m1))
|
||||
#define USTORM_TOE_GRQ_PROD_SIZE (IRO[IRO_USTORM_TOE_GRQ_PROD].size)
|
||||
|
||||
/* Ustorm VF-PF Channel ready flag */
|
||||
#define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
|
||||
(IRO[IRO_USTORM_VF_PF_CHANNEL_READY].base \
|
||||
+ ((vf_id) * IRO[IRO_USTORM_VF_PF_CHANNEL_READY].m1))
|
||||
#define USTORM_VF_PF_CHANNEL_READY_SIZE \
|
||||
(IRO[IRO_USTORM_VF_PF_CHANNEL_READY].size)
|
||||
|
||||
/* Xstorm queue zone */
|
||||
#define XSTORM_ETH_QUEUE_ZONE_OFFSET(queue_id) \
|
||||
(IRO[IRO_XSTORM_ETH_QUEUE_ZONE].base \
|
||||
+ ((queue_id) * IRO[IRO_XSTORM_ETH_QUEUE_ZONE].m1))
|
||||
#define XSTORM_ETH_QUEUE_ZONE_SIZE (IRO[IRO_XSTORM_ETH_QUEUE_ZONE].size)
|
||||
|
||||
/* Xstorm Integration Test Data */
|
||||
#define XSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_XSTORM_INTEG_TEST_DATA].base)
|
||||
#define XSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_XSTORM_INTEG_TEST_DATA].size)
|
||||
|
||||
/* Xstorm iSCSI TX stats */
|
||||
#define XSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
|
||||
(IRO[IRO_XSTORM_ISCSI_TX_STATS].base \
|
||||
+ ((storage_func_id) * IRO[IRO_XSTORM_ISCSI_TX_STATS].m1))
|
||||
#define XSTORM_ISCSI_TX_STATS_SIZE (IRO[IRO_XSTORM_ISCSI_TX_STATS].size)
|
||||
|
||||
/* Xstorm iWARP rxmit stats */
|
||||
#define XSTORM_IWARP_RXMIT_STATS_OFFSET(pf_id) \
|
||||
(IRO[IRO_XSTORM_IWARP_RXMIT_STATS].base \
|
||||
+ ((pf_id) * IRO[IRO_XSTORM_IWARP_RXMIT_STATS].m1))
|
||||
#define XSTORM_IWARP_RXMIT_STATS_SIZE (IRO[IRO_XSTORM_IWARP_RXMIT_STATS].size)
|
||||
|
||||
/* Xstorm overlay buffer host address */
|
||||
#define XSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_XSTORM_OVERLAY_BUF_ADDR].base)
|
||||
#define XSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_XSTORM_OVERLAY_BUF_ADDR].size)
|
||||
|
||||
/* Xstorm common PQ info */
|
||||
#define XSTORM_PQ_INFO_OFFSET(pq_id) \
|
||||
(IRO[IRO_XSTORM_PQ_INFO].base \
|
||||
+ ((pq_id) * IRO[IRO_XSTORM_PQ_INFO].m1))
|
||||
#define XSTORM_PQ_INFO_SIZE (IRO[IRO_XSTORM_PQ_INFO].size)
|
||||
|
||||
/* Xstorm error level for assert */
|
||||
#define XSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
|
||||
(IRO[IRO_XSTORM_RDMA_ASSERT_LEVEL].base \
|
||||
+ ((pf_id) * IRO[IRO_XSTORM_RDMA_ASSERT_LEVEL].m1))
|
||||
#define XSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_XSTORM_RDMA_ASSERT_LEVEL].size)
|
||||
|
||||
/* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
|
||||
#define YSTORM_FLOW_CONTROL_MODE_OFFSET (IRO[IRO_YSTORM_FLOW_CONTROL_MODE].base)
|
||||
#define YSTORM_FLOW_CONTROL_MODE_SIZE (IRO[IRO_YSTORM_FLOW_CONTROL_MODE].size)
|
||||
|
||||
/* Ystorm Integration Test Data */
|
||||
#define YSTORM_INTEG_TEST_DATA_OFFSET (IRO[IRO_YSTORM_INTEG_TEST_DATA].base)
|
||||
#define YSTORM_INTEG_TEST_DATA_SIZE (IRO[IRO_YSTORM_INTEG_TEST_DATA].size)
|
||||
|
||||
/* Ystorm iSCSI TX stats */
|
||||
#define YSTORM_ISCSI_TX_STATS_OFFSET(storage_func_id) \
|
||||
(IRO[IRO_YSTORM_ISCSI_TX_STATS].base \
|
||||
+ ((storage_func_id) * IRO[IRO_YSTORM_ISCSI_TX_STATS].m1))
|
||||
#define YSTORM_ISCSI_TX_STATS_SIZE (IRO[IRO_YSTORM_ISCSI_TX_STATS].size)
|
||||
|
||||
/* Ystorm overlay buffer host address */
|
||||
#define YSTORM_OVERLAY_BUF_ADDR_OFFSET (IRO[IRO_YSTORM_OVERLAY_BUF_ADDR].base)
|
||||
#define YSTORM_OVERLAY_BUF_ADDR_SIZE (IRO[IRO_YSTORM_OVERLAY_BUF_ADDR].size)
|
||||
|
||||
/* Ystorm error level for assert */
|
||||
#define YSTORM_RDMA_ASSERT_LEVEL_OFFSET(pf_id) \
|
||||
(IRO[IRO_YSTORM_RDMA_ASSERT_LEVEL].base \
|
||||
+ ((pf_id) * IRO[IRO_YSTORM_RDMA_ASSERT_LEVEL].m1))
|
||||
#define YSTORM_RDMA_ASSERT_LEVEL_SIZE (IRO[IRO_YSTORM_RDMA_ASSERT_LEVEL].size)
|
||||
|
||||
/* DCQCN Received Statistics */
|
||||
#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_OFFSET(roce_pf_id) \
|
||||
(IRO[IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS].base \
|
||||
+ ((roce_pf_id) * IRO[IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS].m1))
|
||||
#define YSTORM_ROCE_DCQCN_RECEIVED_STATS_SIZE \
|
||||
(IRO[IRO_YSTORM_ROCE_DCQCN_RECEIVED_STATS].size)
|
||||
|
||||
/* RoCE Error Statistics */
|
||||
#define YSTORM_ROCE_ERROR_STATS_OFFSET(roce_pf_id) \
|
||||
(IRO[IRO_YSTORM_ROCE_ERROR_STATS].base \
|
||||
+ ((roce_pf_id) * IRO[IRO_YSTORM_ROCE_ERROR_STATS].m1))
|
||||
#define YSTORM_ROCE_ERROR_STATS_SIZE (IRO[IRO_YSTORM_ROCE_ERROR_STATS].size)
|
||||
|
||||
/* Ystorm cqe producer */
|
||||
#define YSTORM_TOE_CQ_PROD_OFFSET(rss_id) \
|
||||
(IRO[IRO_YSTORM_TOE_CQ_PROD].base \
|
||||
+ ((rss_id) * IRO[IRO_YSTORM_TOE_CQ_PROD].m1))
|
||||
#define YSTORM_TOE_CQ_PROD_SIZE (IRO[IRO_YSTORM_TOE_CQ_PROD].size)
|
||||
|
||||
/* Per-chip offsets in iro_arr in dwords */
|
||||
#define E4_IRO_ARR_OFFSET 0
|
||||
#endif
|
||||
|
||||
Loading…
Reference in New Issue
Block a user