Merge branch 'pci/hotplug'
- Disable in-band presence detection when possible (Alexandru Gagniuc)
- Poll for presence detect if in-band presence detection is disabled
(Alexandru Gagniuc)
- Add DMI table of systems that don't support in-band presence detection
(Stuart Hayes)
- Fix indefinite pciehp wait caused by race in handling sysfs requests
(Lukas Wunner)
- Fix pciehp MSI interrupt race that caused us to miss interrupts (Stuart
Hayes)
* pci/hotplug:
PCI: pciehp: Fix MSI interrupt race
PCI: pciehp: Fix indefinite wait on sysfs requests
PCI: pciehp: Add DMI table for in-band presence detection disabled
PCI: pciehp: Wait for PDS if in-band presence is disabled
PCI: pciehp: Disable in-band presence detect when possible
This commit is contained in:
Bjorn Helgaas
commit
3038685357
@ -84,6 +84,7 @@ struct controller {
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struct pcie_device *pcie;
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u32 slot_cap; /* capabilities and quirks */
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unsigned int inband_presence_disabled:1;
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u16 slot_ctrl; /* control register access */
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struct mutex ctrl_lock;
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@ -14,6 +14,7 @@
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#define dev_fmt(fmt) "pciehp: " fmt
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#include <linux/dmi.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/jiffies.h>
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@ -26,6 +27,24 @@
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#include "../pci.h"
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#include "pciehp.h"
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static const struct dmi_system_id inband_presence_disabled_dmi_table[] = {
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/*
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* Match all Dell systems, as some Dell systems have inband
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* presence disabled on NVMe slots (but don't support the bit to
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* report it). Setting inband presence disabled should have no
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* negative effect, except on broken hotplug slots that never
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* assert presence detect--and those will still work, they will
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* just have a bit of extra delay before being probed.
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*/
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{
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.ident = "Dell System",
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.matches = {
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DMI_MATCH(DMI_OEM_STRING, "Dell System"),
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},
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},
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{}
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};
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static inline struct pci_dev *ctrl_dev(struct controller *ctrl)
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{
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return ctrl->pcie->port;
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@ -252,6 +271,22 @@ static bool pci_bus_check_dev(struct pci_bus *bus, int devfn)
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return found;
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}
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static void pcie_wait_for_presence(struct pci_dev *pdev)
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{
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int timeout = 1250;
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u16 slot_status;
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do {
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pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &slot_status);
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if (slot_status & PCI_EXP_SLTSTA_PDS)
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return;
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msleep(10);
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timeout -= 10;
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} while (timeout > 0);
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pci_info(pdev, "Timeout waiting for Presence Detect\n");
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}
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int pciehp_check_link_status(struct controller *ctrl)
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{
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struct pci_dev *pdev = ctrl_dev(ctrl);
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@ -261,6 +296,9 @@ int pciehp_check_link_status(struct controller *ctrl)
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if (!pcie_wait_for_link(pdev, true))
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return -1;
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if (ctrl->inband_presence_disabled)
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pcie_wait_for_presence(pdev);
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found = pci_bus_check_dev(ctrl->pcie->port->subordinate,
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PCI_DEVFN(0, 0));
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@ -527,7 +565,7 @@ static irqreturn_t pciehp_isr(int irq, void *dev_id)
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struct controller *ctrl = (struct controller *)dev_id;
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struct pci_dev *pdev = ctrl_dev(ctrl);
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struct device *parent = pdev->dev.parent;
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u16 status, events;
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u16 status, events = 0;
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/*
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* Interrupts only occur in D3hot or shallower and only if enabled
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@ -552,6 +590,7 @@ static irqreturn_t pciehp_isr(int irq, void *dev_id)
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}
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}
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read_status:
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pcie_capability_read_word(pdev, PCI_EXP_SLTSTA, &status);
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if (status == (u16) ~0) {
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ctrl_info(ctrl, "%s: no response from device\n", __func__);
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@ -564,24 +603,37 @@ static irqreturn_t pciehp_isr(int irq, void *dev_id)
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* Slot Status contains plain status bits as well as event
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* notification bits; right now we only want the event bits.
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*/
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events = status & (PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
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PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
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PCI_EXP_SLTSTA_DLLSC);
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status &= PCI_EXP_SLTSTA_ABP | PCI_EXP_SLTSTA_PFD |
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PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_CC |
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PCI_EXP_SLTSTA_DLLSC;
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/*
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* If we've already reported a power fault, don't report it again
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* until we've done something to handle it.
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*/
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if (ctrl->power_fault_detected)
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events &= ~PCI_EXP_SLTSTA_PFD;
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status &= ~PCI_EXP_SLTSTA_PFD;
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events |= status;
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if (!events) {
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if (parent)
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pm_runtime_put(parent);
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return IRQ_NONE;
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}
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pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events);
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if (status) {
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pcie_capability_write_word(pdev, PCI_EXP_SLTSTA, events);
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/*
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* In MSI mode, all event bits must be zero before the port
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* will send a new interrupt (PCIe Base Spec r5.0 sec 6.7.3.4).
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* So re-read the Slot Status register in case a bit was set
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* between read and write.
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*/
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if (pci_dev_msi_enabled(pdev) && !pciehp_poll_mode)
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goto read_status;
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}
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ctrl_dbg(ctrl, "pending interrupts %#06x from Slot Status\n", events);
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if (parent)
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pm_runtime_put(parent);
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@ -625,17 +677,15 @@ static irqreturn_t pciehp_ist(int irq, void *dev_id)
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if (atomic_fetch_and(~RERUN_ISR, &ctrl->pending_events) & RERUN_ISR) {
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ret = pciehp_isr(irq, dev_id);
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enable_irq(irq);
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if (ret != IRQ_WAKE_THREAD) {
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pci_config_pm_runtime_put(pdev);
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return ret;
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}
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if (ret != IRQ_WAKE_THREAD)
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goto out;
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}
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synchronize_hardirq(irq);
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events = atomic_xchg(&ctrl->pending_events, 0);
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if (!events) {
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pci_config_pm_runtime_put(pdev);
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return IRQ_NONE;
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ret = IRQ_NONE;
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goto out;
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}
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/* Check Attention Button Pressed */
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@ -664,10 +714,12 @@ static irqreturn_t pciehp_ist(int irq, void *dev_id)
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pciehp_handle_presence_or_link_change(ctrl, events);
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up_read(&ctrl->reset_lock);
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ret = IRQ_HANDLED;
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out:
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pci_config_pm_runtime_put(pdev);
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ctrl->ist_running = false;
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wake_up(&ctrl->requester);
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return IRQ_HANDLED;
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return ret;
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}
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static int pciehp_poll(void *data)
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@ -848,7 +900,7 @@ static inline void dbg_ctrl(struct controller *ctrl)
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struct controller *pcie_init(struct pcie_device *dev)
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{
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struct controller *ctrl;
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u32 slot_cap, link_cap;
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u32 slot_cap, slot_cap2, link_cap;
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u8 poweron;
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struct pci_dev *pdev = dev->port;
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struct pci_bus *subordinate = pdev->subordinate;
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@ -883,6 +935,16 @@ struct controller *pcie_init(struct pcie_device *dev)
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ctrl->state = list_empty(&subordinate->devices) ? OFF_STATE : ON_STATE;
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up_read(&pci_bus_sem);
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pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP2, &slot_cap2);
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if (slot_cap2 & PCI_EXP_SLTCAP2_IBPD) {
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pcie_write_cmd_nowait(ctrl, PCI_EXP_SLTCTL_IBPD_DISABLE,
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PCI_EXP_SLTCTL_IBPD_DISABLE);
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ctrl->inband_presence_disabled = 1;
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}
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if (dmi_first_match(inband_presence_disabled_dmi_table))
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ctrl->inband_presence_disabled = 1;
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/* Check if Data Link Layer Link Active Reporting is implemented */
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pcie_capability_read_dword(pdev, PCI_EXP_LNKCAP, &link_cap);
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@ -892,7 +954,7 @@ struct controller *pcie_init(struct pcie_device *dev)
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PCI_EXP_SLTSTA_MRLSC | PCI_EXP_SLTSTA_CC |
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PCI_EXP_SLTSTA_DLLSC | PCI_EXP_SLTSTA_PDC);
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ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c LLActRep%c%s\n",
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ctrl_info(ctrl, "Slot #%d AttnBtn%c PwrCtrl%c MRL%c AttnInd%c PwrInd%c HotPlug%c Surprise%c Interlock%c NoCompl%c IbPresDis%c LLActRep%c%s\n",
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(slot_cap & PCI_EXP_SLTCAP_PSN) >> 19,
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FLAG(slot_cap, PCI_EXP_SLTCAP_ABP),
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FLAG(slot_cap, PCI_EXP_SLTCAP_PCP),
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@ -903,6 +965,7 @@ struct controller *pcie_init(struct pcie_device *dev)
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FLAG(slot_cap, PCI_EXP_SLTCAP_HPS),
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FLAG(slot_cap, PCI_EXP_SLTCAP_EIP),
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FLAG(slot_cap, PCI_EXP_SLTCAP_NCCS),
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FLAG(slot_cap2, PCI_EXP_SLTCAP2_IBPD),
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FLAG(link_cap, PCI_EXP_LNKCAP_DLLLARC),
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pdev->broken_cmd_compl ? " (with Cmd Compl erratum)" : "");
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@ -605,6 +605,7 @@
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#define PCI_EXP_SLTCTL_PWR_OFF 0x0400 /* Power Off */
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#define PCI_EXP_SLTCTL_EIC 0x0800 /* Electromechanical Interlock Control */
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#define PCI_EXP_SLTCTL_DLLSCE 0x1000 /* Data Link Layer State Changed Enable */
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#define PCI_EXP_SLTCTL_IBPD_DISABLE 0x4000 /* In-band PD disable */
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#define PCI_EXP_SLTSTA 26 /* Slot Status */
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#define PCI_EXP_SLTSTA_ABP 0x0001 /* Attention Button Pressed */
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#define PCI_EXP_SLTSTA_PFD 0x0002 /* Power Fault Detected */
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@ -680,6 +681,7 @@
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#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
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#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
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#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
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#define PCI_EXP_SLTCAP2_IBPD 0x00000001 /* In-band PD Disable Supported */
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#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
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#define PCI_EXP_SLTSTA2 58 /* Slot Status 2 */
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