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soc: mediatek: pwrap: add support for MT6359 PMIC

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MT6359 is a new power management IC and it is used for
MT6779 SoCs. To define mt6359_regs for pmic register mapping
and pmic_mt6359 for accessing register.

Signed-off-by: Argus Lin <argus.lin@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Argus Lin 2020-02-16 14:17:23 +08:00 committed by Matthias Brugger
parent adc4e8fcb2
commit 2faccb56ee
1 changed files with 71 additions and 0 deletions
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71
drivers/soc/mediatek/mtk-pmic-wrap.c
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@ -111,6 +111,28 @@ enum dew_regs {
PWRAP_RG_SPI_CON13,
PWRAP_SPISLV_KEY,
/* MT6359 only regs */
PWRAP_DEW_CRC_SWRST,
PWRAP_DEW_RG_EN_RECORD,
PWRAP_DEW_RECORD_CMD0,
PWRAP_DEW_RECORD_CMD1,
PWRAP_DEW_RECORD_CMD2,
PWRAP_DEW_RECORD_CMD3,
PWRAP_DEW_RECORD_CMD4,
PWRAP_DEW_RECORD_CMD5,
PWRAP_DEW_RECORD_WDATA0,
PWRAP_DEW_RECORD_WDATA1,
PWRAP_DEW_RECORD_WDATA2,
PWRAP_DEW_RECORD_WDATA3,
PWRAP_DEW_RECORD_WDATA4,
PWRAP_DEW_RECORD_WDATA5,
PWRAP_DEW_RG_ADDR_TARGET,
PWRAP_DEW_RG_ADDR_MASK,
PWRAP_DEW_RG_WDATA_TARGET,
PWRAP_DEW_RG_WDATA_MASK,
PWRAP_DEW_RG_SPI_RECORD_CLR,
PWRAP_DEW_RG_CMD_ALERT_CLR,
/* MT6397 only regs */
PWRAP_DEW_EVENT_OUT_EN,
PWRAP_DEW_EVENT_SRC_EN,
@ -197,6 +219,42 @@ static const u32 mt6358_regs[] = {
[PWRAP_SPISLV_KEY] = 0x044a,
};
static const u32 mt6359_regs[] = {
[PWRAP_DEW_RG_EN_RECORD] = 0x040a,
[PWRAP_DEW_DIO_EN] = 0x040c,
[PWRAP_DEW_READ_TEST] = 0x040e,
[PWRAP_DEW_WRITE_TEST] = 0x0410,
[PWRAP_DEW_CRC_SWRST] = 0x0412,
[PWRAP_DEW_CRC_EN] = 0x0414,
[PWRAP_DEW_CRC_VAL] = 0x0416,
[PWRAP_DEW_CIPHER_KEY_SEL] = 0x0418,
[PWRAP_DEW_CIPHER_IV_SEL] = 0x041a,
[PWRAP_DEW_CIPHER_EN] = 0x041c,
[PWRAP_DEW_CIPHER_RDY] = 0x041e,
[PWRAP_DEW_CIPHER_MODE] = 0x0420,
[PWRAP_DEW_CIPHER_SWRST] = 0x0422,
[PWRAP_DEW_RDDMY_NO] = 0x0424,
[PWRAP_DEW_RECORD_CMD0] = 0x0428,
[PWRAP_DEW_RECORD_CMD1] = 0x042a,
[PWRAP_DEW_RECORD_CMD2] = 0x042c,
[PWRAP_DEW_RECORD_CMD3] = 0x042e,
[PWRAP_DEW_RECORD_CMD4] = 0x0430,
[PWRAP_DEW_RECORD_CMD5] = 0x0432,
[PWRAP_DEW_RECORD_WDATA0] = 0x0434,
[PWRAP_DEW_RECORD_WDATA1] = 0x0436,
[PWRAP_DEW_RECORD_WDATA2] = 0x0438,
[PWRAP_DEW_RECORD_WDATA3] = 0x043a,
[PWRAP_DEW_RECORD_WDATA4] = 0x043c,
[PWRAP_DEW_RECORD_WDATA5] = 0x043e,
[PWRAP_DEW_RG_ADDR_TARGET] = 0x0440,
[PWRAP_DEW_RG_ADDR_MASK] = 0x0442,
[PWRAP_DEW_RG_WDATA_TARGET] = 0x0444,
[PWRAP_DEW_RG_WDATA_MASK] = 0x0446,
[PWRAP_DEW_RG_SPI_RECORD_CLR] = 0x0448,
[PWRAP_DEW_RG_CMD_ALERT_CLR] = 0x0448,
[PWRAP_SPISLV_KEY] = 0x044a,
};
static const u32 mt6397_regs[] = {
[PWRAP_DEW_BASE] = 0xbc00,
[PWRAP_DEW_EVENT_OUT_EN] = 0xbc00,
@ -977,6 +1035,7 @@ enum pmic_type {
PMIC_MT6351,
PMIC_MT6357,
PMIC_MT6358,
PMIC_MT6359,
PMIC_MT6380,
PMIC_MT6397,
};
@ -1752,6 +1811,15 @@ static const struct pwrap_slv_type pmic_mt6358 = {
.pwrap_write = pwrap_write16,
};
static const struct pwrap_slv_type pmic_mt6359 = {
.dew_regs = mt6359_regs,
.type = PMIC_MT6359,
.regmap = &pwrap_regmap_config16,
.caps = PWRAP_SLV_CAP_DUALIO,
.pwrap_read = pwrap_read16,
.pwrap_write = pwrap_write16,
};
static const struct pwrap_slv_type pmic_mt6380 = {
.dew_regs = NULL,
.type = PMIC_MT6380,
@ -1784,6 +1852,9 @@ static const struct of_device_id of_slave_match_tbl[] = {
}, {
.compatible = "mediatek,mt6358",
.data = &pmic_mt6358,
}, {
.compatible = "mediatek,mt6359",
.data = &pmic_mt6359,
}, {
/* The MT6380 PMIC only implements a regulator, so we bind it
* directly instead of using a MFD.