forked from Minki/linux
arm64: dts: hisilicon: add dts files for hi3798cv200-poplar board
Add basic dts files for hi3798cv200-poplar board. Poplar is the first development board compliant with the 96Boards Enterprise Edition TV Platform specification. The board features the Hi3798CV200 with an integrated quad-core 64-bit ARM Cortex A53 processor and high performance Mali T720 GPU. Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Reviewed-by: Alex Elder <elder@linaro.org> Acked-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This commit is contained in:
Jiancheng Xue
Wei Xu
parent
b96df86307
commit
2f20182ed6
@ -1,4 +1,5 @@
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dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb
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dtb-$(CONFIG_ARCH_HISI) += hi3798cv200-poplar.dtb
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dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
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dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
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dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
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162
arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
Normal file
162
arch/arm64/boot/dts/hisilicon/hi3798cv200-poplar.dts
Normal file
@ -0,0 +1,162 @@
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/*
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* DTS File for HiSilicon Poplar Development Board
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*
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* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
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*
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* Released under the GPLv2 only.
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* SPDX-License-Identifier: GPL-2.0
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "hi3798cv200.dtsi"
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/ {
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model = "HiSilicon Poplar Development Board";
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compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200";
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aliases {
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serial0 = &uart0;
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serial2 = &uart2;
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};
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0 0x0 0x80000000>;
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};
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leds {
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compatible = "gpio-leds";
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user-led0 {
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label = "USER-LED0";
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gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "heartbeat";
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default-state = "off";
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};
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user-led1 {
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label = "USER-LED1";
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gpios = <&gpio5 1 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "mmc0";
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default-state = "off";
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};
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user-led2 {
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label = "USER-LED2";
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gpios = <&gpio5 2 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "none";
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default-state = "off";
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};
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user-led3 {
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label = "USER-LED3";
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gpios = <&gpio10 6 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "cpu0";
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default-state = "off";
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};
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};
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};
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&gmac1 {
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status = "okay";
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#address-cells = <1>;
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#size-cells = <0>;
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phy-handle = <ð_phy1>;
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phy-mode = "rgmii";
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hisilicon,phy-reset-delays-us = <10000 10000 30000>;
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eth_phy1: phy@3 {
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reg = <3>;
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};
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};
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&gpio1 {
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status = "okay";
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gpio-line-names = "LS-GPIO-E", "",
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"", "",
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"", "LS-GPIO-F",
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"", "LS-GPIO-J";
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};
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&gpio2 {
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status = "okay";
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gpio-line-names = "LS-GPIO-H", "LS-GPIO-I",
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"LS-GPIO-L", "LS-GPIO-G",
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"LS-GPIO-K", "",
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"", "";
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};
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&gpio3 {
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status = "okay";
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gpio-line-names = "", "",
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"", "",
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"LS-GPIO-C", "",
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"", "LS-GPIO-B";
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};
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&gpio4 {
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status = "okay";
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gpio-line-names = "", "",
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"", "",
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"", "LS-GPIO-D",
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"", "";
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};
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&gpio5 {
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status = "okay";
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gpio-line-names = "", "USER-LED-1",
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"USER-LED-2", "",
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"", "LS-GPIO-A",
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"", "";
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};
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&gpio6 {
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status = "okay";
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gpio-line-names = "", "",
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"", "USER-LED-0",
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"", "",
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"", "";
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};
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&gpio10 {
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status = "okay";
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gpio-line-names = "", "",
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"", "",
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"", "",
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"USER-LED-3", "";
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};
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&i2c0 {
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status = "okay";
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label = "LS-I2C0";
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};
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&i2c2 {
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status = "okay";
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label = "LS-I2C1";
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};
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&ir {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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label = "LS-SPI0";
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};
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&uart0 {
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status = "okay";
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};
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&uart2 {
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status = "okay";
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label = "LS-UART0";
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};
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/* No optional LS-UART1 on Low Speed Expansion Connector. */
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411
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
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411
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
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@ -0,0 +1,411 @@
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/*
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* DTS File for HiSilicon Hi3798cv200 SoC.
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*
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* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
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*
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* Released under the GPLv2 only.
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <dt-bindings/clock/histb-clock.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/reset/ti-syscon.h>
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/ {
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compatible = "hisilicon,hi3798cv200";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu@0 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x0 0x0>;
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enable-method = "psci";
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};
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cpu@1 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x0 0x1>;
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enable-method = "psci";
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};
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cpu@2 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x0 0x2>;
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enable-method = "psci";
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};
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cpu@3 {
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compatible = "arm,cortex-a53";
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device_type = "cpu";
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reg = <0x0 0x3>;
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enable-method = "psci";
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};
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};
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gic: interrupt-controller@f1001000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xf1001000 0x0 0x1000>, /* GICD */
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<0x0 0xf1002000 0x0 0x100>; /* GICC */
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#address-cells = <0>;
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#interrupt-cells = <3>;
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interrupt-controller;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) |
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IRQ_TYPE_LEVEL_LOW)>;
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};
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soc: soc@f0000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x0 0xf0000000 0x10000000>;
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crg: clock-reset-controller@8a22000 {
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compatible = "hisilicon,hi3798cv200-crg", "syscon", "simple-mfd";
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reg = <0x8a22000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <2>;
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gmacphyrst: reset-controller {
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compatible = "ti,syscon-reset";
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#reset-cells = <1>;
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ti,reset-bits =
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<0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |
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DEASSERT_SET|STATUS_NONE)>,
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<0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |
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DEASSERT_SET|STATUS_NONE)>;
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};
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};
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sysctrl: system-controller@8000000 {
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compatible = "hisilicon,hi3798cv200-sysctrl", "syscon";
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reg = <0x8000000 0x1000>;
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#clock-cells = <1>;
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#reset-cells = <2>;
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};
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uart0: serial@8b00000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x8b00000 0x1000>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&sysctrl HISTB_UART0_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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uart2: serial@8b02000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x8b02000 0x1000>;
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interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HISTB_UART2_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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i2c0: i2c@8b10000 {
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compatible = "hisilicon,hix5hd2-i2c";
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reg = <0x8b10000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>;
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clocks = <&crg HISTB_I2C0_CLK>;
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status = "disabled";
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};
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i2c1: i2c@8b11000 {
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compatible = "hisilicon,hix5hd2-i2c";
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reg = <0x8b11000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>;
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clocks = <&crg HISTB_I2C1_CLK>;
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status = "disabled";
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};
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i2c2: i2c@8b12000 {
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compatible = "hisilicon,hix5hd2-i2c";
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reg = <0x8b12000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>;
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clocks = <&crg HISTB_I2C2_CLK>;
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status = "disabled";
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};
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i2c3: i2c@8b13000 {
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compatible = "hisilicon,hix5hd2-i2c";
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reg = <0x8b13000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>;
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clocks = <&crg HISTB_I2C3_CLK>;
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status = "disabled";
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};
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i2c4: i2c@8b14000 {
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compatible = "hisilicon,hix5hd2-i2c";
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reg = <0x8b14000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
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clock-frequency = <400000>;
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clocks = <&crg HISTB_I2C4_CLK>;
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status = "disabled";
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};
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spi0: spi@8b1a000 {
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compatible = "arm,pl022", "arm,primecell";
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reg = <0x8b1a000 0x1000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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num-cs = <1>;
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cs-gpios = <&gpio7 1 0>;
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clocks = <&crg HISTB_SPI0_CLK>;
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clock-names = "apb_pclk";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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emmc: mmc@9830000 {
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compatible = "snps,dw-mshc";
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reg = <0x9830000 0x10000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HISTB_MMC_CIU_CLK>,
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<&crg HISTB_MMC_BIU_CLK>;
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clock-names = "ciu", "biu";
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};
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gpio0: gpio@8b20000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8b20000 0x1000>;
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interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio1: gpio@8b21000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8b21000 0x1000>;
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interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio2: gpio@8b22000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8b22000 0x1000>;
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interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio3: gpio@8b23000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8b23000 0x1000>;
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interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio4: gpio@8b24000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8b24000 0x1000>;
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interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio5: gpio@8004000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8004000 0x1000>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio6: gpio@8b26000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8b26000 0x1000>;
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interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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};
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gpio7: gpio@8b27000 {
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compatible = "arm,pl061", "arm,primecell";
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reg = <0x8b27000 0x1000>;
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interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&crg HISTB_APB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio8: gpio@8b28000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x8b28000 0x1000>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&crg HISTB_APB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio9: gpio@8b29000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x8b29000 0x1000>;
|
||||
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&crg HISTB_APB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio10: gpio@8b2a000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x8b2a000 0x1000>;
|
||||
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&crg HISTB_APB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio11: gpio@8b2b000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x8b2b000 0x1000>;
|
||||
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&crg HISTB_APB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio12: gpio@8b2c000 {
|
||||
compatible = "arm,pl061", "arm,primecell";
|
||||
reg = <0x8b2c000 0x1000>;
|
||||
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
clocks = <&crg HISTB_APB_CLK>;
|
||||
clock-names = "apb_pclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac0: ethernet@9840000 {
|
||||
compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
|
||||
reg = <0x9840000 0x1000>,
|
||||
<0x984300c 0x4>;
|
||||
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&crg HISTB_ETH0_MAC_CLK>,
|
||||
<&crg HISTB_ETH0_MACIF_CLK>;
|
||||
clock-names = "mac_core", "mac_ifc";
|
||||
resets = <&crg 0xcc 8>,
|
||||
<&crg 0xcc 10>,
|
||||
<&gmacphyrst 0>;
|
||||
reset-names = "mac_core", "mac_ifc", "phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gmac1: ethernet@9841000 {
|
||||
compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
|
||||
reg = <0x9841000 0x1000>,
|
||||
<0x9843010 0x4>;
|
||||
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&crg HISTB_ETH1_MAC_CLK>,
|
||||
<&crg HISTB_ETH1_MACIF_CLK>;
|
||||
clock-names = "mac_core", "mac_ifc";
|
||||
resets = <&crg 0xcc 9>,
|
||||
<&crg 0xcc 11>,
|
||||
<&gmacphyrst 1>;
|
||||
reset-names = "mac_core", "mac_ifc", "phy";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ir: ir@8001000 {
|
||||
compatible = "hisilicon,hix5hd2-ir";
|
||||
reg = <0x8001000 0x1000>;
|
||||
interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&sysctrl HISTB_IR_CLK>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user