drm/amd/amdgpu: Tidy up of gfx_v6_0_setup_rb()
Signed-off-by: Tom St Denis <tom.stdenis@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -1271,8 +1271,9 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
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for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
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gfx_v6_0_select_se_sh(adev, i, j, 0xffffffff);
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data = gfx_v6_0_get_rb_active_bitmap(adev);
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active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
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rb_bitmap_width_per_sh);
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active_rbs |= data <<
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((i * adev->gfx.config.max_sh_per_se + j) *
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rb_bitmap_width_per_sh);
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}
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}
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gfx_v6_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
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@ -1286,13 +1287,12 @@ static void gfx_v6_0_setup_rb(struct amdgpu_device *adev)
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gfx_v6_0_raster_config(adev, &raster_config);
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if (!adev->gfx.config.backend_enable_mask ||
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adev->gfx.config.num_rbs >= num_rb_pipes) {
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adev->gfx.config.num_rbs >= num_rb_pipes)
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WREG32(mmPA_SC_RASTER_CONFIG, raster_config);
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} else {
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else
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gfx_v6_0_write_harvested_raster_configs(adev, raster_config,
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adev->gfx.config.backend_enable_mask,
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num_rb_pipes);
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}
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/* cache the values for userspace */
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for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
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