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dt-bindings: devfreq: rk3399_dmc: improve binding documentation.

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There are several typos, references to non existent files, grammar and
punctuation mistakes in the rk3399_dmc.txt binding. This patch tries
to improve the binding documentation and fix these mistakes.

Signed-off-by: Nick Milner <nick.milner@collabora.com>
Signed-off-by: Enric Balletbo i Serra <enric.balletbo@collabora.com>
Reviewed-by: Rob Herring <robh@kernel.org>
- [1/5] Fix some attributes to match with the code s/_disb/_dis/
Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com>
This commit is contained in:
Nick Milner 2018-05-09 14:57:43 +02:00 committed by MyungJoo Ham
parent 2d803dc8f7
commit 2d2894c94a
1 changed files with 96 additions and 93 deletions
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189
Documentation/devicetree/bindings/devfreq/rk3399_dmc.txt
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@ -1,14 +1,14 @@
* Rockchip rk3399 DMC(Dynamic Memory Controller) device * Rockchip rk3399 DMC (Dynamic Memory Controller) device
Required properties: Required properties:
- compatible: Must be "rockchip,rk3399-dmc". - compatible: Must be "rockchip,rk3399-dmc".
- devfreq-events: Node to get DDR loading, Refer to - devfreq-events: Node to get DDR loading, Refer to
Documentation/devicetree/bindings/devfreq/ Documentation/devicetree/bindings/devfreq/event/
rockchip-dfi.txt rockchip-dfi.txt
- interrupts: The interrupt number to the CPU. The interrupt - interrupts: The CPU interrupt number. The interrupt specifier
specifier format depends on the interrupt controller. format depends on the interrupt controller.
It should be DCF interrupts, when DDR dvfs finish, It should be a DCF interrupt. When DDR DVFS finishes
it will happen. a DCF interrupt is triggered.
- clocks: Phandles for clock specified in "clock-names" property - clocks: Phandles for clock specified in "clock-names" property
- clock-names : The name of clock used by the DFI, must be - clock-names : The name of clock used by the DFI, must be
"pclk_ddr_mon"; "pclk_ddr_mon";
@ -17,139 +17,142 @@ Required properties:
- center-supply: DMC supply node. - center-supply: DMC supply node.
- status: Marks the node enabled/disabled. - status: Marks the node enabled/disabled.
Following properties are ddr timing: Following properties relate to DDR timing:
- rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/ddr.h, - rockchip,dram_speed_bin : Value reference include/dt-bindings/clock/ddr.h,
it select ddr3 cl-trp-trcd type, default value it selects the DDR3 cl-trp-trcd type. It must be
"DDR3_DEFAULT".it must selected according to set according to "Speed Bin" in DDR3 datasheet,
"Speed Bin" in ddr3 datasheet, DO NOT use DO NOT use a smaller "Speed Bin" than specified
smaller "Speed Bin" than ddr3 exactly is. for the DDR3 being used.
- rockchip,pd_idle : Config the PD_IDLE value, defined the power-down - rockchip,pd_idle : Configure the PD_IDLE value. Defines the
idle period, memories are places into power-down power-down idle period in which memories are
mode if bus is idle for PD_IDLE DFI clocks. placed into power-down mode if bus is idle
for PD_IDLE DFI clock cycles.
- rockchip,sr_idle : Configure the SR_IDLE value, defined the - rockchip,sr_idle : Configure the SR_IDLE value. Defines the
selfrefresh idle period, memories are places self-refresh idle period in which memories are
into self-refresh mode if bus is idle for placed into self-refresh mode if bus is idle
SR_IDLE*1024 DFI clocks (DFI clocks freq is for SR_IDLE * 1024 DFI clock cycles (DFI
half of dram's clocks), defaule value is "0". clocks freq is half of DRAM clock), default
value is "0".
- rockchip,sr_mc_gate_idle : Defined the self-refresh with memory and - rockchip,sr_mc_gate_idle : Defines the memory self-refresh and controller
controller clock gating idle period, memories clock gating idle period. Memories are placed
are places into self-refresh mode and memory into self-refresh mode and memory controller
controller clock arg gating if bus is idle for clock arg gating started if bus is idle for
sr_mc_gate_idle*1024 DFI clocks. sr_mc_gate_idle*1024 DFI clock cycles.
- rockchip,srpd_lite_idle : Defined the self-refresh power down idle - rockchip,srpd_lite_idle : Defines the self-refresh power down idle
period, memories are places into self-refresh period in which memories are placed into
power down mode if bus is idle for self-refresh power down mode if bus is idle
srpd_lite_idle*1024 DFI clocks. This parameter for srpd_lite_idle * 1024 DFI clock cycles.
is for LPDDR4 only. This parameter is for LPDDR4 only.
- rockchip,standby_idle : Defined the standby idle period, memories are - rockchip,standby_idle : Defines the standby idle period in which
places into self-refresh than controller, pi, memories are placed into self-refresh mode.
phy and dram clock will gating if bus is idle The controller, pi, PHY and DRAM clock will
for standby_idle * DFI clocks. be gated if bus is idle for standby_idle * DFI
clock cycles.
- rockchip,dram_dll_disb_freq : It's defined the DDR3 dll bypass frequency in - rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
MHz, when ddr freq less than DRAM_DLL_DISB_FREQ, When DDR frequency is less than DRAM_DLL_DISB_FREQ,
ddr3 dll will bypssed note: if dll was bypassed, DDR3 DLL will be bypassed. Note: if DLL was bypassed,
the odt also stop working. the odt will also stop working.
- rockchip,phy_dll_disb_freq : Defined the PHY dll bypass frequency in - rockchip,phy_dll_dis_freq : Defines the PHY dll bypass frequency in
MHz (Mega Hz), when ddr freq less than MHz (Mega Hz). When DDR frequency is less than
DRAM_DLL_DISB_FREQ, phy dll will bypssed. DRAM_DLL_DISB_FREQ, PHY DLL will be bypassed.
note: phy dll and phy odt are independent. Note: PHY DLL and PHY ODT are independent.
- rockchip,ddr3_odt_disb_freq : When dram type is DDR3, this parameter defined - rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines
the odt disable frequency in MHz (Mega Hz), the ODT disable frequency in MHz (Mega Hz).
when ddr frequency less then ddr3_odt_disb_freq, when the DDR frequency is less then ddr3_odt_dis_freq,
the odt on dram side and controller side are the ODT on the DRAM side and controller side are
both disabled. both disabled.
- rockchip,ddr3_drv : When dram type is DDR3, this parameter define - rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
the dram side driver stength in ohm, default the DRAM side driver strength in ohms. Default
value is DDR3_DS_40ohm. value is DDR3_DS_40ohm.
- rockchip,ddr3_odt : When dram type is DDR3, this parameter define - rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
the dram side ODT stength in ohm, default value the DRAM side ODT strength in ohms. Default value
is DDR3_ODT_120ohm. is DDR3_ODT_120ohm.
- rockchip,phy_ddr3_ca_drv : When dram type is DDR3, this parameter define - rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
the phy side CA line(incluing command line, the phy side CA line (incluing command line,
address line and clock line) driver strength. address line and clock line) driver strength.
Default value is PHY_DRV_ODT_40. Default value is PHY_DRV_ODT_40.
- rockchip,phy_ddr3_dq_drv : When dram type is DDR3, this parameter define - rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
the phy side DQ line(incluing DQS/DQ/DM line) the PHY side DQ line (including DQS/DQ/DM line)
driver strength. default value is PHY_DRV_ODT_40. driver strength. Default value is PHY_DRV_ODT_40.
- rockchip,phy_ddr3_odt : When dram type is DDR3, this parameter define the - rockchip,phy_ddr3_odt : When the DRAM type is DDR3, this parameter defines
phy side odt strength, default value is the PHY side ODT strength. Default value is
PHY_DRV_ODT_240. PHY_DRV_ODT_240.
- rockchip,lpddr3_odt_disb_freq : When dram type is LPDDR3, this parameter defined - rockchip,lpddr3_odt_dis_freq : When the DRAM type is LPDDR3, this parameter defines
then odt disable frequency in MHz (Mega Hz), then ODT disable frequency in MHz (Mega Hz).
when ddr frequency less then ddr3_odt_disb_freq, When DDR frequency is less then ddr3_odt_dis_freq,
the odt on dram side and controller side are the ODT on the DRAM side and controller side are
both disabled. both disabled.
- rockchip,lpddr3_drv : When dram type is LPDDR3, this parameter define - rockchip,lpddr3_drv : When the DRAM type is LPDDR3, this parameter defines
the dram side driver stength in ohm, default the DRAM side driver strength in ohms. Default
value is LP3_DS_34ohm. value is LP3_DS_34ohm.
- rockchip,lpddr3_odt : When dram type is LPDDR3, this parameter define - rockchip,lpddr3_odt : When the DRAM type is LPDDR3, this parameter defines
the dram side ODT stength in ohm, default value the DRAM side ODT strength in ohms. Default value
is LP3_ODT_240ohm. is LP3_ODT_240ohm.
- rockchip,phy_lpddr3_ca_drv : When dram type is LPDDR3, this parameter define - rockchip,phy_lpddr3_ca_drv : When the DRAM type is LPDDR3, this parameter defines
the phy side CA line(incluing command line, the PHY side CA line (including command line,
address line and clock line) driver strength. address line and clock line) driver strength.
default value is PHY_DRV_ODT_40. Default value is PHY_DRV_ODT_40.
- rockchip,phy_lpddr3_dq_drv : When dram type is LPDDR3, this parameter define - rockchip,phy_lpddr3_dq_drv : When the DRAM type is LPDDR3, this parameter defines
the phy side DQ line(incluing DQS/DQ/DM line) the PHY side DQ line (including DQS/DQ/DM line)
driver strength. default value is driver strength. Default value is
PHY_DRV_ODT_40. PHY_DRV_ODT_40.
- rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define - rockchip,phy_lpddr3_odt : When dram type is LPDDR3, this parameter define
the phy side odt strength, default value is the phy side odt strength, default value is
PHY_DRV_ODT_240. PHY_DRV_ODT_240.
- rockchip,lpddr4_odt_disb_freq : When dram type is LPDDR4, this parameter - rockchip,lpddr4_odt_dis_freq : When the DRAM type is LPDDR4, this parameter
defined the odt disable frequency in defines the ODT disable frequency in
MHz (Mega Hz), when ddr frequency less then MHz (Mega Hz). When the DDR frequency is less then
ddr3_odt_disb_freq, the odt on dram side and ddr3_odt_dis_freq, the ODT on the DRAM side and
controller side are both disabled. controller side are both disabled.
- rockchip,lpddr4_drv : When dram type is LPDDR4, this parameter define - rockchip,lpddr4_drv : When the DRAM type is LPDDR4, this parameter defines
the dram side driver stength in ohm, default the DRAM side driver strength in ohms. Default
value is LP4_PDDS_60ohm. value is LP4_PDDS_60ohm.
- rockchip,lpddr4_dq_odt : When dram type is LPDDR4, this parameter define - rockchip,lpddr4_dq_odt : When the DRAM type is LPDDR4, this parameter defines
the dram side ODT on dqs/dq line stength in ohm, the DRAM side ODT on DQS/DQ line strength in ohms.
default value is LP4_DQ_ODT_40ohm. Default value is LP4_DQ_ODT_40ohm.
- rockchip,lpddr4_ca_odt : When dram type is LPDDR4, this parameter define - rockchip,lpddr4_ca_odt : When the DRAM type is LPDDR4, this parameter defines
the dram side ODT on ca line stength in ohm, the DRAM side ODT on CA line strength in ohms.
default value is LP4_CA_ODT_40ohm. Default value is LP4_CA_ODT_40ohm.
- rockchip,phy_lpddr4_ca_drv : When dram type is LPDDR4, this parameter define - rockchip,phy_lpddr4_ca_drv : When the DRAM type is LPDDR4, this parameter defines
the phy side CA line(incluing command address the PHY side CA line (including command address
line) driver strength. default value is line) driver strength. Default value is
PHY_DRV_ODT_40. PHY_DRV_ODT_40.
- rockchip,phy_lpddr4_ck_cs_drv : When dram type is LPDDR4, this parameter define - rockchip,phy_lpddr4_ck_cs_drv : When the DRAM type is LPDDR4, this parameter defines
the phy side clock line and cs line driver the PHY side clock line and CS line driver
strength. default value is PHY_DRV_ODT_80. strength. Default value is PHY_DRV_ODT_80.
- rockchip,phy_lpddr4_dq_drv : When dram type is LPDDR4, this parameter define - rockchip,phy_lpddr4_dq_drv : When the DRAM type is LPDDR4, this parameter defines
the phy side DQ line(incluing DQS/DQ/DM line) the PHY side DQ line (including DQS/DQ/DM line)
driver strength. default value is PHY_DRV_ODT_80. driver strength. Default value is PHY_DRV_ODT_80.
- rockchip,phy_lpddr4_odt : When dram type is LPDDR4, this parameter define - rockchip,phy_lpddr4_odt : When the DRAM type is LPDDR4, this parameter defines
the phy side odt strength, default value is the PHY side ODT strength. Default value is
PHY_DRV_ODT_60. PHY_DRV_ODT_60.
Example: Example: