forked from Minki/linux
drm/nv50/disp: allocate display from driver core
EVO channels still handled "manually", this won't be ported here, and will instead be held off until nv50_display/nvd0_display are merged. Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
75f8693f30
commit
2d0aca2119
@ -36,6 +36,8 @@
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#include "nouveau_fence.h"
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#include <core/gpuobj.h>
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#include <core/class.h>
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#include <subdev/timer.h>
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static void nv50_display_bh(unsigned long);
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@ -120,43 +122,6 @@ nv50_display_init(struct drm_device *dev)
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struct nouveau_device *device = nouveau_dev(dev);
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struct nouveau_channel *evo;
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int ret, i;
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u32 val;
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nv_wr32(device, 0x00610184, nv_rd32(device, 0x00614004));
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/*
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* I think the 0x006101XX range is some kind of main control area
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* that enables things.
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*/
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/* CRTC? */
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for (i = 0; i < 2; i++) {
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val = nv_rd32(device, 0x00616100 + (i * 0x800));
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nv_wr32(device, 0x00610190 + (i * 0x10), val);
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val = nv_rd32(device, 0x00616104 + (i * 0x800));
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nv_wr32(device, 0x00610194 + (i * 0x10), val);
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val = nv_rd32(device, 0x00616108 + (i * 0x800));
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nv_wr32(device, 0x00610198 + (i * 0x10), val);
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val = nv_rd32(device, 0x0061610c + (i * 0x800));
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nv_wr32(device, 0x0061019c + (i * 0x10), val);
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}
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/* DAC */
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for (i = 0; i < 3; i++) {
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val = nv_rd32(device, 0x0061a000 + (i * 0x800));
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nv_wr32(device, 0x006101d0 + (i * 0x04), val);
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}
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/* SOR */
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for (i = 0; i < nv50_sor_nr(dev); i++) {
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val = nv_rd32(device, 0x0061c000 + (i * 0x800));
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nv_wr32(device, 0x006101e0 + (i * 0x04), val);
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}
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/* EXT */
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for (i = 0; i < 3; i++) {
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val = nv_rd32(device, 0x0061e000 + (i * 0x800));
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nv_wr32(device, 0x006101f0 + (i * 0x04), val);
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}
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for (i = 0; i < 3; i++) {
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nv_wr32(device, NV50_PDISPLAY_DAC_DPMS_CTRL(i), 0x00550000 |
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@ -164,20 +129,6 @@ nv50_display_init(struct drm_device *dev)
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nv_wr32(device, NV50_PDISPLAY_DAC_CLK_CTRL1(i), 0x00000001);
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}
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/* The precise purpose is unknown, i suspect it has something to do
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* with text mode.
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*/
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if (nv_rd32(device, NV50_PDISPLAY_INTR_1) & 0x100) {
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nv_wr32(device, NV50_PDISPLAY_INTR_1, 0x100);
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nv_wr32(device, 0x006194e8, nv_rd32(device, 0x006194e8) & ~1);
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if (!nv_wait(device, 0x006194e8, 2, 0)) {
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NV_ERROR(drm, "timeout: (0x6194e8 & 2) != 0\n");
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NV_ERROR(drm, "0x6194e8 = 0x%08x\n",
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nv_rd32(device, 0x6194e8));
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return -EBUSY;
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}
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}
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for (i = 0; i < 2; i++) {
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nv_wr32(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i), 0x2000);
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if (!nv_wait(device, NV50_PDISPLAY_CURSOR_CURSOR_CTRL2(i),
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@ -201,22 +152,11 @@ nv50_display_init(struct drm_device *dev)
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}
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}
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nv_wr32(device, NV50_PDISPLAY_PIO_CTRL, 0x00000000);
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nv_mask(device, NV50_PDISPLAY_INTR_0, 0x00000000, 0x00000000);
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nv_wr32(device, NV50_PDISPLAY_INTR_EN_0, 0x00000000);
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nv_mask(device, NV50_PDISPLAY_INTR_1, 0x00000000, 0x00000000);
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nv_wr32(device, NV50_PDISPLAY_INTR_EN_1,
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NV50_PDISPLAY_INTR_EN_1_CLK_UNK10 |
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NV50_PDISPLAY_INTR_EN_1_CLK_UNK20 |
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NV50_PDISPLAY_INTR_EN_1_CLK_UNK40);
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ret = nv50_evo_init(dev);
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if (ret)
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return ret;
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evo = nv50_display(dev)->master;
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nv_wr32(device, NV50_PDISPLAY_OBJECTS, (nv50_display(dev)->ramin->addr >> 8) | 9);
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ret = RING_SPACE(evo, 3);
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if (ret)
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return ret;
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@ -289,14 +229,18 @@ nv50_display_fini(struct drm_device *dev)
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nv_rd32(device, NV50_PDISPLAY_SOR_DPMS_STATE(i)));
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}
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}
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/* disable interrupts. */
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nv_wr32(device, NV50_PDISPLAY_INTR_EN_1, 0x00000000);
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}
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int
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nv50_display_create(struct drm_device *dev)
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{
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static const u16 oclass[] = {
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NVA3_DISP_CLASS,
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NV94_DISP_CLASS,
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NVA0_DISP_CLASS,
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NV84_DISP_CLASS,
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NV50_DISP_CLASS,
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};
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struct nouveau_drm *drm = nouveau_drm(dev);
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struct dcb_table *dcb = &drm->vbios.dcb;
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struct drm_connector *connector, *ct;
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@ -312,6 +256,17 @@ nv50_display_create(struct drm_device *dev)
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nouveau_display(dev)->init = nv50_display_init;
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nouveau_display(dev)->fini = nv50_display_fini;
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/* attempt to allocate a supported evo display class */
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ret = -ENODEV;
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for (i = 0; ret && i < ARRAY_SIZE(oclass); i++) {
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ret = nouveau_object_new(nv_object(drm), NVDRM_DEVICE,
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0xd1500000, oclass[i], NULL, 0,
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&priv->core);
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}
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if (ret)
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return ret;
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/* Create CRTC objects */
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for (i = 0; i < 2; i++) {
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ret = nv50_crtc_create(dev, i);
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@ -44,6 +44,7 @@ struct nv50_display_crtc {
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struct nv50_display {
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struct nouveau_channel *master;
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struct nouveau_object *core;
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struct nouveau_gpuobj *ramin;
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u32 dmao;
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u32 hash;
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@ -245,7 +245,6 @@ nv50_evo_destroy(struct drm_device *dev)
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nv50_evo_channel_del(&disp->crtc[i].sync);
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}
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nv50_evo_channel_del(&disp->master);
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nouveau_gpuobj_ref(NULL, &disp->ramin);
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}
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int
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@ -261,13 +260,7 @@ nv50_evo_create(struct drm_device *dev)
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* use this also as there's no per-channel support on the
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* hardware
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*/
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ret = nouveau_gpuobj_new(drm->device, NULL, 32768, 65536,
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NVOBJ_FLAG_ZERO_ALLOC, &disp->ramin);
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if (ret) {
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NV_ERROR(drm, "Error allocating EVO channel memory: %d\n", ret);
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goto err;
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}
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disp->ramin = nv_gpuobj(disp->core->parent);
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disp->hash = 0x0000;
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disp->dmao = 0x1000;
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