forked from Minki/linux
arm64: add support for the AMU extension v1
The activity monitors extension is an optional extension introduced by the ARMv8.4 CPU architecture. This implements basic support for version 1 of the activity monitors architecture, AMUv1. This support includes: - Extension detection on each CPU (boot, secondary, hotplugged) - Register interface for AMU aarch64 registers Signed-off-by: Ionela Voinescu <ionela.voinescu@arm.com> Reviewed-by: Valentin Schneider <valentin.schneider@arm.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Marc Zyngier <maz@kernel.org> Cc: Suzuki K Poulose <suzuki.poulose@arm.com> Cc: Will Deacon <will@kernel.org> Cc: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
This commit is contained in:
Ionela Voinescu
Catalin Marinas
parent
f8788d86ab
commit
2c9d45b43c
@ -1517,6 +1517,33 @@ config ARM64_PTR_AUTH
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endmenu
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menu "ARMv8.4 architectural features"
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config ARM64_AMU_EXTN
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bool "Enable support for the Activity Monitors Unit CPU extension"
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default y
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help
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The activity monitors extension is an optional extension introduced
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by the ARMv8.4 CPU architecture. This enables support for version 1
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of the activity monitors architecture, AMUv1.
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To enable the use of this extension on CPUs that implement it, say Y.
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Note that for architectural reasons, firmware _must_ implement AMU
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support when running on CPUs that present the activity monitors
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extension. The required support is present in:
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* Version 1.5 and later of the ARM Trusted Firmware
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For kernels that have this configuration enabled but boot with broken
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firmware, you may need to say N here until the firmware is fixed.
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Otherwise you may experience firmware panics or lockups when
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accessing the counter registers. Even if you are not observing these
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symptoms, the values returned by the register reads might not
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correctly reflect reality. Most commonly, the value read will be 0,
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indicating that the counter is not enabled.
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endmenu
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menu "ARMv8.5 architectural features"
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config ARM64_E0PD
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@ -58,7 +58,8 @@
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#define ARM64_WORKAROUND_SPECULATIVE_AT_NVHE 48
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#define ARM64_HAS_E0PD 49
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#define ARM64_HAS_RNG 50
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#define ARM64_HAS_AMU_EXTN 51
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#define ARM64_NCAPS 51
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#define ARM64_NCAPS 52
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#endif /* __ASM_CPUCAPS_H */
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@ -678,6 +678,11 @@ static inline bool cpu_has_hw_af(void)
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ID_AA64MMFR1_HADBS_SHIFT);
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}
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#ifdef CONFIG_ARM64_AMU_EXTN
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/* Check whether the cpu supports the Activity Monitors Unit (AMU) */
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extern bool cpu_has_amu_feat(int cpu);
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#endif
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#endif /* __ASSEMBLY__ */
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#endif
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@ -386,6 +386,42 @@
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#define SYS_TPIDR_EL0 sys_reg(3, 3, 13, 0, 2)
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#define SYS_TPIDRRO_EL0 sys_reg(3, 3, 13, 0, 3)
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/* Definitions for system register interface to AMU for ARMv8.4 onwards */
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#define SYS_AM_EL0(crm, op2) sys_reg(3, 3, 13, (crm), (op2))
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#define SYS_AMCR_EL0 SYS_AM_EL0(2, 0)
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#define SYS_AMCFGR_EL0 SYS_AM_EL0(2, 1)
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#define SYS_AMCGCR_EL0 SYS_AM_EL0(2, 2)
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#define SYS_AMUSERENR_EL0 SYS_AM_EL0(2, 3)
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#define SYS_AMCNTENCLR0_EL0 SYS_AM_EL0(2, 4)
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#define SYS_AMCNTENSET0_EL0 SYS_AM_EL0(2, 5)
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#define SYS_AMCNTENCLR1_EL0 SYS_AM_EL0(3, 0)
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#define SYS_AMCNTENSET1_EL0 SYS_AM_EL0(3, 1)
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/*
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* Group 0 of activity monitors (architected):
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* op0 op1 CRn CRm op2
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* Counter: 11 011 1101 010:n<3> n<2:0>
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* Type: 11 011 1101 011:n<3> n<2:0>
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* n: 0-15
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*
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* Group 1 of activity monitors (auxiliary):
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* op0 op1 CRn CRm op2
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* Counter: 11 011 1101 110:n<3> n<2:0>
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* Type: 11 011 1101 111:n<3> n<2:0>
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* n: 0-15
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*/
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#define SYS_AMEVCNTR0_EL0(n) SYS_AM_EL0(4 + ((n) >> 3), (n) & 7)
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#define SYS_AMEVTYPE0_EL0(n) SYS_AM_EL0(6 + ((n) >> 3), (n) & 7)
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#define SYS_AMEVCNTR1_EL0(n) SYS_AM_EL0(12 + ((n) >> 3), (n) & 7)
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#define SYS_AMEVTYPE1_EL0(n) SYS_AM_EL0(14 + ((n) >> 3), (n) & 7)
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/* AMU v1: Fixed (architecturally defined) activity monitors */
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#define SYS_AMEVCNTR0_CORE_EL0 SYS_AMEVCNTR0_EL0(0)
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#define SYS_AMEVCNTR0_CONST_EL0 SYS_AMEVCNTR0_EL0(1)
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#define SYS_AMEVCNTR0_INST_RET_EL0 SYS_AMEVCNTR0_EL0(2)
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#define SYS_AMEVCNTR0_MEM_STALL SYS_AMEVCNTR0_EL0(3)
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#define SYS_CNTFRQ_EL0 sys_reg(3, 3, 14, 0, 0)
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#define SYS_CNTP_TVAL_EL0 sys_reg(3, 3, 14, 2, 0)
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@ -598,6 +634,7 @@
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#define ID_AA64PFR0_CSV3_SHIFT 60
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#define ID_AA64PFR0_CSV2_SHIFT 56
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#define ID_AA64PFR0_DIT_SHIFT 48
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#define ID_AA64PFR0_AMU_SHIFT 44
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#define ID_AA64PFR0_SVE_SHIFT 32
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#define ID_AA64PFR0_RAS_SHIFT 28
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#define ID_AA64PFR0_GIC_SHIFT 24
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@ -608,6 +645,7 @@
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#define ID_AA64PFR0_EL1_SHIFT 4
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#define ID_AA64PFR0_EL0_SHIFT 0
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#define ID_AA64PFR0_AMU 0x1
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#define ID_AA64PFR0_SVE 0x1
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#define ID_AA64PFR0_RAS_V1 0x1
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#define ID_AA64PFR0_FP_NI 0xf
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@ -163,6 +163,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = {
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV3_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_CSV2_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_DIT_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_AMU_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_SVE),
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FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_SVE_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64PFR0_RAS_SHIFT, 4, 0),
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@ -1222,6 +1223,53 @@ static bool has_hw_dbm(const struct arm64_cpu_capabilities *cap,
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#endif
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#ifdef CONFIG_ARM64_AMU_EXTN
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/*
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* The "amu_cpus" cpumask only signals that the CPU implementation for the
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* flagged CPUs supports the Activity Monitors Unit (AMU) but does not provide
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* information regarding all the events that it supports. When a CPU bit is
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* set in the cpumask, the user of this feature can only rely on the presence
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* of the 4 fixed counters for that CPU. But this does not guarantee that the
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* counters are enabled or access to these counters is enabled by code
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* executed at higher exception levels (firmware).
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*/
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static struct cpumask amu_cpus __read_mostly;
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bool cpu_has_amu_feat(int cpu)
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{
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return cpumask_test_cpu(cpu, &amu_cpus);
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}
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static void cpu_amu_enable(struct arm64_cpu_capabilities const *cap)
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{
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if (has_cpuid_feature(cap, SCOPE_LOCAL_CPU)) {
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pr_info("detected CPU%d: Activity Monitors Unit (AMU)\n",
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smp_processor_id());
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cpumask_set_cpu(smp_processor_id(), &amu_cpus);
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}
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}
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static bool has_amu(const struct arm64_cpu_capabilities *cap,
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int __unused)
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{
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/*
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* The AMU extension is a non-conflicting feature: the kernel can
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* safely run a mix of CPUs with and without support for the
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* activity monitors extension. Therefore, unconditionally enable
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* the capability to allow any late CPU to use the feature.
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*
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* With this feature unconditionally enabled, the cpu_enable
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* function will be called for all CPUs that match the criteria,
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* including secondary and hotplugged, marking this feature as
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* present on that respective CPU. The enable function will also
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* print a detection message.
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*/
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return true;
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}
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#endif
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#ifdef CONFIG_ARM64_VHE
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static bool runs_at_el2(const struct arm64_cpu_capabilities *entry, int __unused)
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{
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@ -1499,6 +1547,24 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.cpu_enable = cpu_clear_disr,
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},
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#endif /* CONFIG_ARM64_RAS_EXTN */
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#ifdef CONFIG_ARM64_AMU_EXTN
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{
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/*
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* The feature is enabled by default if CONFIG_ARM64_AMU_EXTN=y.
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* Therefore, don't provide .desc as we don't want the detection
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* message to be shown until at least one CPU is detected to
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* support the feature.
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*/
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.capability = ARM64_HAS_AMU_EXTN,
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.type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE,
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.matches = has_amu,
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.sys_reg = SYS_ID_AA64PFR0_EL1,
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.sign = FTR_UNSIGNED,
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.field_pos = ID_AA64PFR0_AMU_SHIFT,
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.min_field_value = ID_AA64PFR0_AMU,
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.cpu_enable = cpu_amu_enable,
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},
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#endif /* CONFIG_ARM64_AMU_EXTN */
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{
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.desc = "Data cache clean to the PoU not required for I/D coherence",
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.capability = ARM64_HAS_CACHE_IDC,
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