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drm/amd/display: add n_vid_mul and half pix_rate for odm

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Dp needs half container rate to properly support odm

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Nikola Cornij <Nikola.Cornij@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Dmytro Laktyushkin 2019-01-14 15:19:44 -05:00 committed by Alex Deucher
parent fb55546ea4
commit 2c850b7b9e
3 changed files with 8 additions and 5 deletions
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4
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
View File

@ -1032,8 +1032,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
struct dc_link *link = stream->link;
/* only 3 items below are used by unblank */
params.pixel_clk_khz =
pipe_ctx->stream->timing.pix_clk_100hz / 10;
params.pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10;
params.link_settings.link_rate = link_settings->link_rate;
if (dc_is_dp_signal(pipe_ctx->stream->signal))
@ -1043,6 +1042,7 @@ void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
link->dc->hwss.edp_backlight_control(link, true);
}
}
void dce110_blank_stream(struct pipe_ctx *pipe_ctx)
{
struct dc_stream_state *stream = pipe_ctx->stream;

7
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.c
View File

@ -390,7 +390,7 @@ void optc1_program_timing(
h_div_2 = optc1_is_two_pixels_per_containter(&patched_crtc_timing);
REG_UPDATE(OTG_H_TIMING_CNTL,
OTG_H_TIMING_DIV_BY2, h_div_2);
OTG_H_TIMING_DIV_BY2, h_div_2 || optc1->comb_opp_id != 0xf);
}
@ -1531,10 +1531,13 @@ void dcn10_timing_generator_init(struct optc *optc1)
optc1->min_v_blank_interlace = 5;
optc1->min_h_sync_width = 8;
optc1->min_v_sync_width = 1;
optc1->comb_opp_id = 0xf;
}
bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing)
{
return timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
return two_pix;
}

2
drivers/gpu/drm/amd/display/dc/dcn10/dcn10_optc.h
View File

@ -435,7 +435,7 @@ struct optc {
const struct dcn_optc_shift *tg_shift;
const struct dcn_optc_mask *tg_mask;
enum controller_id controller_id;
int comb_opp_id;
uint32_t max_h_total;
uint32_t max_v_total;