forked from Minki/linux
net/mlx4_en: Use PTYS register to query ethtool settings
- If dev cap MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL is ON, query PTYS register to fill ethtool settings. else use default values. - Use autoneg port cap and dev backplane autoneg cap to reprort autoneg interface capbilities. - Fix typo in mlx4_en_port_state struct field (transciver to transceiver). Signed-off-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: Amir Vadai <amirv@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Saeed Mahameed
David S. Miller
parent
dcf972a334
commit
2c76267943
@ -375,7 +375,277 @@ static void mlx4_en_get_strings(struct net_device *dev,
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}
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}
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static int mlx4_en_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
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static u32 mlx4_en_autoneg_get(struct net_device *dev)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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struct mlx4_en_dev *mdev = priv->mdev;
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u32 autoneg = AUTONEG_DISABLE;
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if ((mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP) &&
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(priv->port_state.flags & MLX4_EN_PORT_ANE))
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autoneg = AUTONEG_ENABLE;
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return autoneg;
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}
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static u32 ptys_get_supported_port(struct mlx4_ptys_reg *ptys_reg)
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{
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u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
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if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
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| MLX4_PROT_MASK(MLX4_1000BASE_T)
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| MLX4_PROT_MASK(MLX4_100BASE_TX))) {
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return SUPPORTED_TP;
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}
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if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
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| MLX4_PROT_MASK(MLX4_10GBASE_SR)
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| MLX4_PROT_MASK(MLX4_56GBASE_SR4)
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| MLX4_PROT_MASK(MLX4_40GBASE_CR4)
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| MLX4_PROT_MASK(MLX4_40GBASE_SR4)
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| MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
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return SUPPORTED_FIBRE;
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}
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if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
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| MLX4_PROT_MASK(MLX4_40GBASE_KR4)
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| MLX4_PROT_MASK(MLX4_20GBASE_KR2)
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| MLX4_PROT_MASK(MLX4_10GBASE_KR)
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| MLX4_PROT_MASK(MLX4_10GBASE_KX4)
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| MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
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return SUPPORTED_Backplane;
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}
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return 0;
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}
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static u32 ptys_get_active_port(struct mlx4_ptys_reg *ptys_reg)
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{
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u32 eth_proto = be32_to_cpu(ptys_reg->eth_proto_oper);
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if (!eth_proto) /* link down */
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eth_proto = be32_to_cpu(ptys_reg->eth_proto_cap);
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if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_T)
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| MLX4_PROT_MASK(MLX4_1000BASE_T)
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| MLX4_PROT_MASK(MLX4_100BASE_TX))) {
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return PORT_TP;
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}
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if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_SR)
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| MLX4_PROT_MASK(MLX4_56GBASE_SR4)
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| MLX4_PROT_MASK(MLX4_40GBASE_SR4)
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| MLX4_PROT_MASK(MLX4_1000BASE_CX_SGMII))) {
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return PORT_FIBRE;
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}
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if (eth_proto & (MLX4_PROT_MASK(MLX4_10GBASE_CR)
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| MLX4_PROT_MASK(MLX4_56GBASE_CR4)
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| MLX4_PROT_MASK(MLX4_40GBASE_CR4))) {
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return PORT_DA;
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}
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if (eth_proto & (MLX4_PROT_MASK(MLX4_56GBASE_KR4)
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| MLX4_PROT_MASK(MLX4_40GBASE_KR4)
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| MLX4_PROT_MASK(MLX4_20GBASE_KR2)
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| MLX4_PROT_MASK(MLX4_10GBASE_KR)
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| MLX4_PROT_MASK(MLX4_10GBASE_KX4)
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| MLX4_PROT_MASK(MLX4_1000BASE_KX))) {
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return PORT_NONE;
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}
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return PORT_OTHER;
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}
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#define MLX4_LINK_MODES_SZ \
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(FIELD_SIZEOF(struct mlx4_ptys_reg, eth_proto_cap) * 8)
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enum ethtool_report {
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SUPPORTED = 0,
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ADVERTISED = 1,
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SPEED = 2
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};
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/* Translates mlx4 link mode to equivalent ethtool Link modes/speed */
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static u32 ptys2ethtool_map[MLX4_LINK_MODES_SZ][3] = {
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[MLX4_100BASE_TX] = {
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SUPPORTED_100baseT_Full,
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ADVERTISED_100baseT_Full,
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SPEED_100
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},
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[MLX4_1000BASE_T] = {
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SUPPORTED_1000baseT_Full,
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ADVERTISED_1000baseT_Full,
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SPEED_1000
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},
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[MLX4_1000BASE_CX_SGMII] = {
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SUPPORTED_1000baseKX_Full,
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ADVERTISED_1000baseKX_Full,
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SPEED_1000
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},
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[MLX4_1000BASE_KX] = {
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SUPPORTED_1000baseKX_Full,
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ADVERTISED_1000baseKX_Full,
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SPEED_1000
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},
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[MLX4_10GBASE_T] = {
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SUPPORTED_10000baseT_Full,
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ADVERTISED_10000baseT_Full,
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SPEED_10000
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},
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[MLX4_10GBASE_CX4] = {
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SUPPORTED_10000baseKX4_Full,
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ADVERTISED_10000baseKX4_Full,
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SPEED_10000
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},
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[MLX4_10GBASE_KX4] = {
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SUPPORTED_10000baseKX4_Full,
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ADVERTISED_10000baseKX4_Full,
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SPEED_10000
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},
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[MLX4_10GBASE_KR] = {
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SUPPORTED_10000baseKR_Full,
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ADVERTISED_10000baseKR_Full,
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SPEED_10000
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},
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[MLX4_10GBASE_CR] = {
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SUPPORTED_10000baseKR_Full,
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ADVERTISED_10000baseKR_Full,
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SPEED_10000
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},
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[MLX4_10GBASE_SR] = {
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SUPPORTED_10000baseKR_Full,
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ADVERTISED_10000baseKR_Full,
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SPEED_10000
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},
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[MLX4_20GBASE_KR2] = {
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SUPPORTED_20000baseMLD2_Full | SUPPORTED_20000baseKR2_Full,
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ADVERTISED_20000baseMLD2_Full | ADVERTISED_20000baseKR2_Full,
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SPEED_20000
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},
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[MLX4_40GBASE_CR4] = {
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SUPPORTED_40000baseCR4_Full,
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ADVERTISED_40000baseCR4_Full,
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SPEED_40000
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},
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[MLX4_40GBASE_KR4] = {
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SUPPORTED_40000baseKR4_Full,
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ADVERTISED_40000baseKR4_Full,
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SPEED_40000
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},
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[MLX4_40GBASE_SR4] = {
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SUPPORTED_40000baseSR4_Full,
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ADVERTISED_40000baseSR4_Full,
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SPEED_40000
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},
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[MLX4_56GBASE_KR4] = {
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SUPPORTED_56000baseKR4_Full,
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ADVERTISED_56000baseKR4_Full,
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SPEED_56000
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},
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[MLX4_56GBASE_CR4] = {
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SUPPORTED_56000baseCR4_Full,
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ADVERTISED_56000baseCR4_Full,
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SPEED_56000
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},
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[MLX4_56GBASE_SR4] = {
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SUPPORTED_56000baseSR4_Full,
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ADVERTISED_56000baseSR4_Full,
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SPEED_56000
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},
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};
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static u32 ptys2ethtool_link_modes(u32 eth_proto, enum ethtool_report report)
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{
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int i;
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u32 link_modes = 0;
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for (i = 0; i < MLX4_LINK_MODES_SZ; i++) {
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if (eth_proto & MLX4_PROT_MASK(i))
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link_modes |= ptys2ethtool_map[i][report];
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}
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return link_modes;
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}
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static int ethtool_get_ptys_settings(struct net_device *dev,
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struct ethtool_cmd *cmd)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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struct mlx4_ptys_reg ptys_reg;
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u32 eth_proto;
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int ret;
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memset(&ptys_reg, 0, sizeof(ptys_reg));
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ptys_reg.local_port = priv->port;
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ptys_reg.proto_mask = MLX4_PTYS_EN;
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ret = mlx4_ACCESS_PTYS_REG(priv->mdev->dev,
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MLX4_ACCESS_REG_QUERY, &ptys_reg);
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if (ret) {
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en_warn(priv, "Failed to run mlx4_ACCESS_PTYS_REG status(%x)",
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ret);
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return ret;
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}
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en_dbg(DRV, priv, "ptys_reg.proto_mask %x\n",
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ptys_reg.proto_mask);
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en_dbg(DRV, priv, "ptys_reg.eth_proto_cap %x\n",
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be32_to_cpu(ptys_reg.eth_proto_cap));
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en_dbg(DRV, priv, "ptys_reg.eth_proto_admin %x\n",
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be32_to_cpu(ptys_reg.eth_proto_admin));
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en_dbg(DRV, priv, "ptys_reg.eth_proto_oper %x\n",
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be32_to_cpu(ptys_reg.eth_proto_oper));
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en_dbg(DRV, priv, "ptys_reg.eth_proto_lp_adv %x\n",
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be32_to_cpu(ptys_reg.eth_proto_lp_adv));
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cmd->supported = 0;
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cmd->advertising = 0;
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cmd->supported |= ptys_get_supported_port(&ptys_reg);
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eth_proto = be32_to_cpu(ptys_reg.eth_proto_cap);
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cmd->supported |= ptys2ethtool_link_modes(eth_proto, SUPPORTED);
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eth_proto = be32_to_cpu(ptys_reg.eth_proto_admin);
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cmd->advertising |= ptys2ethtool_link_modes(eth_proto, ADVERTISED);
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cmd->supported |= SUPPORTED_Pause | SUPPORTED_Asym_Pause;
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cmd->advertising |= (priv->prof->tx_pause) ? ADVERTISED_Pause : 0;
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cmd->advertising |= (priv->prof->tx_pause ^ priv->prof->rx_pause) ?
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ADVERTISED_Asym_Pause : 0;
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cmd->port = ptys_get_active_port(&ptys_reg);
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cmd->transceiver = (SUPPORTED_TP & cmd->supported) ?
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XCVR_EXTERNAL : XCVR_INTERNAL;
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if (mlx4_en_autoneg_get(dev)) {
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cmd->supported |= SUPPORTED_Autoneg;
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cmd->advertising |= ADVERTISED_Autoneg;
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}
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cmd->autoneg = (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
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AUTONEG_ENABLE : AUTONEG_DISABLE;
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eth_proto = be32_to_cpu(ptys_reg.eth_proto_lp_adv);
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cmd->lp_advertising = ptys2ethtool_link_modes(eth_proto, ADVERTISED);
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cmd->lp_advertising |= (priv->port_state.flags & MLX4_EN_PORT_ANC) ?
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ADVERTISED_Autoneg : 0;
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cmd->phy_address = 0;
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cmd->mdio_support = 0;
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cmd->maxtxpkt = 0;
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cmd->maxrxpkt = 0;
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cmd->eth_tp_mdix = ETH_TP_MDI_INVALID;
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cmd->eth_tp_mdix_ctrl = ETH_TP_MDI_AUTO;
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return ret;
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}
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static void ethtool_get_default_settings(struct net_device *dev,
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struct ethtool_cmd *cmd)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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int trans_type;
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@ -383,18 +653,7 @@ static int mlx4_en_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
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cmd->autoneg = AUTONEG_DISABLE;
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cmd->supported = SUPPORTED_10000baseT_Full;
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cmd->advertising = ADVERTISED_10000baseT_Full;
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if (mlx4_en_QUERY_PORT(priv->mdev, priv->port))
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return -ENOMEM;
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trans_type = priv->port_state.transciver;
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if (netif_carrier_ok(dev)) {
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ethtool_cmd_speed_set(cmd, priv->port_state.link_speed);
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cmd->duplex = DUPLEX_FULL;
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} else {
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ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
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cmd->duplex = DUPLEX_UNKNOWN;
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}
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trans_type = priv->port_state.transceiver;
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if (trans_type > 0 && trans_type <= 0xC) {
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cmd->port = PORT_FIBRE;
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@ -410,6 +669,32 @@ static int mlx4_en_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
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cmd->port = -1;
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cmd->transceiver = -1;
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}
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}
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static int mlx4_en_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
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{
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struct mlx4_en_priv *priv = netdev_priv(dev);
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int ret = -EINVAL;
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if (mlx4_en_QUERY_PORT(priv->mdev, priv->port))
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return -ENOMEM;
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en_dbg(DRV, priv, "query port state.flags ANC(%x) ANE(%x)\n",
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priv->port_state.flags & MLX4_EN_PORT_ANC,
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priv->port_state.flags & MLX4_EN_PORT_ANE);
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if (priv->mdev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL)
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ret = ethtool_get_ptys_settings(dev, cmd);
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if (ret) /* ETH PROT CRTL is not supported or PTYS CMD failed */
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ethtool_get_default_settings(dev, cmd);
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if (netif_carrier_ok(dev)) {
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ethtool_cmd_speed_set(cmd, priv->port_state.link_speed);
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cmd->duplex = DUPLEX_FULL;
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} else {
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ethtool_cmd_speed_set(cmd, SPEED_UNKNOWN);
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cmd->duplex = DUPLEX_UNKNOWN;
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}
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return 0;
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}
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@ -114,7 +114,14 @@ int mlx4_en_QUERY_PORT(struct mlx4_en_dev *mdev, u8 port)
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state->link_speed = -1;
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break;
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}
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state->transciver = qport_context->transceiver;
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state->transceiver = qport_context->transceiver;
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state->flags = 0; /* Reset and recalculate the port flags */
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state->flags |= (qport_context->link_up & MLX4_EN_ANC_MASK) ?
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MLX4_EN_PORT_ANC : 0;
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state->flags |= (qport_context->autoneg & MLX4_EN_AUTONEG_MASK) ?
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MLX4_EN_PORT_ANE : 0;
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out:
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mlx4_free_cmd_mailbox(mdev->dev, mailbox);
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@ -53,6 +53,28 @@ enum {
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MLX4_MCAST_ENABLE = 2,
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};
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enum mlx4_link_mode {
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MLX4_1000BASE_CX_SGMII = 0,
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MLX4_1000BASE_KX = 1,
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MLX4_10GBASE_CX4 = 2,
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MLX4_10GBASE_KX4 = 3,
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MLX4_10GBASE_KR = 4,
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MLX4_20GBASE_KR2 = 5,
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MLX4_40GBASE_CR4 = 6,
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MLX4_40GBASE_KR4 = 7,
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MLX4_56GBASE_KR4 = 8,
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MLX4_10GBASE_CR = 12,
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MLX4_10GBASE_SR = 13,
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MLX4_40GBASE_SR4 = 15,
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MLX4_56GBASE_CR4 = 17,
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MLX4_56GBASE_SR4 = 18,
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MLX4_100BASE_TX = 24,
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MLX4_1000BASE_T = 25,
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MLX4_10GBASE_T = 26,
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};
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#define MLX4_PROT_MASK(link_mode) (1<<link_mode)
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enum {
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MLX4_EN_100M_SPEED = 0x04,
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MLX4_EN_10G_SPEED_XAUI = 0x00,
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@ -67,7 +89,9 @@ enum {
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struct mlx4_en_query_port_context {
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u8 link_up;
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#define MLX4_EN_LINK_UP_MASK 0x80
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u8 reserved;
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#define MLX4_EN_ANC_MASK 0x40
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u8 autoneg;
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#define MLX4_EN_AUTONEG_MASK 0x80
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__be16 mtu;
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u8 reserved2;
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u8 link_speed;
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@ -421,10 +421,16 @@ struct mlx4_en_rss_map {
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enum mlx4_qp_state indir_state;
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};
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enum mlx4_en_port_flag {
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MLX4_EN_PORT_ANC = 1<<0, /* Auto-negotiation complete */
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MLX4_EN_PORT_ANE = 1<<1, /* Auto-negotiation enabled */
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};
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struct mlx4_en_port_state {
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int link_state;
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int link_speed;
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int transciver;
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int transceiver;
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u32 flags;
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};
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struct mlx4_en_pkt_stats {
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