Merge tag 'at91-cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91 into next/cleanup
Pull "Second batch of cleanup/SoC for 3.19" from Nicolas Ferre: - fixes following legacy board removal - removal of an unused config option CONFIG_MACH_SAMA5_DT - move of some header files out of include/mach directory * tag 'at91-cleanup2' of git://git.kernel.org/pub/scm/linux/kernel/git/nferre/linux-at91: ARM: at91: move sdramc/ddrsdr header to include/soc/at91 ARM: at91: remove CONFIG_MACH_SAMA5_DT ARM: at91: remove unused CONFIG_ARCH_AT91SAM9G45 option ARM: at91: remove useless init_time for DT-only SoCs ARM: at91: fix build breakage due to legacy board removals Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
63
include/soc/at91/at91rm9200_sdramc.h
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63
include/soc/at91/at91rm9200_sdramc.h
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/*
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* arch/arm/mach-at91/include/mach/at91rm9200_sdramc.h
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*
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* Copyright (C) 2005 Ivan Kokshaysky
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* Copyright (C) SAN People
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*
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* Memory Controllers (SDRAMC only) - System peripherals registers.
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* Based on AT91RM9200 datasheet revision E.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91RM9200_SDRAMC_H
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#define AT91RM9200_SDRAMC_H
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/* SDRAM Controller registers */
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#define AT91RM9200_SDRAMC_MR 0x90 /* Mode Register */
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#define AT91RM9200_SDRAMC_MODE (0xf << 0) /* Command Mode */
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#define AT91RM9200_SDRAMC_MODE_NORMAL (0 << 0)
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#define AT91RM9200_SDRAMC_MODE_NOP (1 << 0)
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#define AT91RM9200_SDRAMC_MODE_PRECHARGE (2 << 0)
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#define AT91RM9200_SDRAMC_MODE_LMR (3 << 0)
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#define AT91RM9200_SDRAMC_MODE_REFRESH (4 << 0)
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#define AT91RM9200_SDRAMC_DBW (1 << 4) /* Data Bus Width */
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#define AT91RM9200_SDRAMC_DBW_32 (0 << 4)
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#define AT91RM9200_SDRAMC_DBW_16 (1 << 4)
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#define AT91RM9200_SDRAMC_TR 0x94 /* Refresh Timer Register */
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#define AT91RM9200_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
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#define AT91RM9200_SDRAMC_CR 0x98 /* Configuration Register */
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#define AT91RM9200_SDRAMC_NC (3 << 0) /* Number of Column Bits */
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#define AT91RM9200_SDRAMC_NC_8 (0 << 0)
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#define AT91RM9200_SDRAMC_NC_9 (1 << 0)
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#define AT91RM9200_SDRAMC_NC_10 (2 << 0)
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#define AT91RM9200_SDRAMC_NC_11 (3 << 0)
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#define AT91RM9200_SDRAMC_NR (3 << 2) /* Number of Row Bits */
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#define AT91RM9200_SDRAMC_NR_11 (0 << 2)
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#define AT91RM9200_SDRAMC_NR_12 (1 << 2)
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#define AT91RM9200_SDRAMC_NR_13 (2 << 2)
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#define AT91RM9200_SDRAMC_NB (1 << 4) /* Number of Banks */
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#define AT91RM9200_SDRAMC_NB_2 (0 << 4)
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#define AT91RM9200_SDRAMC_NB_4 (1 << 4)
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#define AT91RM9200_SDRAMC_CAS (3 << 5) /* CAS Latency */
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#define AT91RM9200_SDRAMC_CAS_2 (2 << 5)
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#define AT91RM9200_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
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#define AT91RM9200_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
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#define AT91RM9200_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
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#define AT91RM9200_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
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#define AT91RM9200_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
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#define AT91RM9200_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
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#define AT91RM9200_SDRAMC_SRR 0x9c /* Self Refresh Register */
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#define AT91RM9200_SDRAMC_LPR 0xa0 /* Low Power Register */
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#define AT91RM9200_SDRAMC_IER 0xa4 /* Interrupt Enable Register */
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#define AT91RM9200_SDRAMC_IDR 0xa8 /* Interrupt Disable Register */
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#define AT91RM9200_SDRAMC_IMR 0xac /* Interrupt Mask Register */
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#define AT91RM9200_SDRAMC_ISR 0xb0 /* Interrupt Status Register */
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#endif
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124
include/soc/at91/at91sam9_ddrsdr.h
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124
include/soc/at91/at91sam9_ddrsdr.h
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/*
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* Header file for the Atmel DDR/SDR SDRAM Controller
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*
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* Copyright (C) 2010 Atmel Corporation
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* Nicolas Ferre <nicolas.ferre@atmel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91SAM9_DDRSDR_H
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#define AT91SAM9_DDRSDR_H
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#define AT91_DDRSDRC_MR 0x00 /* Mode Register */
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#define AT91_DDRSDRC_MODE (0x7 << 0) /* Command Mode */
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#define AT91_DDRSDRC_MODE_NORMAL 0
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#define AT91_DDRSDRC_MODE_NOP 1
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#define AT91_DDRSDRC_MODE_PRECHARGE 2
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#define AT91_DDRSDRC_MODE_LMR 3
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#define AT91_DDRSDRC_MODE_REFRESH 4
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#define AT91_DDRSDRC_MODE_EXT_LMR 5
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#define AT91_DDRSDRC_MODE_DEEP 6
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#define AT91_DDRSDRC_RTR 0x04 /* Refresh Timer Register */
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#define AT91_DDRSDRC_COUNT (0xfff << 0) /* Refresh Timer Counter */
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#define AT91_DDRSDRC_CR 0x08 /* Configuration Register */
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#define AT91_DDRSDRC_NC (3 << 0) /* Number of Column Bits */
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#define AT91_DDRSDRC_NC_SDR8 (0 << 0)
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#define AT91_DDRSDRC_NC_SDR9 (1 << 0)
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#define AT91_DDRSDRC_NC_SDR10 (2 << 0)
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#define AT91_DDRSDRC_NC_SDR11 (3 << 0)
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#define AT91_DDRSDRC_NC_DDR9 (0 << 0)
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#define AT91_DDRSDRC_NC_DDR10 (1 << 0)
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#define AT91_DDRSDRC_NC_DDR11 (2 << 0)
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#define AT91_DDRSDRC_NC_DDR12 (3 << 0)
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#define AT91_DDRSDRC_NR (3 << 2) /* Number of Row Bits */
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#define AT91_DDRSDRC_NR_11 (0 << 2)
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#define AT91_DDRSDRC_NR_12 (1 << 2)
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#define AT91_DDRSDRC_NR_13 (2 << 2)
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#define AT91_DDRSDRC_NR_14 (3 << 2)
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#define AT91_DDRSDRC_CAS (7 << 4) /* CAS Latency */
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#define AT91_DDRSDRC_CAS_2 (2 << 4)
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#define AT91_DDRSDRC_CAS_3 (3 << 4)
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#define AT91_DDRSDRC_CAS_25 (6 << 4)
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#define AT91_DDRSDRC_RST_DLL (1 << 7) /* Reset DLL */
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#define AT91_DDRSDRC_DICDS (1 << 8) /* Output impedance control */
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#define AT91_DDRSDRC_DIS_DLL (1 << 9) /* Disable DLL [SAM9 Only] */
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#define AT91_DDRSDRC_OCD (1 << 12) /* Off-Chip Driver [SAM9 Only] */
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#define AT91_DDRSDRC_DQMS (1 << 16) /* Mask Data is Shared [SAM9 Only] */
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#define AT91_DDRSDRC_ACTBST (1 << 18) /* Active Bank X to Burst Stop Read Access Bank Y [SAM9 Only] */
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#define AT91_DDRSDRC_T0PR 0x0C /* Timing 0 Register */
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#define AT91_DDRSDRC_TRAS (0xf << 0) /* Active to Precharge delay */
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#define AT91_DDRSDRC_TRCD (0xf << 4) /* Row to Column delay */
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#define AT91_DDRSDRC_TWR (0xf << 8) /* Write recovery delay */
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#define AT91_DDRSDRC_TRC (0xf << 12) /* Row cycle delay */
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#define AT91_DDRSDRC_TRP (0xf << 16) /* Row precharge delay */
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#define AT91_DDRSDRC_TRRD (0xf << 20) /* Active BankA to BankB */
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#define AT91_DDRSDRC_TWTR (0x7 << 24) /* Internal Write to Read delay */
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#define AT91_DDRSDRC_RED_WRRD (0x1 << 27) /* Reduce Write to Read Delay [SAM9 Only] */
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#define AT91_DDRSDRC_TMRD (0xf << 28) /* Load mode to active/refresh delay */
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#define AT91_DDRSDRC_T1PR 0x10 /* Timing 1 Register */
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#define AT91_DDRSDRC_TRFC (0x1f << 0) /* Row Cycle Delay */
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#define AT91_DDRSDRC_TXSNR (0xff << 8) /* Exit self-refresh to non-read */
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#define AT91_DDRSDRC_TXSRD (0xff << 16) /* Exit self-refresh to read */
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#define AT91_DDRSDRC_TXP (0xf << 24) /* Exit power-down delay */
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#define AT91_DDRSDRC_T2PR 0x14 /* Timing 2 Register [SAM9 Only] */
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#define AT91_DDRSDRC_TXARD (0xf << 0) /* Exit active power down delay to read command in mode "Fast Exit" */
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#define AT91_DDRSDRC_TXARDS (0xf << 4) /* Exit active power down delay to read command in mode "Slow Exit" */
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#define AT91_DDRSDRC_TRPA (0xf << 8) /* Row Precharge All delay */
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#define AT91_DDRSDRC_TRTP (0x7 << 12) /* Read to Precharge delay */
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#define AT91_DDRSDRC_LPR 0x1C /* Low Power Register */
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#define AT91_DDRSDRC_LPCB (3 << 0) /* Low-power Configurations */
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#define AT91_DDRSDRC_LPCB_DISABLE 0
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#define AT91_DDRSDRC_LPCB_SELF_REFRESH 1
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#define AT91_DDRSDRC_LPCB_POWER_DOWN 2
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#define AT91_DDRSDRC_LPCB_DEEP_POWER_DOWN 3
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#define AT91_DDRSDRC_CLKFR (1 << 2) /* Clock Frozen */
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#define AT91_DDRSDRC_PASR (7 << 4) /* Partial Array Self Refresh */
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#define AT91_DDRSDRC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
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#define AT91_DDRSDRC_DS (3 << 10) /* Drive Strength */
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#define AT91_DDRSDRC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
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#define AT91_DDRSDRC_TIMEOUT_0_CLK_CYCLES (0 << 12)
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#define AT91_DDRSDRC_TIMEOUT_64_CLK_CYCLES (1 << 12)
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#define AT91_DDRSDRC_TIMEOUT_128_CLK_CYCLES (2 << 12)
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#define AT91_DDRSDRC_APDE (1 << 16) /* Active power down exit time */
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#define AT91_DDRSDRC_UPD_MR (3 << 20) /* Update load mode register and extended mode register */
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#define AT91_DDRSDRC_MDR 0x20 /* Memory Device Register */
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#define AT91_DDRSDRC_MD (3 << 0) /* Memory Device Type */
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#define AT91_DDRSDRC_MD_SDR 0
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#define AT91_DDRSDRC_MD_LOW_POWER_SDR 1
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#define AT91_DDRSDRC_MD_LOW_POWER_DDR 3
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#define AT91_DDRSDRC_MD_DDR2 6 /* [SAM9 Only] */
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#define AT91_DDRSDRC_DBW (1 << 4) /* Data Bus Width */
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#define AT91_DDRSDRC_DBW_32BITS (0 << 4)
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#define AT91_DDRSDRC_DBW_16BITS (1 << 4)
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#define AT91_DDRSDRC_DLL 0x24 /* DLL Information Register */
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#define AT91_DDRSDRC_MDINC (1 << 0) /* Master Delay increment */
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#define AT91_DDRSDRC_MDDEC (1 << 1) /* Master Delay decrement */
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#define AT91_DDRSDRC_MDOVF (1 << 2) /* Master Delay Overflow */
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#define AT91_DDRSDRC_MDVAL (0xff << 8) /* Master Delay value */
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#define AT91_DDRSDRC_HS 0x2C /* High Speed Register [SAM9 Only] */
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#define AT91_DDRSDRC_DIS_ATCP_RD (1 << 2) /* Anticip read access is disabled */
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#define AT91_DDRSDRC_DELAY(n) (0x30 + (0x4 * (n))) /* Delay I/O Register n */
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#define AT91_DDRSDRC_WPMR 0xE4 /* Write Protect Mode Register [SAM9 Only] */
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#define AT91_DDRSDRC_WP (1 << 0) /* Write protect enable */
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#define AT91_DDRSDRC_WPKEY (0xffffff << 8) /* Write protect key */
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#define AT91_DDRSDRC_KEY (0x444452 << 8) /* Write protect key = "DDR" */
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#define AT91_DDRSDRC_WPSR 0xE8 /* Write Protect Status Register [SAM9 Only] */
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#define AT91_DDRSDRC_WPVS (1 << 0) /* Write protect violation status */
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#define AT91_DDRSDRC_WPVSRC (0xffff << 8) /* Write protect violation source */
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#endif
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85
include/soc/at91/at91sam9_sdramc.h
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85
include/soc/at91/at91sam9_sdramc.h
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@@ -0,0 +1,85 @@
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/*
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* arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
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*
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* Copyright (C) 2007 Andrew Victor
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* Copyright (C) 2007 Atmel Corporation.
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*
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* SDRAM Controllers (SDRAMC) - System peripherals registers.
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* Based on AT91SAM9261 datasheet revision D.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef AT91SAM9_SDRAMC_H
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#define AT91SAM9_SDRAMC_H
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/* SDRAM Controller (SDRAMC) registers */
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#define AT91_SDRAMC_MR 0x00 /* SDRAM Controller Mode Register */
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#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
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#define AT91_SDRAMC_MODE_NORMAL 0
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#define AT91_SDRAMC_MODE_NOP 1
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#define AT91_SDRAMC_MODE_PRECHARGE 2
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#define AT91_SDRAMC_MODE_LMR 3
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#define AT91_SDRAMC_MODE_REFRESH 4
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#define AT91_SDRAMC_MODE_EXT_LMR 5
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#define AT91_SDRAMC_MODE_DEEP 6
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#define AT91_SDRAMC_TR 0x04 /* SDRAM Controller Refresh Timer Register */
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#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Counter */
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#define AT91_SDRAMC_CR 0x08 /* SDRAM Controller Configuration Register */
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#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
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#define AT91_SDRAMC_NC_8 (0 << 0)
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#define AT91_SDRAMC_NC_9 (1 << 0)
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#define AT91_SDRAMC_NC_10 (2 << 0)
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#define AT91_SDRAMC_NC_11 (3 << 0)
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#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
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#define AT91_SDRAMC_NR_11 (0 << 2)
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#define AT91_SDRAMC_NR_12 (1 << 2)
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#define AT91_SDRAMC_NR_13 (2 << 2)
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#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
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#define AT91_SDRAMC_NB_2 (0 << 4)
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#define AT91_SDRAMC_NB_4 (1 << 4)
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#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
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#define AT91_SDRAMC_CAS_1 (1 << 5)
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#define AT91_SDRAMC_CAS_2 (2 << 5)
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#define AT91_SDRAMC_CAS_3 (3 << 5)
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#define AT91_SDRAMC_DBW (1 << 7) /* Data Bus Width */
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#define AT91_SDRAMC_DBW_32 (0 << 7)
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#define AT91_SDRAMC_DBW_16 (1 << 7)
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#define AT91_SDRAMC_TWR (0xf << 8) /* Write Recovery Delay */
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#define AT91_SDRAMC_TRC (0xf << 12) /* Row Cycle Delay */
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#define AT91_SDRAMC_TRP (0xf << 16) /* Row Precharge Delay */
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#define AT91_SDRAMC_TRCD (0xf << 20) /* Row to Column Delay */
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#define AT91_SDRAMC_TRAS (0xf << 24) /* Active to Precharge Delay */
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#define AT91_SDRAMC_TXSR (0xf << 28) /* Exit Self Refresh to Active Delay */
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#define AT91_SDRAMC_LPR 0x10 /* SDRAM Controller Low Power Register */
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#define AT91_SDRAMC_LPCB (3 << 0) /* Low-power Configurations */
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#define AT91_SDRAMC_LPCB_DISABLE 0
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#define AT91_SDRAMC_LPCB_SELF_REFRESH 1
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#define AT91_SDRAMC_LPCB_POWER_DOWN 2
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#define AT91_SDRAMC_LPCB_DEEP_POWER_DOWN 3
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#define AT91_SDRAMC_PASR (7 << 4) /* Partial Array Self Refresh */
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#define AT91_SDRAMC_TCSR (3 << 8) /* Temperature Compensated Self Refresh */
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#define AT91_SDRAMC_DS (3 << 10) /* Drive Strength */
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#define AT91_SDRAMC_TIMEOUT (3 << 12) /* Time to define when Low Power Mode is enabled */
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#define AT91_SDRAMC_TIMEOUT_0_CLK_CYCLES (0 << 12)
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#define AT91_SDRAMC_TIMEOUT_64_CLK_CYCLES (1 << 12)
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#define AT91_SDRAMC_TIMEOUT_128_CLK_CYCLES (2 << 12)
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#define AT91_SDRAMC_IER 0x14 /* SDRAM Controller Interrupt Enable Register */
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#define AT91_SDRAMC_IDR 0x18 /* SDRAM Controller Interrupt Disable Register */
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#define AT91_SDRAMC_IMR 0x1C /* SDRAM Controller Interrupt Mask Register */
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#define AT91_SDRAMC_ISR 0x20 /* SDRAM Controller Interrupt Status Register */
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#define AT91_SDRAMC_RES (1 << 0) /* Refresh Error Status */
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#define AT91_SDRAMC_MDR 0x24 /* SDRAM Memory Device Register */
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#define AT91_SDRAMC_MD (3 << 0) /* Memory Device Type */
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#define AT91_SDRAMC_MD_SDRAM 0
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#define AT91_SDRAMC_MD_LOW_POWER_SDRAM 1
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#endif
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