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watchdog: s3c2410: Extract disable and mask code into separate functions

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The s3c2410wdt_mask_and_disable_reset() function content is bound to be
changed further. Prepare it for upcoming changes by splitting into
separate "mask reset" and "disable reset" functions. But keep
s3c2410wdt_mask_and_disable_reset() function present as a facade.

This commit doesn't bring any functional change to existing devices, but
merely provides an infrastructure for upcoming chips support.

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Link: https://lore.kernel.org/r/20211107202943.8859-7-semen.protsenko@linaro.org
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
This commit is contained in:
Sam Protsenko 2021-11-21 18:56:41 +02:00 committed by Wim Van Sebroeck
parent 8d9fdf60e3
commit 2bd33bb4bc
1 changed files with 38 additions and 22 deletions
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58
drivers/watchdog/s3c2410_wdt.c
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@ -202,37 +202,53 @@ static inline struct s3c2410_wdt *freq_to_wdt(struct notifier_block *nb)
return container_of(nb, struct s3c2410_wdt, freq_transition);
}
static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask)
static int s3c2410wdt_disable_wdt_reset(struct s3c2410_wdt *wdt, bool mask)
{
const u32 mask_val = BIT(wdt->drv_data->mask_bit);
const u32 val = mask ? mask_val : 0;
int ret;
u32 mask_val = 1 << wdt->drv_data->mask_bit;
u32 val = 0;
/* No need to do anything if no PMU CONFIG needed */
if (!(wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG))
return 0;
if (mask)
val = mask_val;
if (wdt->drv_data->quirks & QUIRK_HAS_PMU_AUTO_DISABLE) {
ret = regmap_update_bits(wdt->pmureg,
wdt->drv_data->disable_reg, mask_val,
val);
if (ret < 0)
goto error;
}
ret = regmap_update_bits(wdt->pmureg,
wdt->drv_data->mask_reset_reg,
ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->disable_reg,
mask_val, val);
error:
if (ret < 0)
dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
return ret;
}
static int s3c2410wdt_mask_wdt_reset(struct s3c2410_wdt *wdt, bool mask)
{
const u32 mask_val = BIT(wdt->drv_data->mask_bit);
const u32 val = mask ? mask_val : 0;
int ret;
ret = regmap_update_bits(wdt->pmureg, wdt->drv_data->mask_reset_reg,
mask_val, val);
if (ret < 0)
dev_err(wdt->dev, "failed to update reg(%d)\n", ret);
return ret;
}
static int s3c2410wdt_mask_and_disable_reset(struct s3c2410_wdt *wdt, bool mask)
{
int ret;
if (wdt->drv_data->quirks & QUIRK_HAS_PMU_AUTO_DISABLE) {
ret = s3c2410wdt_disable_wdt_reset(wdt, mask);
if (ret < 0)
return ret;
}
if (wdt->drv_data->quirks & QUIRK_HAS_PMU_CONFIG) {
ret = s3c2410wdt_mask_wdt_reset(wdt, mask);
if (ret < 0)
return ret;
}
return 0;
}
static int s3c2410wdt_keepalive(struct watchdog_device *wdd)
{
struct s3c2410_wdt *wdt = watchdog_get_drvdata(wdd);