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staging: comedi: addi_tcw.h: prefer using the BIT macro

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Use the BIT macro to define the register bits.

Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Reviewed-by: Ian Abbott <abbotti@mev.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
H Hartley Sweeten 2015-08-07 11:45:01 -07:00 committed by Greg Kroah-Hartman
parent 13d825edd4
commit 2afc5d49d0
1 changed files with 24 additions and 24 deletions
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48
drivers/staging/comedi/drivers/addi_tcw.h
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@ -10,44 +10,44 @@
#define ADDI_TCW_VAL_REG 0x00
#define ADDI_TCW_SYNC_REG 0x00
#define ADDI_TCW_SYNC_CTR_TRIG (1 << 8)
#define ADDI_TCW_SYNC_CTR_DIS (1 << 7)
#define ADDI_TCW_SYNC_CTR_ENA (1 << 6)
#define ADDI_TCW_SYNC_TIMER_TRIG (1 << 5)
#define ADDI_TCW_SYNC_TIMER_DIS (1 << 4)
#define ADDI_TCW_SYNC_TIMER_ENA (1 << 3)
#define ADDI_TCW_SYNC_WDOG_TRIG (1 << 2)
#define ADDI_TCW_SYNC_WDOG_DIS (1 << 1)
#define ADDI_TCW_SYNC_WDOG_ENA (1 << 0)
#define ADDI_TCW_SYNC_CTR_TRIG BIT(8)
#define ADDI_TCW_SYNC_CTR_DIS BIT(7)
#define ADDI_TCW_SYNC_CTR_ENA BIT(6)
#define ADDI_TCW_SYNC_TIMER_TRIG BIT(5)
#define ADDI_TCW_SYNC_TIMER_DIS BIT(4)
#define ADDI_TCW_SYNC_TIMER_ENA BIT(3)
#define ADDI_TCW_SYNC_WDOG_TRIG BIT(2)
#define ADDI_TCW_SYNC_WDOG_DIS BIT(1)
#define ADDI_TCW_SYNC_WDOG_ENA BIT(0)
#define ADDI_TCW_RELOAD_REG 0x04
#define ADDI_TCW_TIMEBASE_REG 0x08
#define ADDI_TCW_CTRL_REG 0x0c
#define ADDI_TCW_CTRL_EXT_CLK_STATUS (1 << 21)
#define ADDI_TCW_CTRL_CASCADE (1 << 20)
#define ADDI_TCW_CTRL_CNTR_ENA (1 << 19)
#define ADDI_TCW_CTRL_CNT_UP (1 << 18)
#define ADDI_TCW_CTRL_EXT_CLK_STATUS BIT(21)
#define ADDI_TCW_CTRL_CASCADE BIT(20)
#define ADDI_TCW_CTRL_CNTR_ENA BIT(19)
#define ADDI_TCW_CTRL_CNT_UP BIT(18)
#define ADDI_TCW_CTRL_EXT_CLK(x) ((x) << 16)
#define ADDI_TCW_CTRL_OUT(x) ((x) << 11)
#define ADDI_TCW_CTRL_GATE (1 << 10)
#define ADDI_TCW_CTRL_TRIG (1 << 9)
#define ADDI_TCW_CTRL_GATE BIT(10)
#define ADDI_TCW_CTRL_TRIG BIT(9)
#define ADDI_TCW_CTRL_EXT_GATE(x) ((x) << 7)
#define ADDI_TCW_CTRL_EXT_TRIG(x) ((x) << 5)
#define ADDI_TCW_CTRL_TIMER_ENA (1 << 4)
#define ADDI_TCW_CTRL_RESET_ENA (1 << 3)
#define ADDI_TCW_CTRL_WARN_ENA (1 << 2)
#define ADDI_TCW_CTRL_IRQ_ENA (1 << 1)
#define ADDI_TCW_CTRL_ENA (1 << 0)
#define ADDI_TCW_CTRL_TIMER_ENA BIT(4)
#define ADDI_TCW_CTRL_RESET_ENA BIT(3)
#define ADDI_TCW_CTRL_WARN_ENA BIT(2)
#define ADDI_TCW_CTRL_IRQ_ENA BIT(1)
#define ADDI_TCW_CTRL_ENA BIT(0)
#define ADDI_TCW_STATUS_REG 0x10
#define ADDI_TCW_STATUS_SOFT_CLR (1 << 3)
#define ADDI_TCW_STATUS_SOFT_TRIG (1 << 1)
#define ADDI_TCW_STATUS_OVERFLOW (1 << 0)
#define ADDI_TCW_STATUS_SOFT_CLR BIT(3)
#define ADDI_TCW_STATUS_SOFT_TRIG BIT(1)
#define ADDI_TCW_STATUS_OVERFLOW BIT(0)
#define ADDI_TCW_IRQ_REG 0x14
#define ADDI_TCW_IRQ (1 << 0)
#define ADDI_TCW_IRQ BIT(0)
#define ADDI_TCW_WARN_TIMEVAL_REG 0x18