forked from Minki/linux
pciehp: Clean up pcie_init()
Clean up pciehp_ini(). This patch is trying to
- Remove redundant capablity checks that were already done in PCIe
port bus driver.
- Separate the code only for debugging and make debug information
easier to read.
- Make the entire code easier to read and understand what it is doing.
Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
This commit is contained in:
Kenji Kaneshige
Jesse Barnes
parent
d84be093a8
commit
2aeeef1199
@ -221,6 +221,32 @@ static void start_int_poll_timer(struct controller *ctrl, int sec)
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add_timer(&ctrl->poll_timer);
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}
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static inline int pciehp_request_irq(struct controller *ctrl)
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{
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int retval, irq = ctrl->pci_dev->irq;
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/* Install interrupt polling timer. Start with 10 sec delay */
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if (pciehp_poll_mode) {
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init_timer(&ctrl->poll_timer);
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start_int_poll_timer(ctrl, 10);
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return 0;
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}
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/* Installs the interrupt handler */
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retval = request_irq(irq, pcie_isr, IRQF_SHARED, MY_NAME, ctrl);
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if (retval)
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err("Cannot get irq %d for the hotplug controller\n", irq);
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return retval;
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}
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static inline void pciehp_free_irq(struct controller *ctrl)
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{
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if (pciehp_poll_mode)
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del_timer_sync(&ctrl->poll_timer);
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else
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free_irq(ctrl->pci_dev->irq, ctrl);
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}
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static inline int pcie_wait_cmd(struct controller *ctrl)
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{
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int retval = 0;
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@ -541,10 +567,8 @@ static void hpc_release_ctlr(struct controller *ctrl)
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if (pcie_write_cmd(ctrl, 0, HP_INTR_ENABLE | CMD_CMPL_INTR_ENABLE))
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err("%s: Cannot mask hotplut interrupt enable\n", __func__);
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if (pciehp_poll_mode)
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del_timer(&ctrl->poll_timer);
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else
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free_irq(ctrl->pci_dev->irq, ctrl);
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/* Free interrupt handler or interrupt polling timer */
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pciehp_free_irq(ctrl);
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/*
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* If this is the last controller to be released, destroy the
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@ -1057,121 +1081,79 @@ abort:
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return -1;
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}
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static inline void dbg_ctrl(struct controller *ctrl)
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{
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int i;
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u16 reg16;
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struct pci_dev *pdev = ctrl->pci_dev;
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if (!pciehp_debug)
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return;
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dbg("Hotplug Controller:\n");
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dbg(" Seg/Bus/Dev/Func/IRQ : %s IRQ %d\n", pci_name(pdev), pdev->irq);
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dbg(" Vendor ID : 0x%04x\n", pdev->vendor);
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dbg(" Device ID : 0x%04x\n", pdev->device);
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dbg(" Subsystem ID : 0x%04x\n", pdev->subsystem_device);
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dbg(" Subsystem Vendor ID : 0x%04x\n", pdev->subsystem_vendor);
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dbg(" PCIe Cap offset : 0x%02x\n", ctrl->cap_base);
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for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
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if (!pci_resource_len(pdev, i))
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continue;
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dbg(" PCI resource [%d] : 0x%llx@0x%llx\n", i,
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(unsigned long long)pci_resource_len(pdev, i),
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(unsigned long long)pci_resource_start(pdev, i));
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}
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dbg("Slot Capabilities : 0x%08x\n", ctrl->slot_cap);
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dbg(" Physical Slot Number : %d\n", ctrl->first_slot);
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dbg(" Attention Button : %3s\n", ATTN_BUTTN(ctrl) ? "yes" : "no");
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dbg(" Power Controller : %3s\n", POWER_CTRL(ctrl) ? "yes" : "no");
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dbg(" MRL Sensor : %3s\n", MRL_SENS(ctrl) ? "yes" : "no");
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dbg(" Attention Indicator : %3s\n", ATTN_LED(ctrl) ? "yes" : "no");
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dbg(" Power Indicator : %3s\n", PWR_LED(ctrl) ? "yes" : "no");
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dbg(" Hot-Plug Surprise : %3s\n", HP_SUPR_RM(ctrl) ? "yes" : "no");
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dbg(" EMI Present : %3s\n", EMI(ctrl) ? "yes" : "no");
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pciehp_readw(ctrl, SLOTSTATUS, ®16);
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dbg("Slot Status : 0x%04x\n", reg16);
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pciehp_readw(ctrl, SLOTSTATUS, ®16);
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dbg("Slot Control : 0x%04x\n", reg16);
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}
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int pcie_init(struct controller *ctrl, struct pcie_device *dev)
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{
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int rc;
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u16 cap_reg;
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u32 slot_cap;
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int cap_base;
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u16 slot_status, slot_ctrl;
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struct pci_dev *pdev;
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struct pci_dev *pdev = dev->port;
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pdev = dev->port;
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ctrl->pci_dev = pdev; /* save pci_dev in context */
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dbg("%s: hotplug controller vendor id 0x%x device id 0x%x\n",
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__func__, pdev->vendor, pdev->device);
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cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
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if (cap_base == 0) {
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dbg("%s: Can't find PCI_CAP_ID_EXP (0x10)\n", __func__);
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ctrl->pci_dev = pdev;
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ctrl->cap_base = pci_find_capability(pdev, PCI_CAP_ID_EXP);
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if (!ctrl->cap_base) {
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err("%s: Cannot find PCI Express capability\n", __func__);
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goto abort;
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}
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ctrl->cap_base = cap_base;
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dbg("%s: pcie_cap_base %x\n", __func__, cap_base);
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rc = pciehp_readw(ctrl, CAPREG, &cap_reg);
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if (rc) {
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err("%s: Cannot read CAPREG register\n", __func__);
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goto abort;
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}
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dbg("%s: CAPREG offset %x cap_reg %x\n",
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__func__, ctrl->cap_base + CAPREG, cap_reg);
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if (((cap_reg & SLOT_IMPL) == 0) ||
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(((cap_reg & DEV_PORT_TYPE) != 0x0040)
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&& ((cap_reg & DEV_PORT_TYPE) != 0x0060))) {
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dbg("%s : This is not a root port or the port is not "
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"connected to a slot\n", __func__);
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goto abort;
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}
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rc = pciehp_readl(ctrl, SLOTCAP, &slot_cap);
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if (rc) {
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if (pciehp_readl(ctrl, SLOTCAP, &slot_cap)) {
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err("%s: Cannot read SLOTCAP register\n", __func__);
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goto abort;
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}
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dbg("%s: SLOTCAP offset %x slot_cap %x\n",
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__func__, ctrl->cap_base + SLOTCAP, slot_cap);
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if (!(slot_cap & HP_CAP)) {
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dbg("%s : This slot is not hot-plug capable\n", __func__);
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goto abort;
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}
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/* For debugging purpose */
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rc = pciehp_readw(ctrl, SLOTSTATUS, &slot_status);
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if (rc) {
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err("%s: Cannot read SLOTSTATUS register\n", __func__);
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goto abort;
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}
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dbg("%s: SLOTSTATUS offset %x slot_status %x\n",
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__func__, ctrl->cap_base + SLOTSTATUS, slot_status);
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rc = pciehp_readw(ctrl, SLOTCTRL, &slot_ctrl);
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if (rc) {
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err("%s: Cannot read SLOTCTRL register\n", __func__);
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goto abort;
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}
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dbg("%s: SLOTCTRL offset %x slot_ctrl %x\n",
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__func__, ctrl->cap_base + SLOTCTRL, slot_ctrl);
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for (rc = 0; rc < DEVICE_COUNT_RESOURCE; rc++)
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if (pci_resource_len(pdev, rc) > 0)
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dbg("pci resource[%d] start=0x%llx(len=0x%llx)\n", rc,
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(unsigned long long)pci_resource_start(pdev, rc),
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(unsigned long long)pci_resource_len(pdev, rc));
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ctrl->slot_cap = slot_cap;
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ctrl->first_slot = slot_cap >> 19;
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ctrl->slot_device_offset = 0;
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ctrl->num_slots = 1;
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ctrl->hpc_ops = &pciehp_hpc_ops;
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mutex_init(&ctrl->crit_sect);
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mutex_init(&ctrl->ctrl_lock);
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init_waitqueue_head(&ctrl->queue);
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dbg_ctrl(ctrl);
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info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n",
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pdev->vendor, pdev->device,
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pdev->subsystem_vendor, pdev->subsystem_device);
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mutex_init(&ctrl->crit_sect);
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mutex_init(&ctrl->ctrl_lock);
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/* setup wait queue */
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init_waitqueue_head(&ctrl->queue);
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/* return PCI Controller Info */
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ctrl->slot_device_offset = 0;
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ctrl->num_slots = 1;
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ctrl->first_slot = slot_cap >> 19;
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ctrl->slot_cap = slot_cap;
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rc = pcie_init_hardware_part1(ctrl, dev);
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if (rc)
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if (pcie_init_hardware_part1(ctrl, dev))
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goto abort;
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if (pciehp_poll_mode) {
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/* Install interrupt polling timer. Start with 10 sec delay */
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init_timer(&ctrl->poll_timer);
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start_int_poll_timer(ctrl, 10);
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} else {
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/* Installs the interrupt handler */
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rc = request_irq(ctrl->pci_dev->irq, pcie_isr, IRQF_SHARED,
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MY_NAME, (void *)ctrl);
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dbg("%s: request_irq %d for hpc%d (returns %d)\n",
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__func__, ctrl->pci_dev->irq,
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atomic_read(&pciehp_num_controllers), rc);
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if (rc) {
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err("Can't get irq %d for the hotplug controller\n",
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ctrl->pci_dev->irq);
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goto abort;
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}
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}
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dbg("pciehp ctrl b:d:f:irq=0x%x:%x:%x:%x\n", pdev->bus->number,
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PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn), dev->irq);
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if (pciehp_request_irq(ctrl))
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goto abort;
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/*
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* If this is the first controller to be initialized,
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@ -1180,21 +1162,17 @@ int pcie_init(struct controller *ctrl, struct pcie_device *dev)
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if (atomic_add_return(1, &pciehp_num_controllers) == 1) {
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pciehp_wq = create_singlethread_workqueue("pciehpd");
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if (!pciehp_wq) {
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rc = -ENOMEM;
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goto abort_free_irq;
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}
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}
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rc = pcie_init_hardware_part2(ctrl, dev);
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if (rc == 0) {
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ctrl->hpc_ops = &pciehp_hpc_ops;
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return 0;
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}
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if (pcie_init_hardware_part2(ctrl, dev))
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goto abort_free_irq;
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return 0;
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abort_free_irq:
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if (pciehp_poll_mode)
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del_timer_sync(&ctrl->poll_timer);
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else
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free_irq(ctrl->pci_dev->irq, ctrl);
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pciehp_free_irq(ctrl);
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abort:
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return -1;
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}
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