drm/amd/powerplay: enable power containment features for tonga.
v2: fix build error introduced when fix code style problems. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu
Alex Deucher
parent
e9f11dc80a
commit
2a702ccd9a
@ -4,7 +4,7 @@
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HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \
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hardwaremanager.o pp_acpi.o cz_hwmgr.o \
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cz_clockpowergating.o \
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cz_clockpowergating.o tonga_powertune.o\
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tonga_processpptables.o ppatomctrl.o \
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tonga_hwmgr.o pppcielanes.o tonga_thermal.o\
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fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \
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@ -302,6 +302,8 @@ void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_DisableMemoryTransition);
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tonga_initialize_power_tune_defaults(hwmgr);
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data->mclk_strobe_mode_threshold = 40000;
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data->mclk_stutter_mode_threshold = 30000;
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data->mclk_edc_enable_threshold = 40000;
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@ -2479,7 +2481,7 @@ static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t
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graphic_level->VoltageDownHyst = 0;
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graphic_level->PowerThrottle = 0;
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threshold = engine_clock * data->fast_watemark_threshold / 100;
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threshold = engine_clock * data->fast_watermark_threshold / 100;
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/*
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*get the DAL clock. do it in funture.
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PECI_GetMinClockSettings(hwmgr->peci, &minClocks);
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@ -2982,6 +2984,10 @@ int tonga_init_smc_table(struct pp_hwmgr *hwmgr)
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PP_ASSERT_WITH_CODE(0 == result,
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"Failed to initialize Boot Level!", return result;);
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result = tonga_populate_bapm_parameters_in_dpm_table(hwmgr);
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PP_ASSERT_WITH_CODE(result == 0,
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"Failed to populate BAPM Parameters!", return result);
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_ClockStretcher)) {
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result = tonga_populate_clock_stretcher_data_table(hwmgr);
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@ -4370,6 +4376,10 @@ int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
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PP_ASSERT_WITH_CODE((0 == tmp_result),
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"Failed to initialize ARB table index!", result = tmp_result);
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tmp_result = tonga_populate_pm_fuses(hwmgr);
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PP_ASSERT_WITH_CODE((tmp_result == 0),
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"Failed to populate PM fuses!", result = tmp_result);
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tmp_result = tonga_populate_initial_mc_reg_table(hwmgr);
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PP_ASSERT_WITH_CODE((0 == tmp_result),
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"Failed to populate initialize MC Reg table!", result = tmp_result);
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@ -4388,6 +4398,18 @@ int tonga_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
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PP_ASSERT_WITH_CODE((0 == tmp_result),
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"Failed to start DPM!", result = tmp_result);
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tmp_result = tonga_enable_smc_cac(hwmgr);
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PP_ASSERT_WITH_CODE((tmp_result == 0),
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"Failed to enable SMC CAC!", result = tmp_result);
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tmp_result = tonga_enable_power_containment(hwmgr);
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PP_ASSERT_WITH_CODE((tmp_result == 0),
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"Failed to enable power containment!", result = tmp_result);
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tmp_result = tonga_power_control_set_level(hwmgr);
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PP_ASSERT_WITH_CODE((tmp_result == 0),
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"Failed to power control set level!", result = tmp_result);
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return result;
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}
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@ -300,6 +300,7 @@ struct tonga_hwmgr {
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bool dll_defaule_on;
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bool performance_request_registered;
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/* ----------------- Low Power Features ---------------------*/
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phw_tonga_bacos bacos;
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phw_tonga_ulv_parm ulv;
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@ -314,10 +315,14 @@ struct tonga_hwmgr {
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bool enable_tdc_limit_feature;
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bool enable_pkg_pwr_tracking_feature;
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bool disable_uvd_power_tune_feature;
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phw_tonga_pt_defaults *power_tune_defaults;
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struct tonga_pt_defaults *power_tune_defaults;
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SMU72_Discrete_PmFuses power_tune_table;
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uint32_t ul_dte_tj_offset; /* Fudge factor in DPM table to correct HW DTE errors */
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uint32_t fast_watemark_threshold; /* use fast watermark if clock is equal or above this. In percentage of the target high sclk. */
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uint32_t dte_tj_offset; /* Fudge factor in DPM table to correct HW DTE errors */
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uint32_t fast_watermark_threshold; /* use fast watermark if clock is equal or above this. In percentage of the target high sclk. */
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bool enable_dte_feature;
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/* ----------------- Phase Shedding ---------------------*/
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bool vddc_phase_shed_control;
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498
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_powertune.c
Normal file
498
drivers/gpu/drm/amd/powerplay/hwmgr/tonga_powertune.c
Normal file
@ -0,0 +1,498 @@
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/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "hwmgr.h"
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#include "smumgr.h"
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#include "tonga_hwmgr.h"
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#include "tonga_powertune.h"
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#include "tonga_smumgr.h"
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#include "smu72_discrete.h"
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#include "pp_debug.h"
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#include "tonga_ppsmc.h"
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#define VOLTAGE_SCALE 4
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#define POWERTUNE_DEFAULT_SET_MAX 1
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struct tonga_pt_defaults tonga_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = {
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/* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt, TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */
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{1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000,
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{0x79, 0x253, 0x25D, 0xAE, 0x72, 0x80, 0x83, 0x86, 0x6F, 0xC8, 0xC9, 0xC9, 0x2F, 0x4D, 0x61},
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{0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } },
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};
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void tonga_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr)
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{
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struct tonga_hwmgr *tonga_hwmgr = (struct tonga_hwmgr *)(hwmgr->backend);
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struct phm_ppt_v1_information *table_info =
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(struct phm_ppt_v1_information *)(hwmgr->pptable);
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uint32_t tmp = 0;
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if (table_info &&
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table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX &&
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table_info->cac_dtp_table->usPowerTuneDataSetID)
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tonga_hwmgr->power_tune_defaults =
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&tonga_power_tune_data_set_array
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[table_info->cac_dtp_table->usPowerTuneDataSetID - 1];
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else
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tonga_hwmgr->power_tune_defaults = &tonga_power_tune_data_set_array[0];
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/* Assume disabled */
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phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_PowerContainment);
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phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_CAC);
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phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_SQRamping);
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phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_DBRamping);
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phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_TDRamping);
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phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_TCPRamping);
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tonga_hwmgr->dte_tj_offset = tmp;
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if (!tmp) {
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phm_cap_set(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_CAC);
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tonga_hwmgr->fast_watermark_threshold = 100;
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_PowerContainment)) {
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tmp = 1;
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tonga_hwmgr->enable_dte_feature = tmp ? false : true;
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tonga_hwmgr->enable_tdc_limit_feature = tmp ? true : false;
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tonga_hwmgr->enable_pkg_pwr_tracking_feature = tmp ? true : false;
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}
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}
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}
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int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr)
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{
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struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
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struct tonga_pt_defaults *defaults = data->power_tune_defaults;
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SMU72_Discrete_DpmTable *dpm_table = &(data->smc_state_table);
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struct phm_ppt_v1_information *table_info =
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(struct phm_ppt_v1_information *)(hwmgr->pptable);
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struct phm_cac_tdp_table *cac_dtp_table = table_info->cac_dtp_table;
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int i, j, k;
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uint16_t *pdef1;
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uint16_t *pdef2;
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/* TDP number of fraction bits are changed from 8 to 7 for Fiji
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* as requested by SMC team
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*/
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dpm_table->DefaultTdp = PP_HOST_TO_SMC_US(
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(uint16_t)(cac_dtp_table->usTDP * 256));
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dpm_table->TargetTdp = PP_HOST_TO_SMC_US(
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(uint16_t)(cac_dtp_table->usConfigurableTDP * 256));
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PP_ASSERT_WITH_CODE(cac_dtp_table->usTargetOperatingTemp <= 255,
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"Target Operating Temp is out of Range!",
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);
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dpm_table->GpuTjMax = (uint8_t)(cac_dtp_table->usTargetOperatingTemp);
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dpm_table->GpuTjHyst = 8;
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dpm_table->DTEAmbientTempBase = defaults->dte_ambient_temp_base;
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dpm_table->BAPM_TEMP_GRADIENT = PP_HOST_TO_SMC_UL(defaults->bamp_temp_gradient);
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pdef1 = defaults->bapmti_r;
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pdef2 = defaults->bapmti_rc;
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for (i = 0; i < SMU72_DTE_ITERATIONS; i++) {
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for (j = 0; j < SMU72_DTE_SOURCES; j++) {
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for (k = 0; k < SMU72_DTE_SINKS; k++) {
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dpm_table->BAPMTI_R[i][j][k] = PP_HOST_TO_SMC_US(*pdef1);
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dpm_table->BAPMTI_RC[i][j][k] = PP_HOST_TO_SMC_US(*pdef2);
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pdef1++;
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pdef2++;
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}
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}
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}
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return 0;
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}
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static int tonga_populate_svi_load_line(struct pp_hwmgr *hwmgr)
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{
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struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
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const struct tonga_pt_defaults *defaults = data->power_tune_defaults;
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data->power_tune_table.SviLoadLineEn = defaults->svi_load_line_en;
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data->power_tune_table.SviLoadLineVddC = defaults->svi_load_line_vddC;
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data->power_tune_table.SviLoadLineTrimVddC = 3;
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data->power_tune_table.SviLoadLineOffsetVddC = 0;
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return 0;
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}
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static int tonga_populate_tdc_limit(struct pp_hwmgr *hwmgr)
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{
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uint16_t tdc_limit;
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struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
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struct phm_ppt_v1_information *table_info =
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(struct phm_ppt_v1_information *)(hwmgr->pptable);
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const struct tonga_pt_defaults *defaults = data->power_tune_defaults;
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/* TDC number of fraction bits are changed from 8 to 7
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* for Fiji as requested by SMC team
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*/
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tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 256);
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data->power_tune_table.TDC_VDDC_PkgLimit =
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CONVERT_FROM_HOST_TO_SMC_US(tdc_limit);
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data->power_tune_table.TDC_VDDC_ThrottleReleaseLimitPerc =
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defaults->tdc_vddc_throttle_release_limit_perc;
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data->power_tune_table.TDC_MAWt = defaults->tdc_mawt;
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return 0;
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}
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static int tonga_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset)
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{
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struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
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const struct tonga_pt_defaults *defaults = data->power_tune_defaults;
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uint32_t temp;
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if (tonga_read_smc_sram_dword(hwmgr->smumgr,
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fuse_table_offset +
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offsetof(SMU72_Discrete_PmFuses, TdcWaterfallCtl),
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(uint32_t *)&temp, data->sram_end))
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PP_ASSERT_WITH_CODE(false,
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"Attempt to read PmFuses.DW6 (SviLoadLineEn) from SMC Failed!",
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return -EINVAL);
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else
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data->power_tune_table.TdcWaterfallCtl = defaults->tdc_waterfall_ctl;
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return 0;
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}
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static int tonga_populate_temperature_scaler(struct pp_hwmgr *hwmgr)
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{
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int i;
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struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
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/* Currently not used. Set all to zero. */
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for (i = 0; i < 16; i++)
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data->power_tune_table.LPMLTemperatureScaler[i] = 0;
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return 0;
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}
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static int tonga_populate_fuzzy_fan(struct pp_hwmgr *hwmgr)
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{
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struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
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if ((hwmgr->thermal_controller.advanceFanControlParameters.
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usFanOutputSensitivity & (1 << 15)) ||
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(hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity == 0))
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hwmgr->thermal_controller.advanceFanControlParameters.
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usFanOutputSensitivity = hwmgr->thermal_controller.
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advanceFanControlParameters.usDefaultFanOutputSensitivity;
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data->power_tune_table.FuzzyFan_PwmSetDelta =
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PP_HOST_TO_SMC_US(hwmgr->thermal_controller.
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advanceFanControlParameters.usFanOutputSensitivity);
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return 0;
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}
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static int tonga_populate_gnb_lpml(struct pp_hwmgr *hwmgr)
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{
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int i;
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struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
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/* Currently not used. Set all to zero. */
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for (i = 0; i < 16; i++)
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data->power_tune_table.GnbLPML[i] = 0;
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return 0;
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}
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static int tonga_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr)
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{
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return 0;
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}
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static int tonga_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr)
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{
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struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
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struct phm_ppt_v1_information *table_info =
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(struct phm_ppt_v1_information *)(hwmgr->pptable);
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uint16_t hi_sidd = data->power_tune_table.BapmVddCBaseLeakageHiSidd;
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uint16_t lo_sidd = data->power_tune_table.BapmVddCBaseLeakageLoSidd;
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struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
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hi_sidd = (uint16_t)(cac_table->usHighCACLeakage / 100 * 256);
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lo_sidd = (uint16_t)(cac_table->usLowCACLeakage / 100 * 256);
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data->power_tune_table.BapmVddCBaseLeakageHiSidd =
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CONVERT_FROM_HOST_TO_SMC_US(hi_sidd);
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data->power_tune_table.BapmVddCBaseLeakageLoSidd =
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CONVERT_FROM_HOST_TO_SMC_US(lo_sidd);
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return 0;
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}
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int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr)
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{
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struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
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uint32_t pm_fuse_table_offset;
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if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
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PHM_PlatformCaps_PowerContainment)) {
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if (tonga_read_smc_sram_dword(hwmgr->smumgr,
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SMU72_FIRMWARE_HEADER_LOCATION +
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offsetof(SMU72_Firmware_Header, PmFuseTable),
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&pm_fuse_table_offset, data->sram_end))
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PP_ASSERT_WITH_CODE(false,
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"Attempt to get pm_fuse_table_offset Failed!",
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return -EINVAL);
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||||
|
||||
/* DW6 */
|
||||
if (tonga_populate_svi_load_line(hwmgr))
|
||||
PP_ASSERT_WITH_CODE(false,
|
||||
"Attempt to populate SviLoadLine Failed!",
|
||||
return -EINVAL);
|
||||
/* DW7 */
|
||||
if (tonga_populate_tdc_limit(hwmgr))
|
||||
PP_ASSERT_WITH_CODE(false,
|
||||
"Attempt to populate TDCLimit Failed!", return -EINVAL);
|
||||
/* DW8 */
|
||||
if (tonga_populate_dw8(hwmgr, pm_fuse_table_offset))
|
||||
PP_ASSERT_WITH_CODE(false,
|
||||
"Attempt to populate TdcWaterfallCtl Failed !",
|
||||
return -EINVAL);
|
||||
|
||||
/* DW9-DW12 */
|
||||
if (tonga_populate_temperature_scaler(hwmgr) != 0)
|
||||
PP_ASSERT_WITH_CODE(false,
|
||||
"Attempt to populate LPMLTemperatureScaler Failed!",
|
||||
return -EINVAL);
|
||||
|
||||
/* DW13-DW14 */
|
||||
if (tonga_populate_fuzzy_fan(hwmgr))
|
||||
PP_ASSERT_WITH_CODE(false,
|
||||
"Attempt to populate Fuzzy Fan Control parameters Failed!",
|
||||
return -EINVAL);
|
||||
|
||||
/* DW15-DW18 */
|
||||
if (tonga_populate_gnb_lpml(hwmgr))
|
||||
PP_ASSERT_WITH_CODE(false,
|
||||
"Attempt to populate GnbLPML Failed!",
|
||||
return -EINVAL);
|
||||
|
||||
/* DW19 */
|
||||
if (tonga_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr))
|
||||
PP_ASSERT_WITH_CODE(false,
|
||||
"Attempt to populate GnbLPML Min and Max Vid Failed!",
|
||||
return -EINVAL);
|
||||
|
||||
/* DW20 */
|
||||
if (tonga_populate_bapm_vddc_base_leakage_sidd(hwmgr))
|
||||
PP_ASSERT_WITH_CODE(false,
|
||||
"Attempt to populate BapmVddCBaseLeakage Hi and Lo Sidd Failed!",
|
||||
return -EINVAL);
|
||||
|
||||
if (tonga_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset,
|
||||
(uint8_t *)&data->power_tune_table,
|
||||
sizeof(struct SMU72_Discrete_PmFuses), data->sram_end))
|
||||
PP_ASSERT_WITH_CODE(false,
|
||||
"Attempt to download PmFuseTable Failed!",
|
||||
return -EINVAL);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int tonga_enable_smc_cac(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
|
||||
int result = 0;
|
||||
|
||||
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
||||
PHM_PlatformCaps_CAC)) {
|
||||
int smc_result;
|
||||
|
||||
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
|
||||
(uint16_t)(PPSMC_MSG_EnableCac));
|
||||
PP_ASSERT_WITH_CODE((smc_result == 0),
|
||||
"Failed to enable CAC in SMC.", result = -1);
|
||||
|
||||
data->cac_enabled = (smc_result == 0) ? true : false;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
int tonga_disable_smc_cac(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
|
||||
int result = 0;
|
||||
|
||||
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
||||
PHM_PlatformCaps_CAC) && data->cac_enabled) {
|
||||
int smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
|
||||
(uint16_t)(PPSMC_MSG_DisableCac));
|
||||
PP_ASSERT_WITH_CODE((smc_result == 0),
|
||||
"Failed to disable CAC in SMC.", result = -1);
|
||||
|
||||
data->cac_enabled = false;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
int tonga_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n)
|
||||
{
|
||||
struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
|
||||
|
||||
if (data->power_containment_features &
|
||||
POWERCONTAINMENT_FEATURE_PkgPwrLimit)
|
||||
return smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
|
||||
PPSMC_MSG_PkgPwrSetLimit, n);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int tonga_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp)
|
||||
{
|
||||
return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr,
|
||||
PPSMC_MSG_OverDriveSetTargetTdp, target_tdp);
|
||||
}
|
||||
|
||||
int tonga_enable_power_containment(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
|
||||
struct phm_ppt_v1_information *table_info =
|
||||
(struct phm_ppt_v1_information *)(hwmgr->pptable);
|
||||
int smc_result;
|
||||
int result = 0;
|
||||
|
||||
data->power_containment_features = 0;
|
||||
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
||||
PHM_PlatformCaps_PowerContainment)) {
|
||||
if (data->enable_dte_feature) {
|
||||
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
|
||||
(uint16_t)(PPSMC_MSG_EnableDTE));
|
||||
PP_ASSERT_WITH_CODE((smc_result == 0),
|
||||
"Failed to enable DTE in SMC.", result = -1;);
|
||||
if (smc_result == 0)
|
||||
data->power_containment_features |= POWERCONTAINMENT_FEATURE_DTE;
|
||||
}
|
||||
|
||||
if (data->enable_tdc_limit_feature) {
|
||||
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
|
||||
(uint16_t)(PPSMC_MSG_TDCLimitEnable));
|
||||
PP_ASSERT_WITH_CODE((smc_result == 0),
|
||||
"Failed to enable TDCLimit in SMC.", result = -1;);
|
||||
if (smc_result == 0)
|
||||
data->power_containment_features |=
|
||||
POWERCONTAINMENT_FEATURE_TDCLimit;
|
||||
}
|
||||
|
||||
if (data->enable_pkg_pwr_tracking_feature) {
|
||||
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
|
||||
(uint16_t)(PPSMC_MSG_PkgPwrLimitEnable));
|
||||
PP_ASSERT_WITH_CODE((smc_result == 0),
|
||||
"Failed to enable PkgPwrTracking in SMC.", result = -1;);
|
||||
if (smc_result == 0) {
|
||||
struct phm_cac_tdp_table *cac_table =
|
||||
table_info->cac_dtp_table;
|
||||
uint32_t default_limit =
|
||||
(uint32_t)(cac_table->usMaximumPowerDeliveryLimit * 256);
|
||||
|
||||
data->power_containment_features |=
|
||||
POWERCONTAINMENT_FEATURE_PkgPwrLimit;
|
||||
|
||||
if (tonga_set_power_limit(hwmgr, default_limit))
|
||||
printk(KERN_ERR "Failed to set Default Power Limit in SMC!");
|
||||
}
|
||||
}
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
int tonga_disable_power_containment(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
struct tonga_hwmgr *data = (struct tonga_hwmgr *)(hwmgr->backend);
|
||||
int result = 0;
|
||||
|
||||
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
||||
PHM_PlatformCaps_PowerContainment) &&
|
||||
data->power_containment_features) {
|
||||
int smc_result;
|
||||
|
||||
if (data->power_containment_features &
|
||||
POWERCONTAINMENT_FEATURE_TDCLimit) {
|
||||
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
|
||||
(uint16_t)(PPSMC_MSG_TDCLimitDisable));
|
||||
PP_ASSERT_WITH_CODE((smc_result == 0),
|
||||
"Failed to disable TDCLimit in SMC.",
|
||||
result = smc_result);
|
||||
}
|
||||
|
||||
if (data->power_containment_features &
|
||||
POWERCONTAINMENT_FEATURE_DTE) {
|
||||
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
|
||||
(uint16_t)(PPSMC_MSG_DisableDTE));
|
||||
PP_ASSERT_WITH_CODE((smc_result == 0),
|
||||
"Failed to disable DTE in SMC.",
|
||||
result = smc_result);
|
||||
}
|
||||
|
||||
if (data->power_containment_features &
|
||||
POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
|
||||
smc_result = smum_send_msg_to_smc(hwmgr->smumgr,
|
||||
(uint16_t)(PPSMC_MSG_PkgPwrLimitDisable));
|
||||
PP_ASSERT_WITH_CODE((smc_result == 0),
|
||||
"Failed to disable PkgPwrTracking in SMC.",
|
||||
result = smc_result);
|
||||
}
|
||||
data->power_containment_features = 0;
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
int tonga_power_control_set_level(struct pp_hwmgr *hwmgr)
|
||||
{
|
||||
struct phm_ppt_v1_information *table_info =
|
||||
(struct phm_ppt_v1_information *)(hwmgr->pptable);
|
||||
struct phm_cac_tdp_table *cac_table = table_info->cac_dtp_table;
|
||||
int adjust_percent, target_tdp;
|
||||
int result = 0;
|
||||
|
||||
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
|
||||
PHM_PlatformCaps_PowerContainment)) {
|
||||
/* adjustment percentage has already been validated */
|
||||
adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ?
|
||||
hwmgr->platform_descriptor.TDPAdjustment :
|
||||
(-1 * hwmgr->platform_descriptor.TDPAdjustment);
|
||||
/* SMC requested that target_tdp to be 7 bit fraction in DPM table
|
||||
* but message to be 8 bit fraction for messages
|
||||
*/
|
||||
target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100;
|
||||
result = tonga_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);
|
||||
}
|
||||
|
||||
return result;
|
||||
}
|
||||
@ -34,21 +34,24 @@ enum _phw_tonga_ptc_config_reg_type {
|
||||
};
|
||||
typedef enum _phw_tonga_ptc_config_reg_type phw_tonga_ptc_config_reg_type;
|
||||
|
||||
/* PowerContainment Features */
|
||||
#define POWERCONTAINMENT_FEATURE_DTE 0x00000001
|
||||
|
||||
|
||||
/* PowerContainment Features */
|
||||
#define POWERCONTAINMENT_FEATURE_BAPM 0x00000001
|
||||
#define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002
|
||||
#define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004
|
||||
|
||||
struct _phw_tonga_pt_config_reg {
|
||||
struct tonga_pt_config_reg {
|
||||
uint32_t Offset;
|
||||
uint32_t Mask;
|
||||
uint32_t Shift;
|
||||
uint32_t Value;
|
||||
phw_tonga_ptc_config_reg_type Type;
|
||||
};
|
||||
typedef struct _phw_tonga_pt_config_reg phw_tonga_pt_config_reg;
|
||||
|
||||
struct _phw_tonga_pt_defaults {
|
||||
struct tonga_pt_defaults {
|
||||
uint8_t svi_load_line_en;
|
||||
uint8_t svi_load_line_vddC;
|
||||
uint8_t tdc_vddc_throttle_release_limit_perc;
|
||||
@ -60,7 +63,18 @@ struct _phw_tonga_pt_defaults {
|
||||
uint16_t bapmti_r[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
|
||||
uint16_t bapmti_rc[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
|
||||
};
|
||||
typedef struct _phw_tonga_pt_defaults phw_tonga_pt_defaults;
|
||||
|
||||
|
||||
|
||||
void tonga_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr);
|
||||
int tonga_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr);
|
||||
int tonga_populate_pm_fuses(struct pp_hwmgr *hwmgr);
|
||||
int tonga_enable_smc_cac(struct pp_hwmgr *hwmgr);
|
||||
int tonga_disable_smc_cac(struct pp_hwmgr *hwmgr);
|
||||
int tonga_enable_power_containment(struct pp_hwmgr *hwmgr);
|
||||
int tonga_disable_power_containment(struct pp_hwmgr *hwmgr);
|
||||
int tonga_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n);
|
||||
int tonga_power_control_set_level(struct pp_hwmgr *hwmgr);
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user