forked from Minki/linux
rtc: vr41xx: remove driver
Commit d3164e2f3b ("MIPS: Remove VR41xx support") removed support
for MIPS VR41xx platform, so remove exclusive drivers for this
platform, too.
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20220715135330.134684-1-tsbogend@alpha.franken.de
This commit is contained in:
Thomas Bogendoerfer
Alexandre Belloni
parent
03d7a73281
commit
2a692245b6
@ -1478,16 +1478,6 @@ config RTC_DRV_SUNPLUS
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This driver can also be built as a module. If so, the module
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will be called rtc-sunplus.
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config RTC_DRV_VR41XX
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tristate "NEC VR41XX"
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depends on CPU_VR41XX || COMPILE_TEST
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help
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If you say Y here you will get access to the real time clock
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built into your NEC VR41XX CPU.
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To compile this driver as a module, choose M here: the
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module will be called rtc-vr41xx.
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config RTC_DRV_PL030
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tristate "ARM AMBA PL030 RTC"
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depends on ARM_AMBA
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@ -178,7 +178,6 @@ obj-$(CONFIG_RTC_DRV_TPS6586X) += rtc-tps6586x.o
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obj-$(CONFIG_RTC_DRV_TPS65910) += rtc-tps65910.o
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obj-$(CONFIG_RTC_DRV_TWL4030) += rtc-twl.o
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obj-$(CONFIG_RTC_DRV_V3020) += rtc-v3020.o
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obj-$(CONFIG_RTC_DRV_VR41XX) += rtc-vr41xx.o
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obj-$(CONFIG_RTC_DRV_VT8500) += rtc-vt8500.o
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obj-$(CONFIG_RTC_DRV_WILCO_EC) += rtc-wilco-ec.o
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obj-$(CONFIG_RTC_DRV_WM831X) += rtc-wm831x.o
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@ -1,363 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Driver for NEC VR4100 series Real Time Clock unit.
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*
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* Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
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*/
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#include <linux/compat.h>
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#include <linux/err.h>
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#include <linux/fs.h>
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/rtc.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#include <linux/uaccess.h>
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#include <linux/log2.h>
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#include <asm/div64.h>
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MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
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MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
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MODULE_LICENSE("GPL v2");
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/* RTC 1 registers */
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#define ETIMELREG 0x00
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#define ETIMEMREG 0x02
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#define ETIMEHREG 0x04
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/* RFU */
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#define ECMPLREG 0x08
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#define ECMPMREG 0x0a
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#define ECMPHREG 0x0c
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/* RFU */
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#define RTCL1LREG 0x10
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#define RTCL1HREG 0x12
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#define RTCL1CNTLREG 0x14
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#define RTCL1CNTHREG 0x16
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#define RTCL2LREG 0x18
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#define RTCL2HREG 0x1a
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#define RTCL2CNTLREG 0x1c
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#define RTCL2CNTHREG 0x1e
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/* RTC 2 registers */
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#define TCLKLREG 0x00
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#define TCLKHREG 0x02
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#define TCLKCNTLREG 0x04
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#define TCLKCNTHREG 0x06
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/* RFU */
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#define RTCINTREG 0x1e
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#define TCLOCK_INT 0x08
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#define RTCLONG2_INT 0x04
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#define RTCLONG1_INT 0x02
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#define ELAPSEDTIME_INT 0x01
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#define RTC_FREQUENCY 32768
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#define MAX_PERIODIC_RATE 6553
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static void __iomem *rtc1_base;
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static void __iomem *rtc2_base;
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#define rtc1_read(offset) readw(rtc1_base + (offset))
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#define rtc1_write(offset, value) writew((value), rtc1_base + (offset))
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#define rtc2_read(offset) readw(rtc2_base + (offset))
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#define rtc2_write(offset, value) writew((value), rtc2_base + (offset))
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/* 32-bit compat for ioctls that nobody else uses */
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#define RTC_EPOCH_READ32 _IOR('p', 0x0d, __u32)
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static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */
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static DEFINE_SPINLOCK(rtc_lock);
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static char rtc_name[] = "RTC";
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static unsigned long periodic_count;
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static unsigned int alarm_enabled;
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static int aie_irq;
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static int pie_irq;
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static inline time64_t read_elapsed_second(void)
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{
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unsigned long first_low, first_mid, first_high;
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unsigned long second_low, second_mid, second_high;
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do {
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first_low = rtc1_read(ETIMELREG);
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first_mid = rtc1_read(ETIMEMREG);
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first_high = rtc1_read(ETIMEHREG);
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second_low = rtc1_read(ETIMELREG);
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second_mid = rtc1_read(ETIMEMREG);
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second_high = rtc1_read(ETIMEHREG);
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} while (first_low != second_low || first_mid != second_mid ||
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first_high != second_high);
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return ((u64)first_high << 17) | (first_mid << 1) | (first_low >> 15);
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}
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static inline void write_elapsed_second(time64_t sec)
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{
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spin_lock_irq(&rtc_lock);
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rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
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rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
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rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));
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spin_unlock_irq(&rtc_lock);
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}
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static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time)
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{
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time64_t epoch_sec, elapsed_sec;
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epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
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elapsed_sec = read_elapsed_second();
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rtc_time64_to_tm(epoch_sec + elapsed_sec, time);
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return 0;
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}
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static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time)
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{
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time64_t epoch_sec, current_sec;
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epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
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current_sec = rtc_tm_to_time64(time);
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write_elapsed_second(current_sec - epoch_sec);
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return 0;
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}
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static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
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{
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unsigned long low, mid, high;
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struct rtc_time *time = &wkalrm->time;
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spin_lock_irq(&rtc_lock);
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low = rtc1_read(ECMPLREG);
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mid = rtc1_read(ECMPMREG);
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high = rtc1_read(ECMPHREG);
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wkalrm->enabled = alarm_enabled;
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spin_unlock_irq(&rtc_lock);
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rtc_time64_to_tm((high << 17) | (mid << 1) | (low >> 15), time);
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return 0;
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}
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static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
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{
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time64_t alarm_sec;
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alarm_sec = rtc_tm_to_time64(&wkalrm->time);
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spin_lock_irq(&rtc_lock);
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if (alarm_enabled)
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disable_irq(aie_irq);
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rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
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rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
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rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
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if (wkalrm->enabled)
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enable_irq(aie_irq);
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alarm_enabled = wkalrm->enabled;
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spin_unlock_irq(&rtc_lock);
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return 0;
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}
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static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
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{
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switch (cmd) {
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case RTC_EPOCH_READ:
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return put_user(epoch, (unsigned long __user *)arg);
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#ifdef CONFIG_64BIT
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case RTC_EPOCH_READ32:
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return put_user(epoch, (unsigned int __user *)arg);
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#endif
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case RTC_EPOCH_SET:
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/* Doesn't support before 1900 */
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if (arg < 1900)
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return -EINVAL;
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epoch = arg;
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break;
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default:
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return -ENOIOCTLCMD;
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}
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return 0;
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}
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static int vr41xx_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
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{
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spin_lock_irq(&rtc_lock);
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if (enabled) {
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if (!alarm_enabled) {
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enable_irq(aie_irq);
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alarm_enabled = 1;
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}
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} else {
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if (alarm_enabled) {
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disable_irq(aie_irq);
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alarm_enabled = 0;
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}
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}
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spin_unlock_irq(&rtc_lock);
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return 0;
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}
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static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
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{
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struct platform_device *pdev = (struct platform_device *)dev_id;
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struct rtc_device *rtc = platform_get_drvdata(pdev);
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rtc2_write(RTCINTREG, ELAPSEDTIME_INT);
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rtc_update_irq(rtc, 1, RTC_AF);
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return IRQ_HANDLED;
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}
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static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
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{
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struct platform_device *pdev = (struct platform_device *)dev_id;
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struct rtc_device *rtc = platform_get_drvdata(pdev);
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unsigned long count = periodic_count;
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rtc2_write(RTCINTREG, RTCLONG1_INT);
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rtc1_write(RTCL1LREG, count);
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rtc1_write(RTCL1HREG, count >> 16);
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rtc_update_irq(rtc, 1, RTC_PF);
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return IRQ_HANDLED;
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}
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static const struct rtc_class_ops vr41xx_rtc_ops = {
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.ioctl = vr41xx_rtc_ioctl,
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.read_time = vr41xx_rtc_read_time,
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.set_time = vr41xx_rtc_set_time,
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.read_alarm = vr41xx_rtc_read_alarm,
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.set_alarm = vr41xx_rtc_set_alarm,
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.alarm_irq_enable = vr41xx_rtc_alarm_irq_enable,
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};
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static int rtc_probe(struct platform_device *pdev)
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{
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struct resource *res;
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struct rtc_device *rtc;
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int retval;
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if (pdev->num_resources != 4)
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return -EBUSY;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -EBUSY;
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rtc1_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
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if (!rtc1_base)
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return -EBUSY;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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if (!res) {
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retval = -EBUSY;
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goto err_rtc1_iounmap;
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}
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rtc2_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
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if (!rtc2_base) {
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retval = -EBUSY;
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goto err_rtc1_iounmap;
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}
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rtc = devm_rtc_allocate_device(&pdev->dev);
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if (IS_ERR(rtc)) {
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retval = PTR_ERR(rtc);
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goto err_iounmap_all;
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}
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rtc->ops = &vr41xx_rtc_ops;
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/* 48-bit counter at 32.768 kHz */
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rtc->range_max = (1ULL << 33) - 1;
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rtc->max_user_freq = MAX_PERIODIC_RATE;
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spin_lock_irq(&rtc_lock);
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rtc1_write(ECMPLREG, 0);
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rtc1_write(ECMPMREG, 0);
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rtc1_write(ECMPHREG, 0);
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rtc1_write(RTCL1LREG, 0);
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rtc1_write(RTCL1HREG, 0);
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spin_unlock_irq(&rtc_lock);
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aie_irq = platform_get_irq(pdev, 0);
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if (aie_irq <= 0) {
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retval = -EBUSY;
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goto err_iounmap_all;
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}
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retval = devm_request_irq(&pdev->dev, aie_irq, elapsedtime_interrupt, 0,
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"elapsed_time", pdev);
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if (retval < 0)
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goto err_iounmap_all;
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pie_irq = platform_get_irq(pdev, 1);
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if (pie_irq <= 0) {
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retval = -EBUSY;
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goto err_iounmap_all;
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}
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retval = devm_request_irq(&pdev->dev, pie_irq, rtclong1_interrupt, 0,
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"rtclong1", pdev);
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if (retval < 0)
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goto err_iounmap_all;
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platform_set_drvdata(pdev, rtc);
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disable_irq(aie_irq);
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disable_irq(pie_irq);
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dev_info(&pdev->dev, "Real Time Clock of NEC VR4100 series\n");
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retval = devm_rtc_register_device(rtc);
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if (retval)
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goto err_iounmap_all;
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return 0;
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err_iounmap_all:
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rtc2_base = NULL;
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err_rtc1_iounmap:
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rtc1_base = NULL;
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return retval;
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}
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/* work with hotplug and coldplug */
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MODULE_ALIAS("platform:RTC");
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static struct platform_driver rtc_platform_driver = {
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.probe = rtc_probe,
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.driver = {
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.name = rtc_name,
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},
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};
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module_platform_driver(rtc_platform_driver);
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