Merge tag 'dmaengine-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine
Pull dmaengine updates from Vinod Koul: "This time we have bunch of driver updates and some new device support. New support: - Document RZ/V2L and RZ/G2UL dma binding - TI AM62x k3-udma and k3-psil support Updates: - Yaml conversion for Mediatek uart apdma schema - Removal of DMA-32 fallback configuration for various drivers - imx-sdma updates for channel restart" * tag 'dmaengine-5.18-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine: (23 commits) dmaengine: hisi_dma: fix MSI allocate fail when reload hisi_dma dmaengine: dw-axi-dmac: cleanup comments dmaengine: fsl-dpaa2-qdma: Drop comma after SoC match table sentinel dt-bindings: dma: Convert mtk-uart-apdma to DT schema dmaengine: ppc4xx: Make use of the helper macro LIST_HEAD() dmaengine: idxd: Remove useless DMA-32 fallback configuration dmaengine: qcom_hidma: Remove useless DMA-32 fallback configuration dmaengine: sh: Kconfig: Add ARCH_R9A07G054 dependency for RZ_DMAC config option dmaengine: ti: k3-psil: Add AM62x PSIL and PDMA data dmaengine: ti: k3-udma: Add AM62x DMSS support dmaengine: ti: cleanup comments dmaengine: imx-sdma: clean up some inconsistent indenting dmaengine: Revert "dmaengine: shdma: Fix runtime PM imbalance on error" dmaengine: idxd: restore traffic class defaults after wq reset dmaengine: altera-msgdma: Remove useless DMA-32 fallback configuration dmaengine: stm32-dma: set dma_device max_sg_burst dmaengine: imx-sdma: fix cyclic buffer race condition dmaengine: imx-sdma: restart cyclic channel if needed dmaengine: iot: Remove useless DMA-32 fallback configuration dmaengine: ptdma: handle the cases based on DMA is complete ...
This commit is contained in:
Linus Torvalds
122
Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml
Normal file
122
Documentation/devicetree/bindings/dma/mediatek,uart-dma.yaml
Normal file
@@ -0,0 +1,122 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/dma/mediatek,uart-dma.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MediaTek UART APDMA controller
|
||||
|
||||
maintainers:
|
||||
- Long Cheng <long.cheng@mediatek.com>
|
||||
|
||||
description: |
|
||||
The MediaTek UART APDMA controller provides DMA capabilities
|
||||
for the UART peripheral bus.
|
||||
|
||||
allOf:
|
||||
- $ref: "dma-controller.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- items:
|
||||
- enum:
|
||||
- mediatek,mt2712-uart-dma
|
||||
- mediatek,mt8516-uart-dma
|
||||
- const: mediatek,mt6577-uart-dma
|
||||
- enum:
|
||||
- mediatek,mt6577-uart-dma
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 16
|
||||
|
||||
interrupts:
|
||||
description: |
|
||||
TX, RX interrupt lines for each UART APDMA channel
|
||||
minItems: 1
|
||||
maxItems: 16
|
||||
|
||||
clocks:
|
||||
description: Must contain one entry for the APDMA main clock
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: apdma
|
||||
|
||||
"#dma-cells":
|
||||
const: 1
|
||||
description: |
|
||||
The first cell specifies the UART APDMA channel number
|
||||
|
||||
dma-requests:
|
||||
description: |
|
||||
Number of virtual channels of the UART APDMA controller
|
||||
maximum: 16
|
||||
|
||||
mediatek,dma-33bits:
|
||||
type: boolean
|
||||
description: Enable 33-bits UART APDMA support
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
if:
|
||||
not:
|
||||
required:
|
||||
- dma-requests
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
maxItems: 8
|
||||
reg:
|
||||
maxItems: 8
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt2712-clk.h>
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
apdma: dma-controller@11000400 {
|
||||
compatible = "mediatek,mt2712-uart-dma",
|
||||
"mediatek,mt6577-uart-dma";
|
||||
reg = <0 0x11000400 0 0x80>,
|
||||
<0 0x11000480 0 0x80>,
|
||||
<0 0x11000500 0 0x80>,
|
||||
<0 0x11000580 0 0x80>,
|
||||
<0 0x11000600 0 0x80>,
|
||||
<0 0x11000680 0 0x80>,
|
||||
<0 0x11000700 0 0x80>,
|
||||
<0 0x11000780 0 0x80>,
|
||||
<0 0x11000800 0 0x80>,
|
||||
<0 0x11000880 0 0x80>,
|
||||
<0 0x11000900 0 0x80>,
|
||||
<0 0x11000980 0 0x80>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
|
||||
dma-requests = <12>;
|
||||
clocks = <&pericfg CLK_PERI_AP_DMA>;
|
||||
clock-names = "apdma";
|
||||
mediatek,dma-33bits;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@@ -1,56 +0,0 @@
|
||||
* Mediatek UART APDMA Controller
|
||||
|
||||
Required properties:
|
||||
- compatible should contain:
|
||||
* "mediatek,mt2712-uart-dma" for MT2712 compatible APDMA
|
||||
* "mediatek,mt6577-uart-dma" for MT6577 and all of the above
|
||||
* "mediatek,mt8516-uart-dma", "mediatek,mt6577" for MT8516 SoC
|
||||
|
||||
- reg: The base address of the APDMA register bank.
|
||||
|
||||
- interrupts: A single interrupt specifier.
|
||||
One interrupt per dma-requests, or 8 if no dma-requests property is present
|
||||
|
||||
- dma-requests: The number of DMA channels
|
||||
|
||||
- clocks : Must contain an entry for each entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: The APDMA clock for register accesses
|
||||
|
||||
- mediatek,dma-33bits: Present if the DMA requires support
|
||||
|
||||
Examples:
|
||||
|
||||
apdma: dma-controller@11000400 {
|
||||
compatible = "mediatek,mt2712-uart-dma",
|
||||
"mediatek,mt6577-uart-dma";
|
||||
reg = <0 0x11000400 0 0x80>,
|
||||
<0 0x11000480 0 0x80>,
|
||||
<0 0x11000500 0 0x80>,
|
||||
<0 0x11000580 0 0x80>,
|
||||
<0 0x11000600 0 0x80>,
|
||||
<0 0x11000680 0 0x80>,
|
||||
<0 0x11000700 0 0x80>,
|
||||
<0 0x11000780 0 0x80>,
|
||||
<0 0x11000800 0 0x80>,
|
||||
<0 0x11000880 0 0x80>,
|
||||
<0 0x11000900 0 0x80>,
|
||||
<0 0x11000980 0 0x80>;
|
||||
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>;
|
||||
dma-requests = <12>;
|
||||
clocks = <&pericfg CLK_PERI_AP_DMA>;
|
||||
clock-names = "apdma";
|
||||
mediatek,dma-33bits;
|
||||
#dma-cells = <1>;
|
||||
};
|
||||
@@ -4,7 +4,7 @@
|
||||
$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Renesas RZ/G2L DMA Controller
|
||||
title: Renesas RZ/{G2L,G2UL,V2L} DMA Controller
|
||||
|
||||
maintainers:
|
||||
- Biju Das <biju.das.jz@bp.renesas.com>
|
||||
@@ -16,7 +16,9 @@ properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- renesas,r9a07g043-dmac # RZ/G2UL
|
||||
- renesas,r9a07g044-dmac # RZ/G2{L,LC}
|
||||
- renesas,r9a07g054-dmac # RZ/V2L
|
||||
- const: renesas,rz-dmac
|
||||
|
||||
reg:
|
||||
|
||||
Reference in New Issue
Block a user