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drm/i915/psr: Re-org Activate after enable

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Let's move the activation calls together after enable is done.

No real functional change should be expected here. Just an attempt
to get it clear when we are really activating PSR after enabling it.

v2: Add braces on if/else because commit message there is too long
    as suggested by Jani.
v3: Rebased on top of commit d2419ffc10 ("drm/i915: Plumb
    crtc_state to PSR enable/disable")

Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170907230041.22978-9-rodrigo.vivi@intel.com
This commit is contained in:
Rodrigo Vivi 2017-09-07 16:00:38 -07:00
parent 196cebddde
commit 29d1efe070
1 changed files with 16 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
drivers/gpu/drm/i915/intel_psr.c
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@ -549,8 +549,6 @@ void intel_psr_enable(struct intel_dp *intel_dp,
hsw_psr_enable_source(intel_dp, crtc_state);
if (INTEL_GEN(dev_priv) >= 9)
intel_psr_activate(intel_dp);
} else {
vlv_psr_setup_vsc(intel_dp, crtc_state);
@ -560,20 +558,25 @@ void intel_psr_enable(struct intel_dp *intel_dp,
vlv_psr_enable_source(intel_dp, crtc_state);
}
/*
* FIXME: Activation should happen immediately since this function
* is just called after pipe is fully trained and enabled.
* However on every platform we face issues when first activation
* follows a modeset so quickly.
* - On VLV/CHV we get bank screen on first activation
* - On HSW/BDW we get a recoverable frozen screen until next
* exit-activate sequence.
*/
if (INTEL_GEN(dev_priv) < 9)
dev_priv->psr.enabled = intel_dp;
if (INTEL_GEN(dev_priv) >= 9) {
intel_psr_activate(intel_dp);
} else {
/*
* FIXME: Activation should happen immediately since this
* function is just called after pipe is fully trained and
* enabled.
* However on some platforms we face issues when first
* activation follows a modeset so quickly.
* - On VLV/CHV we get bank screen on first activation
* - On HSW/BDW we get a recoverable frozen screen until
* next exit-activate sequence.
*/
schedule_delayed_work(&dev_priv->psr.work,
msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
}
dev_priv->psr.enabled = intel_dp;
unlock:
mutex_unlock(&dev_priv->psr.lock);
}