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RISC-V: PolarFire SoC Device Tree Updates

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This add a device tree for Sundance Polarberry, along with various
cleanups to the PolarFire SOC device trees and bindings.

Link: https://lore.kernel.org/r/20220509142610.128590-1-conor.dooley@microchip.com

* 'riscv-pfsoc-dt' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/palmer/linux:
  riscv: dts: icicle: sort nodes alphabetically
  riscv: microchip: icicle: readability fixes
  riscv: dts: microchip: add the sundance polarberry
  dt-bindings: riscv: microchip: add polarberry compatible string
  dt-bindings: vendor-prefixes: add Sundance DSP
  riscv: dts: microchip: make the fabric dtsi board specific
  dt-bindings: riscv: microchip: document icicle reference design
  riscv: dts: microchip: remove soc vendor from filenames
  riscv: dts: microchip: move sysctrlr out of soc bus
  riscv: dts: microchip: remove icicle memory clocks
This commit is contained in:
Palmer Dabbelt 2022-06-01 18:34:02 -07:00
commit 2981deb83d
No known key found for this signature in database
GPG Key ID: 2E1319F35FBB1889
8 changed files with 198 additions and 76 deletions
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2
Documentation/devicetree/bindings/riscv/microchip.yaml
View File

@ -20,6 +20,8 @@ properties:
items:
- enum:
- microchip,mpfs-icicle-kit
- microchip,mpfs-icicle-reference-rtlv2203
- sundance,polarberry
- const: microchip,mpfs
additionalProperties: true

2
Documentation/devicetree/bindings/vendor-prefixes.yaml
View File

@ -1207,6 +1207,8 @@ patternProperties:
description: Summit microelectronics
"^sunchip,.*":
description: Shenzhen Sunchip Technology Co., Ltd
"^sundance,.*":
description: Sundance DSP Inc.
"^sunplus,.*":
description: Sunplus Technology Co., Ltd.
"^SUNW,.*":

3
arch/riscv/boot/dts/microchip/Makefile
View File

@ -1,3 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += microchip-mpfs-icicle-kit.dtb
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb
dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))

2
arch/riscv/boot/dts/microchip/microchip-mpfs-fabric.dtsi → arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi
View File

@ -2,6 +2,8 @@
/* Copyright (c) 2020-2021 Microchip Technology Inc */
/ {
compatible = "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpfs";
core_pwm0: pwm@41000000 {
compatible = "microchip,corepwm-rtl-v4";
reg = <0x0 0x41000000 0x0 0xF0>;

139
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dts → arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
View File

@ -3,7 +3,8 @@
/dts-v1/;
#include "microchip-mpfs.dtsi"
#include "mpfs.dtsi"
#include "mpfs-icicle-kit-fabric.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define RTCCLK_FREQ 1000000
@ -32,63 +33,29 @@
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x2e000000>;
clocks = <&clkcfg CLK_DDRC>;
status = "okay";
};
ddrc_cache_hi: memory@1000000000 {
device_type = "memory";
reg = <0x10 0x0 0x0 0x40000000>;
clocks = <&clkcfg CLK_DDRC>;
status = "okay";
};
};
&refclk {
clock-frequency = <125000000>;
};
&mmuart1 {
&core_pwm0 {
status = "okay";
};
&mmuart2 {
status = "okay";
};
&mmuart3 {
status = "okay";
};
&mmuart4 {
status = "okay";
};
&mmc {
status = "okay";
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-mmc-highspeed;
card-detect-delay = <200>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
};
&spi0 {
status = "okay";
};
&spi1 {
status = "okay";
};
&qspi {
&gpio2 {
interrupts = <53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>;
status = "okay";
};
@ -107,48 +74,57 @@
&mac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
status = "okay";
};
&mac1 {
status = "okay";
phy-mode = "sgmii";
phy-handle = <&phy1>;
status = "okay";
phy1: ethernet-phy@9 {
reg = <9>;
ti,fifo-depth = <0x1>;
};
phy0: ethernet-phy@8 {
reg = <8>;
ti,fifo-depth = <0x1>;
};
};
&gpio2 {
interrupts = <53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>;
status = "okay";
};
&rtc {
status = "okay";
};
&usb {
status = "okay";
dr_mode = "host";
};
&mbox {
status = "okay";
};
&syscontroller {
&mmc {
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-mmc-highspeed;
card-detect-delay = <200>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&mmuart1 {
status = "okay";
};
&mmuart2 {
status = "okay";
};
&mmuart3 {
status = "okay";
};
&mmuart4 {
status = "okay";
};
@ -156,6 +132,31 @@
status = "okay";
};
&core_pwm0 {
&qspi {
status = "okay";
};
&refclk {
clock-frequency = <125000000>;
};
&rtc {
status = "okay";
};
&spi0 {
status = "okay";
};
&spi1 {
status = "okay";
};
&syscontroller {
status = "okay";
};
&usb {
status = "okay";
dr_mode = "host";
};

16
arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi Normal file
View File

@ -0,0 +1,16 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2022 Microchip Technology Inc */
/ {
fabric_clk3: fabric-clk3 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <62500000>;
};
fabric_clk1: fabric-clk1 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <125000000>;
};
};

99
arch/riscv/boot/dts/microchip/mpfs-polarberry.dts Normal file
View File

@ -0,0 +1,99 @@
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2022 Microchip Technology Inc */
/dts-v1/;
#include "mpfs.dtsi"
#include "mpfs-polarberry-fabric.dtsi"
/* Clock frequency (in Hz) of the rtcclk */
#define MTIMER_FREQ 1000000
/ {
model = "Sundance PolarBerry";
compatible = "sundance,polarberry", "microchip,mpfs";
aliases {
ethernet0 = &mac1;
serial0 = &mmuart0;
};
chosen {
stdout-path = "serial0:115200n8";
};
cpus {
timebase-frequency = <MTIMER_FREQ>;
};
ddrc_cache_lo: memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x2e000000>;
};
ddrc_cache_hi: memory@1000000000 {
device_type = "memory";
reg = <0x10 0x00000000 0x0 0xC0000000>;
};
};
/*
* phy0 is connected to mac0, but the port itself is on the (optional) carrier
* board.
*/
&mac0 {
phy-mode = "sgmii";
phy-handle = <&phy0>;
status = "disabled";
};
&mac1 {
phy-mode = "sgmii";
phy-handle = <&phy1>;
status = "okay";
phy1: ethernet-phy@5 {
reg = <5>;
ti,fifo-depth = <0x01>;
};
phy0: ethernet-phy@4 {
reg = <4>;
ti,fifo-depth = <0x01>;
};
};
&mbox {
status = "okay";
};
&mmc {
bus-width = <4>;
disable-wp;
cap-sd-highspeed;
cap-mmc-highspeed;
card-detect-delay = <200>;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
status = "okay";
};
&mmuart0 {
status = "okay";
};
&refclk {
clock-frequency = <125000000>;
};
&rtc {
status = "okay";
};
&syscontroller {
status = "okay";
};

11
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi → arch/riscv/boot/dts/microchip/mpfs.dtsi
View File

@ -3,7 +3,6 @@
/dts-v1/;
#include "dt-bindings/clock/microchip,mpfs-clock.h"
#include "microchip-mpfs-fabric.dtsi"
/ {
#address-cells = <2>;
@ -146,6 +145,11 @@
#clock-cells = <0>;
};
syscontroller: syscontroller {
compatible = "microchip,mpfs-sys-controller";
mboxes = <&mbox 0>;
};
soc {
#address-cells = <2>;
#size-cells = <2>;
@ -446,10 +450,5 @@
#mbox-cells = <1>;
status = "disabled";
};
syscontroller: syscontroller {
compatible = "microchip,mpfs-sys-controller";
mboxes = <&mbox 0>;
};
};
};