Merge branch 'remotes/lorenzo/pci/dwc'
- Don't ioremap NULL when DT lacks ATU resource (Tim Harvey) - Drop redundant qcom-ep error message for platform_get_irq_byname() failure (Krzysztof Wilczyński) - Add i.MX8MM support (Richard Zhu) - Use DWC common ops instead of layerscape-specific link-up functions (Hou Zhiqiang) * remotes/lorenzo/pci/dwc: PCI: layerscape: Change to use the DWC common link-up check function PCI: imx: Add the imx8mm pcie support dt-bindings: imx6q-pcie: Add PHY phandles and name properties PCI: qcom-ep: Remove surplus dev_err() when using platform_get_irq_byname() PCI: dwc: Do not remap invalid res
This commit is contained in:
Bjorn Helgaas
commit
2948ce70e6
@ -127,6 +127,12 @@ properties:
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enum: [1, 2, 3, 4]
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default: 1
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phys:
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maxItems: 1
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phy-names:
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const: pcie-phy
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reset-gpio:
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description: Should specify the GPIO for controlling the PCI bus device
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reset signal. It's not polarity aware and defaults to active-low reset
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@ -29,6 +29,7 @@
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/reset.h>
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#include <linux/phy/phy.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_runtime.h>
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@ -49,6 +50,7 @@ enum imx6_pcie_variants {
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IMX6QP,
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IMX7D,
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IMX8MQ,
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IMX8MM,
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};
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#define IMX6_PCIE_FLAG_IMX6_PHY BIT(0)
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@ -88,6 +90,7 @@ struct imx6_pcie {
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struct device *pd_pcie;
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/* power domain for pcie phy */
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struct device *pd_pcie_phy;
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struct phy *phy;
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const struct imx6_pcie_drvdata *drvdata;
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};
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@ -372,6 +375,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
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case IMX7D:
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case IMX8MQ:
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reset_control_assert(imx6_pcie->pciephy_reset);
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fallthrough;
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case IMX8MM:
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reset_control_assert(imx6_pcie->apps_reset);
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break;
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case IMX6SX:
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@ -407,7 +412,8 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
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static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
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{
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WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ);
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WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ &&
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imx6_pcie->drvdata->variant != IMX8MM);
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return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
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}
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@ -446,6 +452,11 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
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break;
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case IMX7D:
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break;
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case IMX8MM:
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ret = clk_prepare_enable(imx6_pcie->pcie_aux);
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if (ret)
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dev_err(dev, "unable to enable pcie_aux clock\n");
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break;
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case IMX8MQ:
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ret = clk_prepare_enable(imx6_pcie->pcie_aux);
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if (ret) {
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@ -522,6 +533,14 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
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goto err_ref_clk;
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}
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switch (imx6_pcie->drvdata->variant) {
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case IMX8MM:
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if (phy_power_on(imx6_pcie->phy))
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dev_err(dev, "unable to power on PHY\n");
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break;
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default:
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break;
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}
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/* allow the clocks to stabilize */
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usleep_range(200, 500);
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@ -538,6 +557,10 @@ static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
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case IMX8MQ:
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reset_control_deassert(imx6_pcie->pciephy_reset);
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break;
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case IMX8MM:
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if (phy_init(imx6_pcie->phy))
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dev_err(dev, "waiting for phy ready timeout!\n");
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break;
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case IMX7D:
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reset_control_deassert(imx6_pcie->pciephy_reset);
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@ -614,6 +637,12 @@ static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
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static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
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{
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switch (imx6_pcie->drvdata->variant) {
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case IMX8MM:
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/*
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* The PHY initialization had been done in the PHY
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* driver, break here directly.
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*/
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break;
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case IMX8MQ:
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/*
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* TODO: Currently this code assumes external
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@ -753,6 +782,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
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break;
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case IMX7D:
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case IMX8MQ:
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case IMX8MM:
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reset_control_deassert(imx6_pcie->apps_reset);
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break;
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}
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@ -871,6 +901,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
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IMX6Q_GPR12_PCIE_CTL_2, 0);
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break;
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case IMX7D:
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case IMX8MM:
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reset_control_assert(imx6_pcie->apps_reset);
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break;
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default:
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@ -930,6 +961,7 @@ static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
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IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
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break;
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case IMX8MQ:
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case IMX8MM:
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clk_disable_unprepare(imx6_pcie->pcie_aux);
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break;
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default:
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@ -945,8 +977,16 @@ static int imx6_pcie_suspend_noirq(struct device *dev)
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return 0;
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imx6_pcie_pm_turnoff(imx6_pcie);
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imx6_pcie_clk_disable(imx6_pcie);
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imx6_pcie_ltssm_disable(dev);
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imx6_pcie_clk_disable(imx6_pcie);
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switch (imx6_pcie->drvdata->variant) {
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case IMX8MM:
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if (phy_power_off(imx6_pcie->phy))
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dev_err(dev, "unable to power off PHY\n");
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break;
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default:
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break;
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}
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return 0;
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}
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@ -1043,11 +1083,6 @@ static int imx6_pcie_probe(struct platform_device *pdev)
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}
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/* Fetch clocks */
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imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
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if (IS_ERR(imx6_pcie->pcie_phy))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy),
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"pcie_phy clock source missing or invalid\n");
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imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
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if (IS_ERR(imx6_pcie->pcie_bus))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus),
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@ -1089,10 +1124,35 @@ static int imx6_pcie_probe(struct platform_device *pdev)
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dev_err(dev, "Failed to get PCIE APPS reset control\n");
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return PTR_ERR(imx6_pcie->apps_reset);
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}
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break;
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case IMX8MM:
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imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
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if (IS_ERR(imx6_pcie->pcie_aux))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
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"pcie_aux clock source missing or invalid\n");
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imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
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"apps");
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if (IS_ERR(imx6_pcie->apps_reset))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->apps_reset),
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"failed to get pcie apps reset control\n");
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imx6_pcie->phy = devm_phy_get(dev, "pcie-phy");
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if (IS_ERR(imx6_pcie->phy))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->phy),
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"failed to get pcie phy\n");
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break;
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default:
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break;
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}
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/* Don't fetch the pcie_phy clock, if it has abstract PHY driver */
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if (imx6_pcie->phy == NULL) {
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imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
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if (IS_ERR(imx6_pcie->pcie_phy))
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return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy),
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"pcie_phy clock source missing or invalid\n");
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}
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/* Grab turnoff reset */
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imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
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@ -1202,6 +1262,10 @@ static const struct imx6_pcie_drvdata drvdata[] = {
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[IMX8MQ] = {
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.variant = IMX8MQ,
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},
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[IMX8MM] = {
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.variant = IMX8MM,
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.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
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},
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};
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static const struct of_device_id imx6_pcie_of_match[] = {
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@ -1209,7 +1273,8 @@ static const struct of_device_id imx6_pcie_of_match[] = {
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{ .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
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{ .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
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{ .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
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{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } ,
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{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
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{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
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{},
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};
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@ -3,6 +3,7 @@
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* PCIe host controller driver for Freescale Layerscape SoCs
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*
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* Copyright (C) 2014 Freescale Semiconductor.
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* Copyright 2021 NXP
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*
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* Author: Minghuan Lian <Minghuan.Lian@freescale.com>
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*/
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@ -22,12 +23,6 @@
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#include "pcie-designware.h"
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/* PEX1/2 Misc Ports Status Register */
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#define SCFG_PEXMSCPORTSR(pex_idx) (0x94 + (pex_idx) * 4)
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#define LTSSM_STATE_SHIFT 20
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#define LTSSM_STATE_MASK 0x3f
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#define LTSSM_PCIE_L0 0x11 /* L0 state */
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/* PEX Internal Configuration Registers */
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#define PCIE_STRFMR1 0x71c /* Symbol Timer & Filter Mask Register1 */
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#define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */
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@ -35,20 +30,8 @@
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#define PCIE_IATU_NUM 6
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struct ls_pcie_drvdata {
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u32 lut_offset;
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u32 ltssm_shift;
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u32 lut_dbg;
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const struct dw_pcie_host_ops *ops;
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const struct dw_pcie_ops *dw_pcie_ops;
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};
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struct ls_pcie {
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struct dw_pcie *pci;
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void __iomem *lut;
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struct regmap *scfg;
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const struct ls_pcie_drvdata *drvdata;
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int index;
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};
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#define to_ls_pcie(x) dev_get_drvdata((x)->dev)
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@ -83,38 +66,6 @@ static void ls_pcie_drop_msg_tlp(struct ls_pcie *pcie)
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iowrite32(val, pci->dbi_base + PCIE_STRFMR1);
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}
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static int ls1021_pcie_link_up(struct dw_pcie *pci)
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{
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u32 state;
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struct ls_pcie *pcie = to_ls_pcie(pci);
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if (!pcie->scfg)
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return 0;
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regmap_read(pcie->scfg, SCFG_PEXMSCPORTSR(pcie->index), &state);
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state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
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if (state < LTSSM_PCIE_L0)
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return 0;
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return 1;
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}
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static int ls_pcie_link_up(struct dw_pcie *pci)
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{
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struct ls_pcie *pcie = to_ls_pcie(pci);
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u32 state;
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state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >>
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pcie->drvdata->ltssm_shift) &
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LTSSM_STATE_MASK;
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if (state < LTSSM_PCIE_L0)
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return 0;
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return 1;
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}
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/* Forward error response of outbound non-posted requests */
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static void ls_pcie_fix_error_response(struct ls_pcie *pcie)
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{
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@ -139,96 +90,20 @@ static int ls_pcie_host_init(struct pcie_port *pp)
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return 0;
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}
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static int ls1021_pcie_host_init(struct pcie_port *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct ls_pcie *pcie = to_ls_pcie(pci);
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struct device *dev = pci->dev;
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u32 index[2];
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int ret;
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pcie->scfg = syscon_regmap_lookup_by_phandle(dev->of_node,
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"fsl,pcie-scfg");
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if (IS_ERR(pcie->scfg)) {
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ret = PTR_ERR(pcie->scfg);
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dev_err(dev, "No syscfg phandle specified\n");
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pcie->scfg = NULL;
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return ret;
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}
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if (of_property_read_u32_array(dev->of_node,
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"fsl,pcie-scfg", index, 2)) {
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pcie->scfg = NULL;
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return -EINVAL;
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}
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pcie->index = index[1];
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return ls_pcie_host_init(pp);
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}
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static const struct dw_pcie_host_ops ls1021_pcie_host_ops = {
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.host_init = ls1021_pcie_host_init,
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};
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static const struct dw_pcie_host_ops ls_pcie_host_ops = {
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.host_init = ls_pcie_host_init,
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};
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static const struct dw_pcie_ops dw_ls1021_pcie_ops = {
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.link_up = ls1021_pcie_link_up,
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};
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static const struct dw_pcie_ops dw_ls_pcie_ops = {
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.link_up = ls_pcie_link_up,
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};
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static const struct ls_pcie_drvdata ls1021_drvdata = {
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.ops = &ls1021_pcie_host_ops,
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.dw_pcie_ops = &dw_ls1021_pcie_ops,
|
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};
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static const struct ls_pcie_drvdata ls1043_drvdata = {
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.lut_offset = 0x10000,
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.ltssm_shift = 24,
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.lut_dbg = 0x7fc,
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.ops = &ls_pcie_host_ops,
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.dw_pcie_ops = &dw_ls_pcie_ops,
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};
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static const struct ls_pcie_drvdata ls1046_drvdata = {
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.lut_offset = 0x80000,
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.ltssm_shift = 24,
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.lut_dbg = 0x407fc,
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.ops = &ls_pcie_host_ops,
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.dw_pcie_ops = &dw_ls_pcie_ops,
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};
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static const struct ls_pcie_drvdata ls2080_drvdata = {
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.lut_offset = 0x80000,
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.ltssm_shift = 0,
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.lut_dbg = 0x7fc,
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.ops = &ls_pcie_host_ops,
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.dw_pcie_ops = &dw_ls_pcie_ops,
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};
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static const struct ls_pcie_drvdata ls2088_drvdata = {
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.lut_offset = 0x80000,
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.ltssm_shift = 0,
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.lut_dbg = 0x407fc,
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.ops = &ls_pcie_host_ops,
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.dw_pcie_ops = &dw_ls_pcie_ops,
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};
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|
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static const struct of_device_id ls_pcie_of_match[] = {
|
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{ .compatible = "fsl,ls1012a-pcie", .data = &ls1046_drvdata },
|
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{ .compatible = "fsl,ls1021a-pcie", .data = &ls1021_drvdata },
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{ .compatible = "fsl,ls1028a-pcie", .data = &ls2088_drvdata },
|
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{ .compatible = "fsl,ls1043a-pcie", .data = &ls1043_drvdata },
|
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{ .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata },
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{ .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata },
|
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{ .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata },
|
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{ .compatible = "fsl,ls2088a-pcie", .data = &ls2088_drvdata },
|
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{ .compatible = "fsl,ls1088a-pcie", .data = &ls2088_drvdata },
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{ .compatible = "fsl,ls1012a-pcie", },
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{ .compatible = "fsl,ls1021a-pcie", },
|
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{ .compatible = "fsl,ls1028a-pcie", },
|
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{ .compatible = "fsl,ls1043a-pcie", },
|
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{ .compatible = "fsl,ls1046a-pcie", },
|
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{ .compatible = "fsl,ls2080a-pcie", },
|
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{ .compatible = "fsl,ls2085a-pcie", },
|
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{ .compatible = "fsl,ls2088a-pcie", },
|
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{ .compatible = "fsl,ls1088a-pcie", },
|
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{ },
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};
|
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|
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@ -247,11 +122,8 @@ static int ls_pcie_probe(struct platform_device *pdev)
|
||||
if (!pci)
|
||||
return -ENOMEM;
|
||||
|
||||
pcie->drvdata = of_device_get_match_data(dev);
|
||||
|
||||
pci->dev = dev;
|
||||
pci->ops = pcie->drvdata->dw_pcie_ops;
|
||||
pci->pp.ops = pcie->drvdata->ops;
|
||||
pci->pp.ops = &ls_pcie_host_ops;
|
||||
|
||||
pcie->pci = pci;
|
||||
|
||||
@ -260,8 +132,6 @@ static int ls_pcie_probe(struct platform_device *pdev)
|
||||
if (IS_ERR(pci->dbi_base))
|
||||
return PTR_ERR(pci->dbi_base);
|
||||
|
||||
pcie->lut = pci->dbi_base + pcie->drvdata->lut_offset;
|
||||
|
||||
if (!ls_pcie_is_bridge(pcie))
|
||||
return -ENODEV;
|
||||
|
||||
|
||||
@ -672,10 +672,11 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci)
|
||||
if (!pci->atu_base) {
|
||||
struct resource *res =
|
||||
platform_get_resource_byname(pdev, IORESOURCE_MEM, "atu");
|
||||
if (res)
|
||||
if (res) {
|
||||
pci->atu_size = resource_size(res);
|
||||
pci->atu_base = devm_ioremap_resource(dev, res);
|
||||
if (IS_ERR(pci->atu_base))
|
||||
pci->atu_base = devm_ioremap_resource(dev, res);
|
||||
}
|
||||
if (!pci->atu_base || IS_ERR(pci->atu_base))
|
||||
pci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;
|
||||
}
|
||||
|
||||
|
||||
@ -552,10 +552,8 @@ static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev,
|
||||
int irq, ret;
|
||||
|
||||
irq = platform_get_irq_byname(pdev, "global");
|
||||
if (irq < 0) {
|
||||
dev_err(&pdev->dev, "Failed to get Global IRQ\n");
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
}
|
||||
|
||||
ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
|
||||
qcom_pcie_ep_global_irq_thread,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user