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apic: Move hypervisor detection of x2apic to hypervisor.h

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Then we can reuse it for Xen later.

Acked-by: Jeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com>
Acked-by: Avi Kivity <avi@redhat.com>
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Sheng Yang <sheng@linux.intel.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
This commit is contained in:
Sheng Yang 2010-12-21 14:18:48 +08:00 committed by Konrad Rzeszutek Wilk
parent cf7d7e5a19
commit 2904ed8dd5
2 changed files with 12 additions and 2 deletions
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9
arch/x86/include/asm/hypervisor.h
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@ -20,6 +20,8 @@
#ifndef _ASM_X86_HYPERVISOR_H #ifndef _ASM_X86_HYPERVISOR_H
#define _ASM_X86_HYPERVISOR_H #define _ASM_X86_HYPERVISOR_H
#include <asm/kvm_para.h>
extern void init_hypervisor(struct cpuinfo_x86 *c); extern void init_hypervisor(struct cpuinfo_x86 *c);
extern void init_hypervisor_platform(void); extern void init_hypervisor_platform(void);
@ -47,4 +49,11 @@ extern const struct hypervisor_x86 x86_hyper_vmware;
extern const struct hypervisor_x86 x86_hyper_ms_hyperv; extern const struct hypervisor_x86 x86_hyper_ms_hyperv;
extern const struct hypervisor_x86 x86_hyper_xen_hvm; extern const struct hypervisor_x86 x86_hyper_xen_hvm;
static inline bool hypervisor_x2apic_available(void)
{
if (kvm_para_available())
return true;
return false;
}
#endif #endif

5
arch/x86/kernel/apic/apic.c
View File

@ -50,8 +50,8 @@
#include <asm/mtrr.h> #include <asm/mtrr.h>
#include <asm/smp.h> #include <asm/smp.h>
#include <asm/mce.h> #include <asm/mce.h>
#include <asm/kvm_para.h>
#include <asm/tsc.h> #include <asm/tsc.h>
#include <asm/hypervisor.h>
unsigned int num_processors; unsigned int num_processors;
@ -1476,7 +1476,8 @@ void __init enable_IR_x2apic(void)
/* IR is required if there is APIC ID > 255 even when running /* IR is required if there is APIC ID > 255 even when running
* under KVM * under KVM
*/ */
if (max_physical_apicid > 255 || !kvm_para_available()) if (max_physical_apicid > 255 ||
!hypervisor_x2apic_available())
goto nox2apic; goto nox2apic;
/* /*
* without IR all CPUs can be addressed by IOAPIC/MSI * without IR all CPUs can be addressed by IOAPIC/MSI