forked from Minki/linux
Merge tag 'drm-intel-next-fixes-2016-10-11' of git://anongit.freedesktop.org/drm-intel into drm-next
A big bunch of i915 fixes for drm-next / v4.9 merge window, with more than half of them also cc: stable. We also continue to have more Fixes: annotations for our fixes, which should help the backporters and archeologists. * tag 'drm-intel-next-fixes-2016-10-11' of git://anongit.freedesktop.org/drm-intel: (27 commits) drm/i915: Fix conflict resolution from backmerge of v4.8-rc8 to drm-next drm/i915/guc: Unwind GuC workqueue reservation if request construction fails drm/i915: Reset the breadcrumbs IRQ more carefully drm/i915: Force relocations via cpu if we run out of idle aperture drm/i915: Distinguish last emitted request from last submitted request drm/i915: Allow DP to work w/o EDID drm/i915: Move long hpd handling into the hotplug work drm/i915/execlists: Reinitialise context image after GPU hang drm/i915: Use correct index for backtracking HUNG semaphores drm/i915: Unalias obj->phys_handle and obj->userptr drm/i915: Just clear the mmiodebug before a register access drm/i915/gen9: only add the planes actually affected by ddb changes drm/i915: Allow PCH DPLL sharing regardless of DPLL_SDVO_HIGH_SPEED drm/i915/bxt: Fix HDMI DPLL configuration drm/i915/gen9: fix the watermark res_blocks value drm/i915/gen9: fix plane_blocks_per_line on watermarks calculations drm/i915/gen9: minimum scanlines for Y tile is not always 4 drm/i915/gen9: fix the WaWmMemoryReadLatency implementation drm/i915/kbl: KBL also needs to run the SAGV code drm/i915: introduce intel_has_sagv() ...
This commit is contained in:
Dave Airlie
commit
28da9ed657
@ -1786,15 +1786,6 @@ void i915_reset(struct drm_i915_private *dev_priv)
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goto error;
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}
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/*
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* rps/rc6 re-init is necessary to restore state lost after the
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* reset and the re-install of gt irqs. Skip for ironlake per
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* previous concerns that it doesn't respond well to some forms
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* of re-init after reset.
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*/
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intel_sanitize_gt_powersave(dev_priv);
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intel_autoenable_gt_powersave(dev_priv);
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wakeup:
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wake_up_bit(&error->flags, I915_RESET_IN_PROGRESS);
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return;
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@ -1872,7 +1863,17 @@ static int i915_pm_resume(struct device *kdev)
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/* freeze: before creating the hibernation_image */
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static int i915_pm_freeze(struct device *kdev)
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{
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return i915_pm_suspend(kdev);
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int ret;
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ret = i915_pm_suspend(kdev);
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if (ret)
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return ret;
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ret = i915_gem_freeze(kdev_to_i915(kdev));
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if (ret)
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return ret;
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return 0;
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}
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static int i915_pm_freeze_late(struct device *kdev)
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@ -1984,11 +1984,11 @@ struct drm_i915_private {
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struct vlv_s0ix_state vlv_s0ix_state;
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enum {
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I915_SKL_SAGV_UNKNOWN = 0,
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I915_SKL_SAGV_DISABLED,
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I915_SKL_SAGV_ENABLED,
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I915_SKL_SAGV_NOT_CONTROLLED
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} skl_sagv_status;
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I915_SAGV_UNKNOWN = 0,
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I915_SAGV_DISABLED,
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I915_SAGV_ENABLED,
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I915_SAGV_NOT_CONTROLLED
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} sagv_status;
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struct {
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/*
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@ -2276,10 +2276,6 @@ struct drm_i915_gem_object {
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/** Record of address bit 17 of each page at last unbind. */
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unsigned long *bit_17;
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union {
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/** for phy allocated objects */
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struct drm_dma_handle *phys_handle;
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struct i915_gem_userptr {
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uintptr_t ptr;
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unsigned read_only :1;
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@ -2290,7 +2286,9 @@ struct drm_i915_gem_object {
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struct i915_mmu_object *mmu_object;
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struct work_struct *work;
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} userptr;
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};
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/** for phys allocated objects */
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struct drm_dma_handle *phys_handle;
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};
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static inline struct drm_i915_gem_object *
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@ -3076,6 +3074,7 @@ int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
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void i915_gem_load_init(struct drm_device *dev);
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void i915_gem_load_cleanup(struct drm_device *dev);
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void i915_gem_load_init_fences(struct drm_i915_private *dev_priv);
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int i915_gem_freeze(struct drm_i915_private *dev_priv);
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int i915_gem_freeze_late(struct drm_i915_private *dev_priv);
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void *i915_gem_object_alloc(struct drm_device *dev);
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@ -2616,8 +2616,6 @@ static void i915_gem_reset_engine(struct intel_engine_cs *engine)
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list_for_each_entry_continue(request, &engine->request_list, link)
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if (request->ctx == incomplete_ctx)
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reset_request(request);
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engine->i915->gt.active_engines &= ~intel_engine_flag(engine);
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}
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void i915_gem_reset(struct drm_i915_private *dev_priv)
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@ -2628,9 +2626,15 @@ void i915_gem_reset(struct drm_i915_private *dev_priv)
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for_each_engine(engine, dev_priv)
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i915_gem_reset_engine(engine);
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mod_delayed_work(dev_priv->wq, &dev_priv->gt.idle_work, 0);
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i915_gem_restore_fences(&dev_priv->drm);
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if (dev_priv->gt.awake) {
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intel_sanitize_gt_powersave(dev_priv);
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intel_enable_gt_powersave(dev_priv);
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if (INTEL_GEN(dev_priv) >= 6)
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gen6_rps_busy(dev_priv);
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}
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}
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static void nop_submit_request(struct drm_i915_gem_request *request)
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@ -4589,6 +4593,19 @@ void i915_gem_load_cleanup(struct drm_device *dev)
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rcu_barrier();
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}
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int i915_gem_freeze(struct drm_i915_private *dev_priv)
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{
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intel_runtime_pm_get(dev_priv);
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mutex_lock(&dev_priv->drm.struct_mutex);
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i915_gem_shrink_all(dev_priv);
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mutex_unlock(&dev_priv->drm.struct_mutex);
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intel_runtime_pm_put(dev_priv);
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return 0;
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}
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int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
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{
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struct drm_i915_gem_object *obj;
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@ -4612,7 +4629,8 @@ int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
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* the objects as well.
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*/
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i915_gem_shrink_all(dev_priv);
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mutex_lock(&dev_priv->drm.struct_mutex);
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i915_gem_shrink(dev_priv, -1UL, I915_SHRINK_UNBOUND);
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for (p = phases; *p; p++) {
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list_for_each_entry(obj, *p, global_list) {
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@ -4620,6 +4638,7 @@ int i915_gem_freeze_late(struct drm_i915_private *dev_priv)
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obj->base.write_domain = I915_GEM_DOMAIN_CPU;
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}
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}
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mutex_unlock(&dev_priv->drm.struct_mutex);
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return 0;
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}
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@ -451,8 +451,8 @@ static void *reloc_iomap(struct drm_i915_gem_object *obj,
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0, ggtt->mappable_end,
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DRM_MM_SEARCH_DEFAULT,
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DRM_MM_CREATE_DEFAULT);
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if (ret)
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return ERR_PTR(ret);
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if (ret) /* no inactive aperture space, use cpu reloc */
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return NULL;
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} else {
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ret = i915_vma_put_fence(vma);
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if (ret) {
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@ -328,6 +328,7 @@ submit_notify(struct i915_sw_fence *fence, enum i915_sw_fence_notify state)
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switch (state) {
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case FENCE_COMPLETE:
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request->engine->last_submitted_seqno = request->fence.seqno;
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request->engine->submit_request(request);
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break;
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@ -641,8 +642,8 @@ void __i915_add_request(struct drm_i915_gem_request *request, bool flush_caches)
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&request->submitq);
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request->emitted_jiffies = jiffies;
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request->previous_seqno = engine->last_submitted_seqno;
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engine->last_submitted_seqno = request->fence.seqno;
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request->previous_seqno = engine->last_pending_seqno;
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engine->last_pending_seqno = request->fence.seqno;
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i915_gem_active_set(&engine->last_request, request);
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list_add_tail(&request->link, &engine->request_list);
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list_add_tail(&request->ring_link, &ring->request_list);
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@ -451,6 +451,18 @@ int i915_guc_wq_reserve(struct drm_i915_gem_request *request)
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return ret;
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}
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void i915_guc_wq_unreserve(struct drm_i915_gem_request *request)
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{
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const size_t wqi_size = sizeof(struct guc_wq_item);
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struct i915_guc_client *gc = request->i915->guc.execbuf_client;
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GEM_BUG_ON(READ_ONCE(gc->wq_rsvd) < wqi_size);
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spin_lock(&gc->wq_lock);
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gc->wq_rsvd -= wqi_size;
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spin_unlock(&gc->wq_lock);
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}
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/* Construct a Work Item and append it to the GuC's Work Queue */
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static void guc_wq_item_append(struct i915_guc_client *gc,
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struct drm_i915_gem_request *rq)
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@ -350,6 +350,9 @@ void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv)
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void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv)
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{
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if (READ_ONCE(dev_priv->rps.interrupts_enabled))
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return;
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spin_lock_irq(&dev_priv->irq_lock);
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WARN_ON_ONCE(dev_priv->rps.pm_iir);
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WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
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@ -368,6 +371,9 @@ u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
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void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv)
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{
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if (!READ_ONCE(dev_priv->rps.interrupts_enabled))
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return;
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spin_lock_irq(&dev_priv->irq_lock);
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dev_priv->rps.interrupts_enabled = false;
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@ -2816,7 +2822,7 @@ semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
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if (engine == signaller)
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continue;
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if (offset == signaller->semaphore.signal_ggtt[engine->id])
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if (offset == signaller->semaphore.signal_ggtt[engine->hw_id])
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return signaller;
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}
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} else {
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@ -2826,13 +2832,13 @@ semaphore_wait_to_signaller_ring(struct intel_engine_cs *engine, u32 ipehr,
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if(engine == signaller)
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continue;
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if (sync_bits == signaller->semaphore.mbox.wait[engine->id])
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if (sync_bits == signaller->semaphore.mbox.wait[engine->hw_id])
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return signaller;
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}
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}
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DRM_DEBUG_DRIVER("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
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engine->id, ipehr, offset);
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DRM_DEBUG_DRIVER("No signaller ring found for %s, ipehr 0x%08x, offset 0x%016llx\n",
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engine->name, ipehr, offset);
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return ERR_PTR(-ENODEV);
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}
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@ -578,6 +578,36 @@ int intel_engine_init_breadcrumbs(struct intel_engine_cs *engine)
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return 0;
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}
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static void cancel_fake_irq(struct intel_engine_cs *engine)
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{
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struct intel_breadcrumbs *b = &engine->breadcrumbs;
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del_timer_sync(&b->hangcheck);
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del_timer_sync(&b->fake_irq);
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clear_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings);
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}
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void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine)
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{
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struct intel_breadcrumbs *b = &engine->breadcrumbs;
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cancel_fake_irq(engine);
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spin_lock(&b->lock);
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__intel_breadcrumbs_disable_irq(b);
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if (intel_engine_has_waiter(engine)) {
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b->timeout = wait_timeout();
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__intel_breadcrumbs_enable_irq(b);
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if (READ_ONCE(b->irq_posted))
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wake_up_process(b->first_wait->tsk);
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} else {
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/* sanitize the IMR and unmask any auxiliary interrupts */
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irq_disable(engine);
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}
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spin_unlock(&b->lock);
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}
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void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine)
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{
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struct intel_breadcrumbs *b = &engine->breadcrumbs;
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@ -585,8 +615,7 @@ void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine)
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if (!IS_ERR_OR_NULL(b->signaler))
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kthread_stop(b->signaler);
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del_timer_sync(&b->hangcheck);
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del_timer_sync(&b->fake_irq);
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cancel_fake_irq(engine);
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||||
}
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||||
unsigned int intel_kick_waiters(struct drm_i915_private *i915)
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||||
|
||||
@ -3408,6 +3408,8 @@ static void skylake_update_primary_plane(struct drm_plane *plane,
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dst_w--;
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||||
dst_h--;
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||||
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||||
intel_crtc->dspaddr_offset = surf_addr;
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||||
|
||||
intel_crtc->adjusted_x = src_x;
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||||
intel_crtc->adjusted_y = src_y;
|
||||
|
||||
@ -3629,6 +3631,7 @@ void intel_finish_reset(struct drm_i915_private *dev_priv)
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||||
intel_runtime_pm_disable_interrupts(dev_priv);
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||||
intel_runtime_pm_enable_interrupts(dev_priv);
|
||||
|
||||
intel_pps_unlock_regs_wa(dev_priv);
|
||||
intel_modeset_init_hw(dev);
|
||||
|
||||
spin_lock_irq(&dev_priv->irq_lock);
|
||||
@ -9509,6 +9512,24 @@ static void ironlake_compute_dpll(struct intel_crtc *intel_crtc,
|
||||
if (intel_crtc_has_dp_encoder(crtc_state))
|
||||
dpll |= DPLL_SDVO_HIGH_SPEED;
|
||||
|
||||
/*
|
||||
* The high speed IO clock is only really required for
|
||||
* SDVO/HDMI/DP, but we also enable it for CRT to make it
|
||||
* possible to share the DPLL between CRT and HDMI. Enabling
|
||||
* the clock needlessly does no real harm, except use up a
|
||||
* bit of power potentially.
|
||||
*
|
||||
* We'll limit this to IVB with 3 pipes, since it has only two
|
||||
* DPLLs and so DPLL sharing is the only way to get three pipes
|
||||
* driving PCH ports at the same time. On SNB we could do this,
|
||||
* and potentially avoid enabling the second DPLL, but it's not
|
||||
* clear if it''s a win or loss power wise. No point in doing
|
||||
* this on ILK at all since it has a fixed DPLL<->pipe mapping.
|
||||
*/
|
||||
if (INTEL_INFO(dev_priv)->num_pipes == 3 &&
|
||||
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
|
||||
dpll |= DPLL_SDVO_HIGH_SPEED;
|
||||
|
||||
/* compute bitmask from p1 value */
|
||||
dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
|
||||
/* also FPA1 */
|
||||
@ -14364,8 +14385,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
|
||||
* SKL workaround: bspec recommends we disable the SAGV when we
|
||||
* have more then one pipe enabled
|
||||
*/
|
||||
if (IS_SKYLAKE(dev_priv) && !skl_can_enable_sagv(state))
|
||||
skl_disable_sagv(dev_priv);
|
||||
if (!intel_can_enable_sagv(state))
|
||||
intel_disable_sagv(dev_priv);
|
||||
|
||||
intel_modeset_verify_disabled(dev);
|
||||
}
|
||||
@ -14422,9 +14443,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
|
||||
intel_modeset_verify_crtc(crtc, old_crtc_state, crtc->state);
|
||||
}
|
||||
|
||||
if (IS_SKYLAKE(dev_priv) && intel_state->modeset &&
|
||||
skl_can_enable_sagv(state))
|
||||
skl_enable_sagv(dev_priv);
|
||||
if (intel_state->modeset && intel_can_enable_sagv(state))
|
||||
intel_enable_sagv(dev_priv);
|
||||
|
||||
drm_atomic_helper_commit_hw_done(state);
|
||||
|
||||
|
||||
@ -4337,7 +4337,7 @@ intel_dp_unset_edid(struct intel_dp *intel_dp)
|
||||
intel_dp->has_audio = false;
|
||||
}
|
||||
|
||||
static void
|
||||
static enum drm_connector_status
|
||||
intel_dp_long_pulse(struct intel_connector *intel_connector)
|
||||
{
|
||||
struct drm_connector *connector = &intel_connector->base;
|
||||
@ -4361,7 +4361,7 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
|
||||
else
|
||||
status = connector_status_disconnected;
|
||||
|
||||
if (status != connector_status_connected) {
|
||||
if (status == connector_status_disconnected) {
|
||||
intel_dp->compliance_test_active = 0;
|
||||
intel_dp->compliance_test_type = 0;
|
||||
intel_dp->compliance_test_data = 0;
|
||||
@ -4423,7 +4423,7 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
|
||||
intel_dp->aux.i2c_defer_count = 0;
|
||||
|
||||
intel_dp_set_edid(intel_dp);
|
||||
|
||||
if (is_edp(intel_dp) || intel_connector->detect_edid)
|
||||
status = connector_status_connected;
|
||||
intel_dp->detect_done = true;
|
||||
|
||||
@ -4443,12 +4443,11 @@ intel_dp_long_pulse(struct intel_connector *intel_connector)
|
||||
}
|
||||
|
||||
out:
|
||||
if ((status != connector_status_connected) &&
|
||||
(intel_dp->is_mst == false))
|
||||
if (status != connector_status_connected && !intel_dp->is_mst)
|
||||
intel_dp_unset_edid(intel_dp);
|
||||
|
||||
intel_display_power_put(to_i915(dev), power_domain);
|
||||
return;
|
||||
return status;
|
||||
}
|
||||
|
||||
static enum drm_connector_status
|
||||
@ -4457,7 +4456,7 @@ intel_dp_detect(struct drm_connector *connector, bool force)
|
||||
struct intel_dp *intel_dp = intel_attached_dp(connector);
|
||||
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
||||
struct intel_encoder *intel_encoder = &intel_dig_port->base;
|
||||
struct intel_connector *intel_connector = to_intel_connector(connector);
|
||||
enum drm_connector_status status = connector->status;
|
||||
|
||||
DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
|
||||
connector->base.id, connector->name);
|
||||
@ -4472,14 +4471,11 @@ intel_dp_detect(struct drm_connector *connector, bool force)
|
||||
|
||||
/* If full detect is not performed yet, do a full detect */
|
||||
if (!intel_dp->detect_done)
|
||||
intel_dp_long_pulse(intel_dp->attached_connector);
|
||||
status = intel_dp_long_pulse(intel_dp->attached_connector);
|
||||
|
||||
intel_dp->detect_done = false;
|
||||
|
||||
if (is_edp(intel_dp) || intel_connector->detect_edid)
|
||||
return connector_status_connected;
|
||||
else
|
||||
return connector_status_disconnected;
|
||||
return status;
|
||||
}
|
||||
|
||||
static void
|
||||
@ -4831,16 +4827,14 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
|
||||
port_name(intel_dig_port->port),
|
||||
long_hpd ? "long" : "short");
|
||||
|
||||
if (long_hpd) {
|
||||
intel_dp->detect_done = false;
|
||||
return IRQ_NONE;
|
||||
}
|
||||
|
||||
power_domain = intel_display_port_aux_power_domain(intel_encoder);
|
||||
intel_display_power_get(dev_priv, power_domain);
|
||||
|
||||
if (long_hpd) {
|
||||
intel_dp_long_pulse(intel_dp->attached_connector);
|
||||
if (intel_dp->is_mst)
|
||||
ret = IRQ_HANDLED;
|
||||
goto put_power;
|
||||
|
||||
} else {
|
||||
if (intel_dp->is_mst) {
|
||||
if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
|
||||
/*
|
||||
@ -4852,17 +4846,17 @@ intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
|
||||
intel_dp->is_mst = false;
|
||||
drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
|
||||
intel_dp->is_mst);
|
||||
intel_dp->detect_done = false;
|
||||
goto put_power;
|
||||
}
|
||||
}
|
||||
|
||||
if (!intel_dp->is_mst) {
|
||||
if (!intel_dp_short_pulse(intel_dp)) {
|
||||
intel_dp_long_pulse(intel_dp->attached_connector);
|
||||
intel_dp->detect_done = false;
|
||||
goto put_power;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
ret = IRQ_HANDLED;
|
||||
|
||||
|
||||
@ -1694,21 +1694,32 @@ bool bxt_ddi_dp_set_dpll_hw_state(int clock,
|
||||
return bxt_ddi_set_dpll_hw_state(clock, &clk_div, dpll_hw_state);
|
||||
}
|
||||
|
||||
static bool
|
||||
bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc *intel_crtc,
|
||||
struct intel_crtc_state *crtc_state, int clock,
|
||||
struct intel_dpll_hw_state *dpll_hw_state)
|
||||
{
|
||||
struct bxt_clk_div clk_div = { };
|
||||
|
||||
bxt_ddi_hdmi_pll_dividers(intel_crtc, crtc_state, clock, &clk_div);
|
||||
|
||||
return bxt_ddi_set_dpll_hw_state(clock, &clk_div, dpll_hw_state);
|
||||
}
|
||||
|
||||
static struct intel_shared_dpll *
|
||||
bxt_get_dpll(struct intel_crtc *crtc,
|
||||
struct intel_crtc_state *crtc_state,
|
||||
struct intel_encoder *encoder)
|
||||
{
|
||||
struct bxt_clk_div clk_div = {0};
|
||||
struct intel_dpll_hw_state dpll_hw_state = {0};
|
||||
struct intel_dpll_hw_state dpll_hw_state = { };
|
||||
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
|
||||
struct intel_digital_port *intel_dig_port;
|
||||
struct intel_shared_dpll *pll;
|
||||
int i, clock = crtc_state->port_clock;
|
||||
|
||||
if (encoder->type == INTEL_OUTPUT_HDMI
|
||||
&& !bxt_ddi_hdmi_pll_dividers(crtc, crtc_state,
|
||||
clock, &clk_div))
|
||||
if (encoder->type == INTEL_OUTPUT_HDMI &&
|
||||
!bxt_ddi_hdmi_set_dpll_hw_state(crtc, crtc_state, clock,
|
||||
&dpll_hw_state))
|
||||
return NULL;
|
||||
|
||||
if ((encoder->type == INTEL_OUTPUT_DP ||
|
||||
|
||||
@ -263,6 +263,7 @@ struct intel_panel {
|
||||
bool enabled;
|
||||
bool combination_mode; /* gen 2/4 only */
|
||||
bool active_low_pwm;
|
||||
bool alternate_pwm_increment; /* lpt+ */
|
||||
|
||||
/* PWM chip */
|
||||
bool util_pin_active_low; /* bxt+ */
|
||||
@ -1741,9 +1742,9 @@ void ilk_wm_get_hw_state(struct drm_device *dev);
|
||||
void skl_wm_get_hw_state(struct drm_device *dev);
|
||||
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
|
||||
struct skl_ddb_allocation *ddb /* out */);
|
||||
bool skl_can_enable_sagv(struct drm_atomic_state *state);
|
||||
int skl_enable_sagv(struct drm_i915_private *dev_priv);
|
||||
int skl_disable_sagv(struct drm_i915_private *dev_priv);
|
||||
bool intel_can_enable_sagv(struct drm_atomic_state *state);
|
||||
int intel_enable_sagv(struct drm_i915_private *dev_priv);
|
||||
int intel_disable_sagv(struct drm_i915_private *dev_priv);
|
||||
bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
|
||||
const struct skl_ddb_allocation *new,
|
||||
enum pipe pipe);
|
||||
|
||||
@ -210,9 +210,6 @@ void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno)
|
||||
void intel_engine_init_hangcheck(struct intel_engine_cs *engine)
|
||||
{
|
||||
memset(&engine->hangcheck, 0, sizeof(engine->hangcheck));
|
||||
clear_bit(engine->id, &engine->i915->gpu_error.missed_irq_rings);
|
||||
if (intel_engine_has_waiter(engine))
|
||||
i915_queue_hangcheck(engine->i915);
|
||||
}
|
||||
|
||||
static void intel_engine_init_requests(struct intel_engine_cs *engine)
|
||||
@ -307,18 +304,6 @@ int intel_engine_init_common(struct intel_engine_cs *engine)
|
||||
return 0;
|
||||
}
|
||||
|
||||
void intel_engine_reset_irq(struct intel_engine_cs *engine)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = engine->i915;
|
||||
|
||||
spin_lock_irq(&dev_priv->irq_lock);
|
||||
if (intel_engine_has_waiter(engine))
|
||||
engine->irq_enable(engine);
|
||||
else
|
||||
engine->irq_disable(engine);
|
||||
spin_unlock_irq(&dev_priv->irq_lock);
|
||||
}
|
||||
|
||||
/**
|
||||
* intel_engines_cleanup_common - cleans up the engine state created by
|
||||
* the common initiailizers.
|
||||
|
||||
@ -160,6 +160,7 @@ extern int intel_guc_resume(struct drm_device *dev);
|
||||
int i915_guc_submission_init(struct drm_i915_private *dev_priv);
|
||||
int i915_guc_submission_enable(struct drm_i915_private *dev_priv);
|
||||
int i915_guc_wq_reserve(struct drm_i915_gem_request *rq);
|
||||
void i915_guc_wq_unreserve(struct drm_i915_gem_request *request);
|
||||
void i915_guc_submission_disable(struct drm_i915_private *dev_priv);
|
||||
void i915_guc_submission_fini(struct drm_i915_private *dev_priv);
|
||||
|
||||
|
||||
@ -226,10 +226,16 @@ enum {
|
||||
/* Typical size of the average request (2 pipecontrols and a MI_BB) */
|
||||
#define EXECLISTS_REQUEST_SIZE 64 /* bytes */
|
||||
|
||||
#define WA_TAIL_DWORDS 2
|
||||
|
||||
static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
|
||||
struct intel_engine_cs *engine);
|
||||
static int intel_lr_context_pin(struct i915_gem_context *ctx,
|
||||
struct intel_engine_cs *engine);
|
||||
static void execlists_init_reg_state(u32 *reg_state,
|
||||
struct i915_gem_context *ctx,
|
||||
struct intel_engine_cs *engine,
|
||||
struct intel_ring *ring);
|
||||
|
||||
/**
|
||||
* intel_sanitize_enable_execlists() - sanitize i915.enable_execlists
|
||||
@ -621,6 +627,10 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
|
||||
|
||||
request->ring = ce->ring;
|
||||
|
||||
ret = intel_lr_context_pin(request->ctx, engine);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (i915.enable_guc_submission) {
|
||||
/*
|
||||
* Check that the GuC has space for the request before
|
||||
@ -629,21 +639,17 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
|
||||
*/
|
||||
ret = i915_guc_wq_reserve(request);
|
||||
if (ret)
|
||||
return ret;
|
||||
goto err_unpin;
|
||||
}
|
||||
|
||||
ret = intel_lr_context_pin(request->ctx, engine);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = intel_ring_begin(request, 0);
|
||||
if (ret)
|
||||
goto err_unpin;
|
||||
goto err_unreserve;
|
||||
|
||||
if (!ce->initialised) {
|
||||
ret = engine->init_context(request);
|
||||
if (ret)
|
||||
goto err_unpin;
|
||||
goto err_unreserve;
|
||||
|
||||
ce->initialised = true;
|
||||
}
|
||||
@ -658,6 +664,9 @@ int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request
|
||||
request->reserved_space -= EXECLISTS_REQUEST_SIZE;
|
||||
return 0;
|
||||
|
||||
err_unreserve:
|
||||
if (i915.enable_guc_submission)
|
||||
i915_guc_wq_unreserve(request);
|
||||
err_unpin:
|
||||
intel_lr_context_unpin(request->ctx, engine);
|
||||
return ret;
|
||||
@ -708,7 +717,6 @@ static int intel_lr_context_pin(struct i915_gem_context *ctx,
|
||||
{
|
||||
struct intel_context *ce = &ctx->engine[engine->id];
|
||||
void *vaddr;
|
||||
u32 *lrc_reg_state;
|
||||
int ret;
|
||||
|
||||
lockdep_assert_held(&ctx->i915->drm.struct_mutex);
|
||||
@ -727,17 +735,16 @@ static int intel_lr_context_pin(struct i915_gem_context *ctx,
|
||||
goto unpin_vma;
|
||||
}
|
||||
|
||||
lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
|
||||
|
||||
ret = intel_ring_pin(ce->ring);
|
||||
if (ret)
|
||||
goto unpin_map;
|
||||
|
||||
intel_lr_context_descriptor_update(ctx, engine);
|
||||
|
||||
lrc_reg_state[CTX_RING_BUFFER_START+1] =
|
||||
ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
|
||||
ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
|
||||
i915_ggtt_offset(ce->ring->vma);
|
||||
ce->lrc_reg_state = lrc_reg_state;
|
||||
|
||||
ce->state->obj->dirty = true;
|
||||
|
||||
/* Invalidate GuC TLB. */
|
||||
@ -1231,7 +1238,7 @@ static int gen8_init_common_ring(struct intel_engine_cs *engine)
|
||||
|
||||
lrc_init_hws(engine);
|
||||
|
||||
intel_engine_reset_irq(engine);
|
||||
intel_engine_reset_breadcrumbs(engine);
|
||||
|
||||
I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
|
||||
|
||||
@ -1289,8 +1296,21 @@ static void reset_common_ring(struct intel_engine_cs *engine,
|
||||
struct execlist_port *port = engine->execlist_port;
|
||||
struct intel_context *ce = &request->ctx->engine[engine->id];
|
||||
|
||||
/* We want a simple context + ring to execute the breadcrumb update.
|
||||
* We cannot rely on the context being intact across the GPU hang,
|
||||
* so clear it and rebuild just what we need for the breadcrumb.
|
||||
* All pending requests for this context will be zapped, and any
|
||||
* future request will be after userspace has had the opportunity
|
||||
* to recreate its own state.
|
||||
*/
|
||||
execlists_init_reg_state(ce->lrc_reg_state,
|
||||
request->ctx, engine, ce->ring);
|
||||
|
||||
/* Move the RING_HEAD onto the breadcrumb, past the hanging batch */
|
||||
ce->lrc_reg_state[CTX_RING_BUFFER_START+1] =
|
||||
i915_ggtt_offset(ce->ring->vma);
|
||||
ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix;
|
||||
|
||||
request->ring->head = request->postfix;
|
||||
request->ring->last_retired_head = -1;
|
||||
intel_ring_update_space(request->ring);
|
||||
@ -1310,6 +1330,9 @@ static void reset_common_ring(struct intel_engine_cs *engine,
|
||||
GEM_BUG_ON(request->ctx != port[0].request->ctx);
|
||||
port[0].count = 0;
|
||||
port[1].count = 0;
|
||||
|
||||
/* Reset WaIdleLiteRestore:bdw,skl as well */
|
||||
request->tail = request->wa_tail - WA_TAIL_DWORDS * sizeof(u32);
|
||||
}
|
||||
|
||||
static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req)
|
||||
@ -1547,7 +1570,6 @@ static void bxt_a_seqno_barrier(struct intel_engine_cs *engine)
|
||||
* used as a workaround for not being allowed to do lite
|
||||
* restore with HEAD==TAIL (WaIdleLiteRestore).
|
||||
*/
|
||||
#define WA_TAIL_DWORDS 2
|
||||
|
||||
static int gen8_emit_request(struct drm_i915_gem_request *request)
|
||||
{
|
||||
@ -1894,38 +1916,13 @@ static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine)
|
||||
return indirect_ctx_offset;
|
||||
}
|
||||
|
||||
static int
|
||||
populate_lr_context(struct i915_gem_context *ctx,
|
||||
struct drm_i915_gem_object *ctx_obj,
|
||||
static void execlists_init_reg_state(u32 *reg_state,
|
||||
struct i915_gem_context *ctx,
|
||||
struct intel_engine_cs *engine,
|
||||
struct intel_ring *ring)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = ctx->i915;
|
||||
struct i915_hw_ppgtt *ppgtt = ctx->ppgtt;
|
||||
void *vaddr;
|
||||
u32 *reg_state;
|
||||
int ret;
|
||||
|
||||
if (!ppgtt)
|
||||
ppgtt = dev_priv->mm.aliasing_ppgtt;
|
||||
|
||||
ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
|
||||
if (ret) {
|
||||
DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
|
||||
if (IS_ERR(vaddr)) {
|
||||
ret = PTR_ERR(vaddr);
|
||||
DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
ctx_obj->dirty = true;
|
||||
|
||||
/* The second page of the context object contains some fields which must
|
||||
* be set up prior to the first execution. */
|
||||
reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
|
||||
struct drm_i915_private *dev_priv = engine->i915;
|
||||
struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt;
|
||||
|
||||
/* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM
|
||||
* commands followed by (reg, value) pairs. The values we are setting here are
|
||||
@ -1944,9 +1941,6 @@ populate_lr_context(struct i915_gem_context *ctx,
|
||||
0);
|
||||
ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base),
|
||||
0);
|
||||
/* Ring buffer start address is not known until the buffer is pinned.
|
||||
* It is written to the context image in execlists_update_context()
|
||||
*/
|
||||
ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START,
|
||||
RING_START(engine->mmio_base), 0);
|
||||
ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL,
|
||||
@ -2029,6 +2023,36 @@ populate_lr_context(struct i915_gem_context *ctx,
|
||||
ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE,
|
||||
make_rpcs(dev_priv));
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
populate_lr_context(struct i915_gem_context *ctx,
|
||||
struct drm_i915_gem_object *ctx_obj,
|
||||
struct intel_engine_cs *engine,
|
||||
struct intel_ring *ring)
|
||||
{
|
||||
void *vaddr;
|
||||
int ret;
|
||||
|
||||
ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true);
|
||||
if (ret) {
|
||||
DRM_DEBUG_DRIVER("Could not set to CPU domain\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
|
||||
if (IS_ERR(vaddr)) {
|
||||
ret = PTR_ERR(vaddr);
|
||||
DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
|
||||
return ret;
|
||||
}
|
||||
ctx_obj->dirty = true;
|
||||
|
||||
/* The second page of the context object contains some fields which must
|
||||
* be set up prior to the first execution. */
|
||||
|
||||
execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE,
|
||||
ctx, engine, ring);
|
||||
|
||||
i915_gem_object_unpin_map(ctx_obj);
|
||||
|
||||
|
||||
@ -841,7 +841,7 @@ static void lpt_enable_backlight(struct intel_connector *connector)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
|
||||
struct intel_panel *panel = &connector->panel;
|
||||
u32 pch_ctl1, pch_ctl2;
|
||||
u32 pch_ctl1, pch_ctl2, schicken;
|
||||
|
||||
pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
|
||||
if (pch_ctl1 & BLM_PCH_PWM_ENABLE) {
|
||||
@ -850,6 +850,22 @@ static void lpt_enable_backlight(struct intel_connector *connector)
|
||||
I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
|
||||
}
|
||||
|
||||
if (HAS_PCH_LPT(dev_priv)) {
|
||||
schicken = I915_READ(SOUTH_CHICKEN2);
|
||||
if (panel->backlight.alternate_pwm_increment)
|
||||
schicken |= LPT_PWM_GRANULARITY;
|
||||
else
|
||||
schicken &= ~LPT_PWM_GRANULARITY;
|
||||
I915_WRITE(SOUTH_CHICKEN2, schicken);
|
||||
} else {
|
||||
schicken = I915_READ(SOUTH_CHICKEN1);
|
||||
if (panel->backlight.alternate_pwm_increment)
|
||||
schicken |= SPT_PWM_GRANULARITY;
|
||||
else
|
||||
schicken &= ~SPT_PWM_GRANULARITY;
|
||||
I915_WRITE(SOUTH_CHICKEN1, schicken);
|
||||
}
|
||||
|
||||
pch_ctl2 = panel->backlight.max << 16;
|
||||
I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2);
|
||||
|
||||
@ -1242,10 +1258,10 @@ static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
|
||||
*/
|
||||
static u32 spt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
|
||||
struct intel_panel *panel = &connector->panel;
|
||||
u32 mul;
|
||||
|
||||
if (I915_READ(SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY)
|
||||
if (panel->backlight.alternate_pwm_increment)
|
||||
mul = 128;
|
||||
else
|
||||
mul = 16;
|
||||
@ -1261,9 +1277,10 @@ static u32 spt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
|
||||
static u32 lpt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
|
||||
{
|
||||
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
|
||||
struct intel_panel *panel = &connector->panel;
|
||||
u32 mul, clock;
|
||||
|
||||
if (I915_READ(SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY)
|
||||
if (panel->backlight.alternate_pwm_increment)
|
||||
mul = 16;
|
||||
else
|
||||
mul = 128;
|
||||
@ -1414,6 +1431,13 @@ static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unus
|
||||
struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
|
||||
struct intel_panel *panel = &connector->panel;
|
||||
u32 pch_ctl1, pch_ctl2, val;
|
||||
bool alt;
|
||||
|
||||
if (HAS_PCH_LPT(dev_priv))
|
||||
alt = I915_READ(SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY;
|
||||
else
|
||||
alt = I915_READ(SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY;
|
||||
panel->backlight.alternate_pwm_increment = alt;
|
||||
|
||||
pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
|
||||
panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY;
|
||||
|
||||
@ -2126,33 +2126,35 @@ static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
|
||||
wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
|
||||
GEN9_MEM_LATENCY_LEVEL_MASK;
|
||||
|
||||
/*
|
||||
* If a level n (n > 1) has a 0us latency, all levels m (m >= n)
|
||||
* need to be disabled. We make sure to sanitize the values out
|
||||
* of the punit to satisfy this requirement.
|
||||
*/
|
||||
for (level = 1; level <= max_level; level++) {
|
||||
if (wm[level] == 0) {
|
||||
for (i = level + 1; i <= max_level; i++)
|
||||
wm[i] = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* WaWmMemoryReadLatency:skl
|
||||
*
|
||||
* punit doesn't take into account the read latency so we need
|
||||
* to add 2us to the various latency levels we retrieve from
|
||||
* the punit.
|
||||
* - W0 is a bit special in that it's the only level that
|
||||
* can't be disabled if we want to have display working, so
|
||||
* we always add 2us there.
|
||||
* - For levels >=1, punit returns 0us latency when they are
|
||||
* disabled, so we respect that and don't add 2us then
|
||||
*
|
||||
* Additionally, if a level n (n > 1) has a 0us latency, all
|
||||
* levels m (m >= n) need to be disabled. We make sure to
|
||||
* sanitize the values out of the punit to satisfy this
|
||||
* requirement.
|
||||
* to add 2us to the various latency levels we retrieve from the
|
||||
* punit when level 0 response data us 0us.
|
||||
*/
|
||||
if (wm[0] == 0) {
|
||||
wm[0] += 2;
|
||||
for (level = 1; level <= max_level; level++)
|
||||
if (wm[level] != 0)
|
||||
wm[level] += 2;
|
||||
else {
|
||||
for (i = level + 1; i <= max_level; i++)
|
||||
wm[i] = 0;
|
||||
|
||||
for (level = 1; level <= max_level; level++) {
|
||||
if (wm[level] == 0)
|
||||
break;
|
||||
wm[level] += 2;
|
||||
}
|
||||
}
|
||||
|
||||
} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
|
||||
uint64_t sskpd = I915_READ64(MCH_SSKPD);
|
||||
|
||||
@ -2877,6 +2879,19 @@ skl_wm_plane_id(const struct intel_plane *plane)
|
||||
}
|
||||
}
|
||||
|
||||
static bool
|
||||
intel_has_sagv(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
if (IS_KABYLAKE(dev_priv))
|
||||
return true;
|
||||
|
||||
if (IS_SKYLAKE(dev_priv) &&
|
||||
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
|
||||
return true;
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
/*
|
||||
* SAGV dynamically adjusts the system agent voltage and clock frequencies
|
||||
* depending on power and performance requirements. The display engine access
|
||||
@ -2889,12 +2904,14 @@ skl_wm_plane_id(const struct intel_plane *plane)
|
||||
* - We're not using an interlaced display configuration
|
||||
*/
|
||||
int
|
||||
skl_enable_sagv(struct drm_i915_private *dev_priv)
|
||||
intel_enable_sagv(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (dev_priv->skl_sagv_status == I915_SKL_SAGV_NOT_CONTROLLED ||
|
||||
dev_priv->skl_sagv_status == I915_SKL_SAGV_ENABLED)
|
||||
if (!intel_has_sagv(dev_priv))
|
||||
return 0;
|
||||
|
||||
if (dev_priv->sagv_status == I915_SAGV_ENABLED)
|
||||
return 0;
|
||||
|
||||
DRM_DEBUG_KMS("Enabling the SAGV\n");
|
||||
@ -2910,21 +2927,21 @@ skl_enable_sagv(struct drm_i915_private *dev_priv)
|
||||
* Some skl systems, pre-release machines in particular,
|
||||
* don't actually have an SAGV.
|
||||
*/
|
||||
if (ret == -ENXIO) {
|
||||
if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
|
||||
DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
|
||||
dev_priv->skl_sagv_status = I915_SKL_SAGV_NOT_CONTROLLED;
|
||||
dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
|
||||
return 0;
|
||||
} else if (ret < 0) {
|
||||
DRM_ERROR("Failed to enable the SAGV\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_priv->skl_sagv_status = I915_SKL_SAGV_ENABLED;
|
||||
dev_priv->sagv_status = I915_SAGV_ENABLED;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
skl_do_sagv_disable(struct drm_i915_private *dev_priv)
|
||||
intel_do_sagv_disable(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
int ret;
|
||||
uint32_t temp = GEN9_SAGV_DISABLE;
|
||||
@ -2938,19 +2955,21 @@ skl_do_sagv_disable(struct drm_i915_private *dev_priv)
|
||||
}
|
||||
|
||||
int
|
||||
skl_disable_sagv(struct drm_i915_private *dev_priv)
|
||||
intel_disable_sagv(struct drm_i915_private *dev_priv)
|
||||
{
|
||||
int ret, result;
|
||||
|
||||
if (dev_priv->skl_sagv_status == I915_SKL_SAGV_NOT_CONTROLLED ||
|
||||
dev_priv->skl_sagv_status == I915_SKL_SAGV_DISABLED)
|
||||
if (!intel_has_sagv(dev_priv))
|
||||
return 0;
|
||||
|
||||
if (dev_priv->sagv_status == I915_SAGV_DISABLED)
|
||||
return 0;
|
||||
|
||||
DRM_DEBUG_KMS("Disabling the SAGV\n");
|
||||
mutex_lock(&dev_priv->rps.hw_lock);
|
||||
|
||||
/* bspec says to keep retrying for at least 1 ms */
|
||||
ret = wait_for(result = skl_do_sagv_disable(dev_priv), 1);
|
||||
ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
|
||||
mutex_unlock(&dev_priv->rps.hw_lock);
|
||||
|
||||
if (ret == -ETIMEDOUT) {
|
||||
@ -2962,20 +2981,20 @@ skl_disable_sagv(struct drm_i915_private *dev_priv)
|
||||
* Some skl systems, pre-release machines in particular,
|
||||
* don't actually have an SAGV.
|
||||
*/
|
||||
if (result == -ENXIO) {
|
||||
if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
|
||||
DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
|
||||
dev_priv->skl_sagv_status = I915_SKL_SAGV_NOT_CONTROLLED;
|
||||
dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
|
||||
return 0;
|
||||
} else if (result < 0) {
|
||||
DRM_ERROR("Failed to disable the SAGV\n");
|
||||
return result;
|
||||
}
|
||||
|
||||
dev_priv->skl_sagv_status = I915_SKL_SAGV_DISABLED;
|
||||
dev_priv->sagv_status = I915_SAGV_DISABLED;
|
||||
return 0;
|
||||
}
|
||||
|
||||
bool skl_can_enable_sagv(struct drm_atomic_state *state)
|
||||
bool intel_can_enable_sagv(struct drm_atomic_state *state)
|
||||
{
|
||||
struct drm_device *dev = state->dev;
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
@ -2984,6 +3003,9 @@ bool skl_can_enable_sagv(struct drm_atomic_state *state)
|
||||
enum pipe pipe;
|
||||
int level, plane;
|
||||
|
||||
if (!intel_has_sagv(dev_priv))
|
||||
return false;
|
||||
|
||||
/*
|
||||
* SKL workaround: bspec recommends we disable the SAGV when we have
|
||||
* more then one pipe enabled
|
||||
@ -3472,29 +3494,14 @@ static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latenc
|
||||
}
|
||||
|
||||
static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
|
||||
uint32_t horiz_pixels, uint8_t cpp,
|
||||
uint64_t tiling, uint32_t latency)
|
||||
uint32_t latency, uint32_t plane_blocks_per_line)
|
||||
{
|
||||
uint32_t ret;
|
||||
uint32_t plane_bytes_per_line, plane_blocks_per_line;
|
||||
uint32_t wm_intermediate_val;
|
||||
|
||||
if (latency == 0)
|
||||
return UINT_MAX;
|
||||
|
||||
plane_bytes_per_line = horiz_pixels * cpp;
|
||||
|
||||
if (tiling == I915_FORMAT_MOD_Y_TILED ||
|
||||
tiling == I915_FORMAT_MOD_Yf_TILED) {
|
||||
plane_bytes_per_line *= 4;
|
||||
plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
|
||||
plane_blocks_per_line /= 4;
|
||||
} else if (tiling == DRM_FORMAT_MOD_NONE) {
|
||||
plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1;
|
||||
} else {
|
||||
plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
|
||||
}
|
||||
|
||||
wm_intermediate_val = latency * pixel_rate;
|
||||
ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
|
||||
plane_blocks_per_line;
|
||||
@ -3545,6 +3552,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
|
||||
uint8_t cpp;
|
||||
uint32_t width = 0, height = 0;
|
||||
uint32_t plane_pixel_rate;
|
||||
uint32_t y_tile_minimum, y_min_scanlines;
|
||||
|
||||
if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
|
||||
*enabled = false;
|
||||
@ -3560,21 +3568,6 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
|
||||
cpp = drm_format_plane_cpp(fb->pixel_format, 0);
|
||||
plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
|
||||
|
||||
method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
|
||||
method2 = skl_wm_method2(plane_pixel_rate,
|
||||
cstate->base.adjusted_mode.crtc_htotal,
|
||||
width,
|
||||
cpp,
|
||||
fb->modifier[0],
|
||||
latency);
|
||||
|
||||
plane_bytes_per_line = width * cpp;
|
||||
plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
|
||||
|
||||
if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
|
||||
fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
|
||||
uint32_t min_scanlines = 4;
|
||||
uint32_t y_tile_minimum;
|
||||
if (intel_rotation_90_or_270(pstate->rotation)) {
|
||||
int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
|
||||
drm_format_plane_cpp(fb->pixel_format, 1) :
|
||||
@ -3582,16 +3575,44 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
|
||||
|
||||
switch (cpp) {
|
||||
case 1:
|
||||
min_scanlines = 16;
|
||||
y_min_scanlines = 16;
|
||||
break;
|
||||
case 2:
|
||||
min_scanlines = 8;
|
||||
y_min_scanlines = 8;
|
||||
break;
|
||||
case 8:
|
||||
default:
|
||||
WARN(1, "Unsupported pixel depth for rotation");
|
||||
case 4:
|
||||
y_min_scanlines = 4;
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
y_min_scanlines = 4;
|
||||
}
|
||||
y_tile_minimum = plane_blocks_per_line * min_scanlines;
|
||||
|
||||
plane_bytes_per_line = width * cpp;
|
||||
if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
|
||||
fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
|
||||
plane_blocks_per_line =
|
||||
DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
|
||||
plane_blocks_per_line /= y_min_scanlines;
|
||||
} else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
|
||||
plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
|
||||
+ 1;
|
||||
} else {
|
||||
plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
|
||||
}
|
||||
|
||||
method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
|
||||
method2 = skl_wm_method2(plane_pixel_rate,
|
||||
cstate->base.adjusted_mode.crtc_htotal,
|
||||
latency,
|
||||
plane_blocks_per_line);
|
||||
|
||||
y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
|
||||
|
||||
if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
|
||||
fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
|
||||
selected_result = max(method2, y_tile_minimum);
|
||||
} else {
|
||||
if ((ddb_allocation / plane_blocks_per_line) >= 1)
|
||||
@ -3605,11 +3626,13 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
|
||||
|
||||
if (level >= 1 && level <= 7) {
|
||||
if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
|
||||
fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
|
||||
res_lines += 4;
|
||||
else
|
||||
fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
|
||||
res_blocks += y_tile_minimum;
|
||||
res_lines += y_min_scanlines;
|
||||
} else {
|
||||
res_blocks++;
|
||||
}
|
||||
}
|
||||
|
||||
if (res_blocks >= ddb_allocation || res_lines > 31) {
|
||||
*enabled = false;
|
||||
@ -3939,6 +3962,41 @@ pipes_modified(struct drm_atomic_state *state)
|
||||
return ret;
|
||||
}
|
||||
|
||||
int
|
||||
skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
|
||||
{
|
||||
struct drm_atomic_state *state = cstate->base.state;
|
||||
struct drm_device *dev = state->dev;
|
||||
struct drm_crtc *crtc = cstate->base.crtc;
|
||||
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
|
||||
struct drm_i915_private *dev_priv = to_i915(dev);
|
||||
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
|
||||
struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
|
||||
struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
|
||||
struct drm_plane_state *plane_state;
|
||||
struct drm_plane *plane;
|
||||
enum pipe pipe = intel_crtc->pipe;
|
||||
int id;
|
||||
|
||||
WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
|
||||
|
||||
drm_for_each_plane_mask(plane, dev, crtc->state->plane_mask) {
|
||||
id = skl_wm_plane_id(to_intel_plane(plane));
|
||||
|
||||
if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
|
||||
&new_ddb->plane[pipe][id]) &&
|
||||
skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
|
||||
&new_ddb->y_plane[pipe][id]))
|
||||
continue;
|
||||
|
||||
plane_state = drm_atomic_get_plane_state(state, plane);
|
||||
if (IS_ERR(plane_state))
|
||||
return PTR_ERR(plane_state);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int
|
||||
skl_compute_ddb(struct drm_atomic_state *state)
|
||||
{
|
||||
@ -4003,7 +4061,7 @@ skl_compute_ddb(struct drm_atomic_state *state)
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
ret = drm_atomic_add_affected_planes(state, &intel_crtc->base);
|
||||
ret = skl_ddb_add_affected_planes(cstate);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -564,7 +564,7 @@ static int init_ring_common(struct intel_engine_cs *engine)
|
||||
else
|
||||
intel_ring_setup_status_page(engine);
|
||||
|
||||
intel_engine_reset_irq(engine);
|
||||
intel_engine_reset_breadcrumbs(engine);
|
||||
|
||||
/* Enforce ordering by reading HEAD register back */
|
||||
I915_READ_HEAD(engine);
|
||||
|
||||
@ -328,6 +328,7 @@ struct intel_engine_cs {
|
||||
* inspecting request list.
|
||||
*/
|
||||
u32 last_submitted_seqno;
|
||||
u32 last_pending_seqno;
|
||||
|
||||
/* An RCU guarded pointer to the last request. No reference is
|
||||
* held to the request, users must carefully acquire a reference to
|
||||
@ -492,7 +493,6 @@ int __intel_ring_space(int head, int tail, int size);
|
||||
void intel_ring_update_space(struct intel_ring *ring);
|
||||
|
||||
void intel_engine_init_seqno(struct intel_engine_cs *engine, u32 seqno);
|
||||
void intel_engine_reset_irq(struct intel_engine_cs *engine);
|
||||
|
||||
void intel_engine_setup_common(struct intel_engine_cs *engine);
|
||||
int intel_engine_init_common(struct intel_engine_cs *engine);
|
||||
@ -584,6 +584,7 @@ static inline bool intel_engine_wakeup(const struct intel_engine_cs *engine)
|
||||
return wakeup;
|
||||
}
|
||||
|
||||
void intel_engine_reset_breadcrumbs(struct intel_engine_cs *engine);
|
||||
void intel_engine_fini_breadcrumbs(struct intel_engine_cs *engine);
|
||||
unsigned int intel_kick_waiters(struct drm_i915_private *i915);
|
||||
unsigned int intel_kick_signalers(struct drm_i915_private *i915);
|
||||
|
||||
@ -796,10 +796,9 @@ __unclaimed_reg_debug(struct drm_i915_private *dev_priv,
|
||||
const bool read,
|
||||
const bool before)
|
||||
{
|
||||
if (WARN(check_for_unclaimed_mmio(dev_priv),
|
||||
"Unclaimed register detected %s %s register 0x%x\n",
|
||||
before ? "before" : "after",
|
||||
read ? "reading" : "writing to",
|
||||
if (WARN(check_for_unclaimed_mmio(dev_priv) && !before,
|
||||
"Unclaimed %s register 0x%x\n",
|
||||
read ? "read from" : "write to",
|
||||
i915_mmio_reg_offset(reg)))
|
||||
i915.mmio_debug--; /* Only report the first N failures */
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user