mmc: sdhci-esdhc-imx: add imx7d support and support HS400
The imx7d usdhc is derived from imx6sx, the difference is that imx7d support HS400. So introduce a new compatible string for imx7d and add HS400 support for imx7d usdhc. Signed-off-by: Haibo Chen <haibo.chen@freescale.com> Acked-by: Dong Aisheng <aisheng.dong@freescale.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Haibo Chen
Ulf Hansson
parent
2a2a7ea7c0
commit
28b07674f2
@ -44,6 +44,7 @@
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#define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22)
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#define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23)
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#define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25)
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#define ESDHC_MIX_CTRL_HS400_EN (1 << 26)
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/* Bits 3 and 6 are not SDHCI standard definitions */
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#define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7
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/* Tuning bits */
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@ -60,6 +61,16 @@
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#define ESDHC_TUNE_CTRL_MIN 0
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#define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1)
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/* strobe dll register */
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#define ESDHC_STROBE_DLL_CTRL 0x70
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#define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0)
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#define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1)
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#define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3
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#define ESDHC_STROBE_DLL_STATUS 0x74
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#define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1)
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#define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1
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#define ESDHC_TUNING_CTRL 0xcc
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#define ESDHC_STD_TUNING_EN (1 << 24)
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/* NOTE: the minimum valid tuning start tap for mx6sl is 1 */
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@ -120,6 +131,11 @@
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#define ESDHC_FLAG_ERR004536 BIT(7)
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/* The IP supports HS200 mode */
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#define ESDHC_FLAG_HS200 BIT(8)
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/* The IP supports HS400 mode */
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#define ESDHC_FLAG_HS400 BIT(9)
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/* A higher clock ferquency than this rate requires strobell dll control */
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#define ESDHC_STROBE_DLL_CLK_FREQ 100000000
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struct esdhc_soc_data {
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u32 flags;
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@ -156,6 +172,12 @@ static struct esdhc_soc_data usdhc_imx6sx_data = {
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| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200,
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};
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static struct esdhc_soc_data usdhc_imx7d_data = {
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.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
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| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
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| ESDHC_FLAG_HS400,
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};
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struct pltfm_imx_data {
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u32 scratchpad;
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struct pinctrl *pinctrl;
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@ -199,6 +221,7 @@ static const struct of_device_id imx_esdhc_dt_ids[] = {
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{ .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, },
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{ .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, },
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{ .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, },
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{ .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
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@ -274,6 +297,9 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
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val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104
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| SDHCI_SUPPORT_SDR50
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| SDHCI_USE_SDR50_TUNING;
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if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
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val |= SDHCI_SUPPORT_HS400;
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}
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}
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@ -774,6 +800,7 @@ static int esdhc_change_pinstate(struct sdhci_host *host,
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break;
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case MMC_TIMING_UHS_SDR104:
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case MMC_TIMING_MMC_HS200:
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case MMC_TIMING_MMC_HS400:
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pinctrl = imx_data->pins_200mhz;
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break;
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default:
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@ -784,24 +811,68 @@ static int esdhc_change_pinstate(struct sdhci_host *host,
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return pinctrl_select_state(imx_data->pinctrl, pinctrl);
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}
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/*
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* For HS400 eMMC, there is a data_strobe line, this signal is generated
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* by the device and used for data output and CRC status response output
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* in HS400 mode. The frequency of this signal follows the frequency of
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* CLK generated by host. Host receive the data which is aligned to the
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* edge of data_strobe line. Due to the time delay between CLK line and
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* data_strobe line, if the delay time is larger than one clock cycle,
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* then CLK and data_strobe line will misaligned, read error shows up.
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* So when the CLK is higher than 100MHz, each clock cycle is short enough,
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* host should config the delay target.
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*/
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static void esdhc_set_strobe_dll(struct sdhci_host *host)
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{
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u32 v;
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if (host->mmc->actual_clock > ESDHC_STROBE_DLL_CLK_FREQ) {
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/* force a reset on strobe dll */
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writel(ESDHC_STROBE_DLL_CTRL_RESET,
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host->ioaddr + ESDHC_STROBE_DLL_CTRL);
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/*
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* enable strobe dll ctrl and adjust the delay target
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* for the uSDHC loopback read clock
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*/
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v = ESDHC_STROBE_DLL_CTRL_ENABLE |
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(7 << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
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writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL);
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/* wait 1us to make sure strobe dll status register stable */
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udelay(1);
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v = readl(host->ioaddr + ESDHC_STROBE_DLL_STATUS);
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if (!(v & ESDHC_STROBE_DLL_STS_REF_LOCK))
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dev_warn(mmc_dev(host->mmc),
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"warning! HS400 strobe DLL status REF not lock!\n");
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if (!(v & ESDHC_STROBE_DLL_STS_SLV_LOCK))
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dev_warn(mmc_dev(host->mmc),
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"warning! HS400 strobe DLL status SLV not lock!\n");
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}
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}
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static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
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{
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u32 m;
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct pltfm_imx_data *imx_data = pltfm_host->priv;
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struct esdhc_platform_data *boarddata = &imx_data->boarddata;
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/* disable ddr mode and disable HS400 mode */
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m = readl(host->ioaddr + ESDHC_MIX_CTRL);
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m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN);
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imx_data->is_ddr = 0;
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switch (timing) {
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case MMC_TIMING_UHS_SDR12:
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case MMC_TIMING_UHS_SDR25:
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case MMC_TIMING_UHS_SDR50:
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case MMC_TIMING_UHS_SDR104:
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case MMC_TIMING_MMC_HS200:
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writel(m, host->ioaddr + ESDHC_MIX_CTRL);
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break;
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case MMC_TIMING_UHS_DDR50:
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case MMC_TIMING_MMC_DDR52:
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writel(readl(host->ioaddr + ESDHC_MIX_CTRL) |
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ESDHC_MIX_CTRL_DDREN,
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host->ioaddr + ESDHC_MIX_CTRL);
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m |= ESDHC_MIX_CTRL_DDREN;
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writel(m, host->ioaddr + ESDHC_MIX_CTRL);
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imx_data->is_ddr = 1;
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if (boarddata->delay_line) {
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u32 v;
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@ -813,6 +884,12 @@ static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing)
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writel(v, host->ioaddr + ESDHC_DLL_CTRL);
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}
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break;
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case MMC_TIMING_MMC_HS400:
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m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN;
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writel(m, host->ioaddr + ESDHC_MIX_CTRL);
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imx_data->is_ddr = 1;
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esdhc_set_strobe_dll(host);
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break;
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}
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esdhc_change_pinstate(host, timing);
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@ -1100,6 +1177,9 @@ static int sdhci_esdhc_imx_probe(struct platform_device *pdev)
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if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536)
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host->quirks |= SDHCI_QUIRK_BROKEN_ADMA;
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if (imx_data->socdata->flags & ESDHC_FLAG_HS400)
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host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400;
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if (of_id)
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err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data);
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else
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