forked from Minki/linux
drm/i915/gvt: vGPU HW resource management
This patch introduces the GVT-g vGPU HW resource management. Under GVT-g virtualizaion environment, each vGPU requires portions HW resources, including aperture, hidden GM space, and fence registers. When creating a vGPU, GVT-g will request these HW resources from host, and return them to host after a vGPU is destroyed. Signed-off-by: Zhi Wang <zhi.a.wang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
This commit is contained in:
Zhi Wang
Zhenyu Wang
parent
86e83e35d1
commit
28a60dee2c
@ -1,5 +1,5 @@
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GVT_DIR := gvt
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GVT_SOURCE := gvt.o
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GVT_SOURCE := gvt.o aperture_gm.o
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ccflags-y += -I$(src) -I$(src)/$(GVT_DIR) -Wall
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i915-y += $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))
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341
drivers/gpu/drm/i915/gvt/aperture_gm.c
Normal file
341
drivers/gpu/drm/i915/gvt/aperture_gm.c
Normal file
@ -0,0 +1,341 @@
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/*
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* Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Kevin Tian <kevin.tian@intel.com>
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* Dexuan Cui
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*
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* Contributors:
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* Pei Zhang <pei.zhang@intel.com>
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* Min He <min.he@intel.com>
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* Niu Bing <bing.niu@intel.com>
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* Yulei Zhang <yulei.zhang@intel.com>
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* Zhenyu Wang <zhenyuw@linux.intel.com>
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* Zhi Wang <zhi.a.wang@intel.com>
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*
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*/
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#include "i915_drv.h"
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#define MB_TO_BYTES(mb) ((mb) << 20ULL)
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#define BYTES_TO_MB(b) ((b) >> 20ULL)
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#define HOST_LOW_GM_SIZE MB_TO_BYTES(128)
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#define HOST_HIGH_GM_SIZE MB_TO_BYTES(384)
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#define HOST_FENCE 4
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static int alloc_gm(struct intel_vgpu *vgpu, bool high_gm)
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{
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struct intel_gvt *gvt = vgpu->gvt;
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struct drm_i915_private *dev_priv = gvt->dev_priv;
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u32 alloc_flag, search_flag;
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u64 start, end, size;
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struct drm_mm_node *node;
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int retried = 0;
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int ret;
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if (high_gm) {
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search_flag = DRM_MM_SEARCH_BELOW;
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alloc_flag = DRM_MM_CREATE_TOP;
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node = &vgpu->gm.high_gm_node;
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size = vgpu_hidden_sz(vgpu);
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start = gvt_hidden_gmadr_base(gvt);
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end = gvt_hidden_gmadr_end(gvt);
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} else {
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search_flag = DRM_MM_SEARCH_DEFAULT;
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alloc_flag = DRM_MM_CREATE_DEFAULT;
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node = &vgpu->gm.low_gm_node;
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size = vgpu_aperture_sz(vgpu);
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start = gvt_aperture_gmadr_base(gvt);
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end = gvt_aperture_gmadr_end(gvt);
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}
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mutex_lock(&dev_priv->drm.struct_mutex);
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search_again:
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ret = drm_mm_insert_node_in_range_generic(&dev_priv->ggtt.base.mm,
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node, size, 4096, 0,
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start, end, search_flag,
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alloc_flag);
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if (ret) {
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ret = i915_gem_evict_something(&dev_priv->ggtt.base,
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size, 4096, 0, start, end, 0);
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if (ret == 0 && ++retried < 3)
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goto search_again;
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gvt_err("fail to alloc %s gm space from host, retried %d\n",
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high_gm ? "high" : "low", retried);
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}
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mutex_unlock(&dev_priv->drm.struct_mutex);
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return ret;
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}
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static int alloc_vgpu_gm(struct intel_vgpu *vgpu)
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{
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struct intel_gvt *gvt = vgpu->gvt;
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struct drm_i915_private *dev_priv = gvt->dev_priv;
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int ret;
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ret = alloc_gm(vgpu, false);
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if (ret)
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return ret;
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ret = alloc_gm(vgpu, true);
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if (ret)
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goto out_free_aperture;
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gvt_dbg_core("vgpu%d: alloc low GM start %llx size %llx\n", vgpu->id,
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vgpu_aperture_offset(vgpu), vgpu_aperture_sz(vgpu));
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gvt_dbg_core("vgpu%d: alloc high GM start %llx size %llx\n", vgpu->id,
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vgpu_hidden_offset(vgpu), vgpu_hidden_sz(vgpu));
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return 0;
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out_free_aperture:
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mutex_lock(&dev_priv->drm.struct_mutex);
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drm_mm_remove_node(&vgpu->gm.low_gm_node);
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mutex_unlock(&dev_priv->drm.struct_mutex);
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return ret;
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}
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static void free_vgpu_gm(struct intel_vgpu *vgpu)
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{
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struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
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mutex_lock(&dev_priv->drm.struct_mutex);
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drm_mm_remove_node(&vgpu->gm.low_gm_node);
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drm_mm_remove_node(&vgpu->gm.high_gm_node);
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mutex_unlock(&dev_priv->drm.struct_mutex);
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}
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/**
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* intel_vgpu_write_fence - write fence registers owned by a vGPU
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* @vgpu: vGPU instance
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* @fence: vGPU fence register number
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* @value: Fence register value to be written
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*
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* This function is used to write fence registers owned by a vGPU. The vGPU
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* fence register number will be translated into HW fence register number.
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*
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*/
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void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
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u32 fence, u64 value)
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{
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struct intel_gvt *gvt = vgpu->gvt;
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struct drm_i915_private *dev_priv = gvt->dev_priv;
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struct drm_i915_fence_reg *reg;
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i915_reg_t fence_reg_lo, fence_reg_hi;
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if (WARN_ON(fence > vgpu_fence_sz(vgpu)))
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return;
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reg = vgpu->fence.regs[fence];
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if (WARN_ON(!reg))
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return;
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fence_reg_lo = FENCE_REG_GEN6_LO(reg->id);
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fence_reg_hi = FENCE_REG_GEN6_HI(reg->id);
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I915_WRITE(fence_reg_lo, 0);
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POSTING_READ(fence_reg_lo);
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I915_WRITE(fence_reg_hi, upper_32_bits(value));
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I915_WRITE(fence_reg_lo, lower_32_bits(value));
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POSTING_READ(fence_reg_lo);
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}
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static void free_vgpu_fence(struct intel_vgpu *vgpu)
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{
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struct intel_gvt *gvt = vgpu->gvt;
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struct drm_i915_private *dev_priv = gvt->dev_priv;
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struct drm_i915_fence_reg *reg;
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u32 i;
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if (WARN_ON(!vgpu_fence_sz(vgpu)))
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return;
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mutex_lock(&dev_priv->drm.struct_mutex);
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for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
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reg = vgpu->fence.regs[i];
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intel_vgpu_write_fence(vgpu, i, 0);
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list_add_tail(®->link,
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&dev_priv->mm.fence_list);
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}
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mutex_unlock(&dev_priv->drm.struct_mutex);
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}
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static int alloc_vgpu_fence(struct intel_vgpu *vgpu)
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{
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struct intel_gvt *gvt = vgpu->gvt;
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struct drm_i915_private *dev_priv = gvt->dev_priv;
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struct drm_i915_fence_reg *reg;
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int i;
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struct list_head *pos, *q;
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/* Request fences from host */
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mutex_lock(&dev_priv->drm.struct_mutex);
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i = 0;
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list_for_each_safe(pos, q, &dev_priv->mm.fence_list) {
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reg = list_entry(pos, struct drm_i915_fence_reg, link);
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if (reg->pin_count || reg->vma)
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continue;
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list_del(pos);
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vgpu->fence.regs[i] = reg;
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intel_vgpu_write_fence(vgpu, i, 0);
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if (++i == vgpu_fence_sz(vgpu))
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break;
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}
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if (i != vgpu_fence_sz(vgpu))
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goto out_free_fence;
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mutex_unlock(&dev_priv->drm.struct_mutex);
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return 0;
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out_free_fence:
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/* Return fences to host, if fail */
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for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
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reg = vgpu->fence.regs[i];
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if (!reg)
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continue;
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list_add_tail(®->link,
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&dev_priv->mm.fence_list);
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}
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mutex_unlock(&dev_priv->drm.struct_mutex);
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return -ENOSPC;
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}
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static void free_resource(struct intel_vgpu *vgpu)
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{
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struct intel_gvt *gvt = vgpu->gvt;
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gvt->gm.vgpu_allocated_low_gm_size -= vgpu_aperture_sz(vgpu);
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gvt->gm.vgpu_allocated_high_gm_size -= vgpu_hidden_sz(vgpu);
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gvt->fence.vgpu_allocated_fence_num -= vgpu_fence_sz(vgpu);
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}
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static int alloc_resource(struct intel_vgpu *vgpu,
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struct intel_vgpu_creation_params *param)
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{
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struct intel_gvt *gvt = vgpu->gvt;
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unsigned long request, avail, max, taken;
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const char *item;
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if (!param->low_gm_sz || !param->high_gm_sz || !param->fence_sz) {
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gvt_err("Invalid vGPU creation params\n");
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return -EINVAL;
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}
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item = "low GM space";
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max = gvt_aperture_sz(gvt) - HOST_LOW_GM_SIZE;
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taken = gvt->gm.vgpu_allocated_low_gm_size;
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avail = max - taken;
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request = MB_TO_BYTES(param->low_gm_sz);
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if (request > avail)
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goto no_enough_resource;
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vgpu_aperture_sz(vgpu) = request;
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item = "high GM space";
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max = gvt_hidden_sz(gvt) - HOST_HIGH_GM_SIZE;
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taken = gvt->gm.vgpu_allocated_high_gm_size;
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avail = max - taken;
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request = MB_TO_BYTES(param->high_gm_sz);
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if (request > avail)
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goto no_enough_resource;
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vgpu_hidden_sz(vgpu) = request;
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item = "fence";
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max = gvt_fence_sz(gvt) - HOST_FENCE;
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taken = gvt->fence.vgpu_allocated_fence_num;
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avail = max - taken;
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request = param->fence_sz;
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if (request > avail)
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goto no_enough_resource;
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vgpu_fence_sz(vgpu) = request;
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gvt->gm.vgpu_allocated_low_gm_size += MB_TO_BYTES(param->low_gm_sz);
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gvt->gm.vgpu_allocated_high_gm_size += MB_TO_BYTES(param->high_gm_sz);
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gvt->fence.vgpu_allocated_fence_num += param->fence_sz;
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return 0;
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no_enough_resource:
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gvt_err("vgpu%d: fail to allocate resource %s\n", vgpu->id, item);
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gvt_err("vgpu%d: request %luMB avail %luMB max %luMB taken %luMB\n",
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vgpu->id, BYTES_TO_MB(request), BYTES_TO_MB(avail),
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BYTES_TO_MB(max), BYTES_TO_MB(taken));
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return -ENOSPC;
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}
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/**
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* inte_gvt_free_vgpu_resource - free HW resource owned by a vGPU
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* @vgpu: a vGPU
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*
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* This function is used to free the HW resource owned by a vGPU.
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*
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*/
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void intel_vgpu_free_resource(struct intel_vgpu *vgpu)
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{
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free_vgpu_gm(vgpu);
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free_vgpu_fence(vgpu);
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free_resource(vgpu);
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}
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/**
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* intel_alloc_vgpu_resource - allocate HW resource for a vGPU
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* @vgpu: vGPU
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* @param: vGPU creation params
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*
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* This function is used to allocate HW resource for a vGPU. User specifies
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* the resource configuration through the creation params.
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*
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* Returns:
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* zero on success, negative error code if failed.
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*
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*/
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int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
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struct intel_vgpu_creation_params *param)
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{
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int ret;
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ret = alloc_resource(vgpu, param);
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if (ret)
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return ret;
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ret = alloc_vgpu_gm(vgpu);
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if (ret)
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goto out_free_resource;
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ret = alloc_vgpu_fence(vgpu);
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if (ret)
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goto out_free_vgpu_gm;
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return 0;
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out_free_vgpu_gm:
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free_vgpu_gm(vgpu);
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out_free_resource:
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free_resource(vgpu);
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return ret;
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}
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@ -24,6 +24,9 @@
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#ifndef __GVT_DEBUG_H__
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#define __GVT_DEBUG_H__
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#define gvt_err(fmt, args...) \
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DRM_ERROR("gvt: "fmt, ##args)
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#define gvt_dbg_core(fmt, args...) \
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DRM_DEBUG_DRIVER("gvt: core: "fmt, ##args)
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@ -84,7 +84,7 @@ int intel_gvt_init_host(void)
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static void init_device_info(struct intel_gvt *gvt)
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{
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if (IS_BROADWELL(gvt->dev_priv))
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if (IS_BROADWELL(gvt->dev_priv) || IS_SKYLAKE(gvt->dev_priv))
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gvt->device_info.max_support_vgpus = 8;
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/* This function will grow large in GVT device model patches. */
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}
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@ -135,6 +135,9 @@ int intel_gvt_init_device(struct drm_i915_private *dev_priv)
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gvt_dbg_core("init gvt device\n");
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mutex_init(&gvt->lock);
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gvt->dev_priv = dev_priv;
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init_device_info(gvt);
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/*
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* Other initialization of GVT components will be introduce here.
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@ -48,10 +48,39 @@ struct intel_gvt_device_info {
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/* This data structure will grow bigger in GVT device model patches */
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};
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/* GM resources owned by a vGPU */
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struct intel_vgpu_gm {
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u64 aperture_sz;
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u64 hidden_sz;
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struct drm_mm_node low_gm_node;
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struct drm_mm_node high_gm_node;
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};
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#define INTEL_GVT_MAX_NUM_FENCES 32
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/* Fences owned by a vGPU */
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struct intel_vgpu_fence {
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struct drm_i915_fence_reg *regs[INTEL_GVT_MAX_NUM_FENCES];
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u32 base;
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u32 size;
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};
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struct intel_vgpu {
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struct intel_gvt *gvt;
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int id;
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unsigned long handle; /* vGPU handle used by hypervisor MPT modules */
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struct intel_vgpu_fence fence;
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struct intel_vgpu_gm gm;
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};
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struct intel_gvt_gm {
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unsigned long vgpu_allocated_low_gm_size;
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unsigned long vgpu_allocated_high_gm_size;
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};
|
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struct intel_gvt_fence {
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unsigned long vgpu_allocated_fence_num;
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};
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struct intel_gvt {
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@ -62,8 +91,68 @@ struct intel_gvt {
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struct idr vgpu_idr; /* vGPU IDR pool */
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struct intel_gvt_device_info device_info;
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struct intel_gvt_gm gm;
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struct intel_gvt_fence fence;
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};
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/* Aperture/GM space definitions for GVT device */
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#define gvt_aperture_sz(gvt) (gvt->dev_priv->ggtt.mappable_end)
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#define gvt_aperture_pa_base(gvt) (gvt->dev_priv->ggtt.mappable_base)
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#define gvt_ggtt_gm_sz(gvt) (gvt->dev_priv->ggtt.base.total)
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#define gvt_hidden_sz(gvt) (gvt_ggtt_gm_sz(gvt) - gvt_aperture_sz(gvt))
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#define gvt_aperture_gmadr_base(gvt) (0)
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#define gvt_aperture_gmadr_end(gvt) (gvt_aperture_gmadr_base(gvt) \
|
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+ gvt_aperture_sz(gvt) - 1)
|
||||
|
||||
#define gvt_hidden_gmadr_base(gvt) (gvt_aperture_gmadr_base(gvt) \
|
||||
+ gvt_aperture_sz(gvt))
|
||||
#define gvt_hidden_gmadr_end(gvt) (gvt_hidden_gmadr_base(gvt) \
|
||||
+ gvt_hidden_sz(gvt) - 1)
|
||||
|
||||
#define gvt_fence_sz(gvt) (gvt->dev_priv->num_fence_regs)
|
||||
|
||||
/* Aperture/GM space definitions for vGPU */
|
||||
#define vgpu_aperture_offset(vgpu) ((vgpu)->gm.low_gm_node.start)
|
||||
#define vgpu_hidden_offset(vgpu) ((vgpu)->gm.high_gm_node.start)
|
||||
#define vgpu_aperture_sz(vgpu) ((vgpu)->gm.aperture_sz)
|
||||
#define vgpu_hidden_sz(vgpu) ((vgpu)->gm.hidden_sz)
|
||||
|
||||
#define vgpu_aperture_pa_base(vgpu) \
|
||||
(gvt_aperture_pa_base(vgpu->gvt) + vgpu_aperture_offset(vgpu))
|
||||
|
||||
#define vgpu_ggtt_gm_sz(vgpu) ((vgpu)->gm.aperture_sz + (vgpu)->gm.hidden_sz)
|
||||
|
||||
#define vgpu_aperture_pa_end(vgpu) \
|
||||
(vgpu_aperture_pa_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
|
||||
|
||||
#define vgpu_aperture_gmadr_base(vgpu) (vgpu_aperture_offset(vgpu))
|
||||
#define vgpu_aperture_gmadr_end(vgpu) \
|
||||
(vgpu_aperture_gmadr_base(vgpu) + vgpu_aperture_sz(vgpu) - 1)
|
||||
|
||||
#define vgpu_hidden_gmadr_base(vgpu) (vgpu_hidden_offset(vgpu))
|
||||
#define vgpu_hidden_gmadr_end(vgpu) \
|
||||
(vgpu_hidden_gmadr_base(vgpu) + vgpu_hidden_sz(vgpu) - 1)
|
||||
|
||||
#define vgpu_fence_base(vgpu) (vgpu->fence.base)
|
||||
#define vgpu_fence_sz(vgpu) (vgpu->fence.size)
|
||||
|
||||
struct intel_vgpu_creation_params {
|
||||
__u64 handle;
|
||||
__u64 low_gm_sz; /* in MB */
|
||||
__u64 high_gm_sz; /* in MB */
|
||||
__u64 fence_sz;
|
||||
__s32 primary;
|
||||
__u64 vgpu_id;
|
||||
};
|
||||
|
||||
int intel_vgpu_alloc_resource(struct intel_vgpu *vgpu,
|
||||
struct intel_vgpu_creation_params *param);
|
||||
void intel_vgpu_free_resource(struct intel_vgpu *vgpu);
|
||||
void intel_vgpu_write_fence(struct intel_vgpu *vgpu,
|
||||
u32 fence, u64 value);
|
||||
|
||||
#include "mpt.h"
|
||||
|
||||
#endif
|
||||
|
||||
@ -24,6 +24,7 @@
|
||||
#ifndef _INTEL_GVT_H_
|
||||
#define _INTEL_GVT_H_
|
||||
|
||||
#include "i915_pvinfo.h"
|
||||
#include "gvt/gvt.h"
|
||||
|
||||
#ifdef CONFIG_DRM_I915_GVT
|
||||
|
||||
Loading…
Reference in New Issue
Block a user