forked from Minki/linux
KVM: arm64: selftests: Add basic GICv3 support
Add basic support for ARM Generic Interrupt Controller v3. The support provides guests to setup interrupts. The work is inspired from kvm-unit-tests and the kernel's GIC driver (drivers/irqchip/irq-gic-v3.c). Signed-off-by: Raghavendra Rao Ananta <rananta@google.com> Reviewed-by: Andrew Jones <drjones@redhat.com> Reviewed-by: Ricardo Koller <ricarkol@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Link: https://lore.kernel.org/r/20211007233439.1826892-13-rananta@google.com
This commit is contained in:
Raghavendra Rao Ananta
Marc Zyngier
parent
414de89df1
commit
28281652f9
@ -35,7 +35,7 @@ endif
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LIBKVM = lib/assert.c lib/elf.c lib/io.c lib/kvm_util.c lib/rbtree.c lib/sparsebit.c lib/test_util.c lib/guest_modes.c lib/perf_test_util.c
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LIBKVM_x86_64 = lib/x86_64/apic.c lib/x86_64/processor.c lib/x86_64/vmx.c lib/x86_64/svm.c lib/x86_64/ucall.c lib/x86_64/handlers.S
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LIBKVM_aarch64 = lib/aarch64/processor.c lib/aarch64/ucall.c lib/aarch64/handlers.S lib/aarch64/spinlock.c
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LIBKVM_aarch64 = lib/aarch64/processor.c lib/aarch64/ucall.c lib/aarch64/handlers.S lib/aarch64/spinlock.c lib/aarch64/gic.c lib/aarch64/gic_v3.c
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LIBKVM_s390x = lib/s390x/processor.c lib/s390x/ucall.c lib/s390x/diag318_test_handler.c
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TEST_GEN_PROGS_x86_64 = x86_64/cr4_cpuid_sync_test
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21
tools/testing/selftests/kvm/include/aarch64/gic.h
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21
tools/testing/selftests/kvm/include/aarch64/gic.h
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@ -0,0 +1,21 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* ARM Generic Interrupt Controller (GIC) specific defines
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*/
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#ifndef SELFTEST_KVM_GIC_H
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#define SELFTEST_KVM_GIC_H
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enum gic_type {
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GIC_V3,
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GIC_TYPE_MAX,
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};
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void gic_init(enum gic_type type, unsigned int nr_cpus,
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void *dist_base, void *redist_base);
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void gic_irq_enable(unsigned int intid);
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void gic_irq_disable(unsigned int intid);
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unsigned int gic_get_and_ack_irq(void);
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void gic_set_eoi(unsigned int intid);
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#endif /* SELFTEST_KVM_GIC_H */
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95
tools/testing/selftests/kvm/lib/aarch64/gic.c
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95
tools/testing/selftests/kvm/lib/aarch64/gic.c
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@ -0,0 +1,95 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* ARM Generic Interrupt Controller (GIC) support
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*/
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#include <errno.h>
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#include <linux/bits.h>
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#include <linux/sizes.h>
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#include "kvm_util.h"
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#include <gic.h>
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#include "gic_private.h"
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#include "processor.h"
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#include "spinlock.h"
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static const struct gic_common_ops *gic_common_ops;
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static struct spinlock gic_lock;
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static void gic_cpu_init(unsigned int cpu, void *redist_base)
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{
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gic_common_ops->gic_cpu_init(cpu, redist_base);
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}
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static void
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gic_dist_init(enum gic_type type, unsigned int nr_cpus, void *dist_base)
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{
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const struct gic_common_ops *gic_ops = NULL;
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spin_lock(&gic_lock);
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/* Distributor initialization is needed only once per VM */
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if (gic_common_ops) {
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spin_unlock(&gic_lock);
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return;
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}
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if (type == GIC_V3)
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gic_ops = &gicv3_ops;
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GUEST_ASSERT(gic_ops);
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gic_ops->gic_init(nr_cpus, dist_base);
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gic_common_ops = gic_ops;
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/* Make sure that the initialized data is visible to all the vCPUs */
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dsb(sy);
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spin_unlock(&gic_lock);
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}
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void gic_init(enum gic_type type, unsigned int nr_cpus,
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void *dist_base, void *redist_base)
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{
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uint32_t cpu = guest_get_vcpuid();
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GUEST_ASSERT(type < GIC_TYPE_MAX);
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GUEST_ASSERT(dist_base);
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GUEST_ASSERT(redist_base);
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GUEST_ASSERT(nr_cpus);
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gic_dist_init(type, nr_cpus, dist_base);
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gic_cpu_init(cpu, redist_base);
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}
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void gic_irq_enable(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_irq_enable(intid);
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}
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void gic_irq_disable(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_irq_disable(intid);
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}
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unsigned int gic_get_and_ack_irq(void)
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{
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uint64_t irqstat;
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unsigned int intid;
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GUEST_ASSERT(gic_common_ops);
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irqstat = gic_common_ops->gic_read_iar();
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intid = irqstat & GENMASK(23, 0);
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return intid;
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}
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void gic_set_eoi(unsigned int intid)
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{
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GUEST_ASSERT(gic_common_ops);
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gic_common_ops->gic_write_eoir(intid);
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}
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21
tools/testing/selftests/kvm/lib/aarch64/gic_private.h
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21
tools/testing/selftests/kvm/lib/aarch64/gic_private.h
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@ -0,0 +1,21 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* ARM Generic Interrupt Controller (GIC) private defines that's only
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* shared among the GIC library code.
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*/
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#ifndef SELFTEST_KVM_GIC_PRIVATE_H
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#define SELFTEST_KVM_GIC_PRIVATE_H
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struct gic_common_ops {
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void (*gic_init)(unsigned int nr_cpus, void *dist_base);
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void (*gic_cpu_init)(unsigned int cpu, void *redist_base);
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void (*gic_irq_enable)(unsigned int intid);
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void (*gic_irq_disable)(unsigned int intid);
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uint64_t (*gic_read_iar)(void);
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void (*gic_write_eoir)(uint32_t irq);
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};
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extern const struct gic_common_ops gicv3_ops;
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#endif /* SELFTEST_KVM_GIC_PRIVATE_H */
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240
tools/testing/selftests/kvm/lib/aarch64/gic_v3.c
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240
tools/testing/selftests/kvm/lib/aarch64/gic_v3.c
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@ -0,0 +1,240 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* ARM Generic Interrupt Controller (GIC) v3 support
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*/
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#include <linux/sizes.h>
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#include "kvm_util.h"
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#include "processor.h"
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#include "delay.h"
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#include "gic_v3.h"
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#include "gic_private.h"
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struct gicv3_data {
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void *dist_base;
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void *redist_base[GICV3_MAX_CPUS];
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unsigned int nr_cpus;
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unsigned int nr_spis;
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};
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#define sgi_base_from_redist(redist_base) (redist_base + SZ_64K)
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enum gicv3_intid_range {
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SGI_RANGE,
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PPI_RANGE,
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SPI_RANGE,
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INVALID_RANGE,
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};
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static struct gicv3_data gicv3_data;
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static void gicv3_gicd_wait_for_rwp(void)
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{
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unsigned int count = 100000; /* 1s */
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while (readl(gicv3_data.dist_base + GICD_CTLR) & GICD_CTLR_RWP) {
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GUEST_ASSERT(count--);
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udelay(10);
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}
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}
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static void gicv3_gicr_wait_for_rwp(void *redist_base)
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{
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unsigned int count = 100000; /* 1s */
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while (readl(redist_base + GICR_CTLR) & GICR_CTLR_RWP) {
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GUEST_ASSERT(count--);
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udelay(10);
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}
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}
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static enum gicv3_intid_range get_intid_range(unsigned int intid)
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{
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switch (intid) {
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case 0 ... 15:
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return SGI_RANGE;
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case 16 ... 31:
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return PPI_RANGE;
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case 32 ... 1019:
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return SPI_RANGE;
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}
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/* We should not be reaching here */
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GUEST_ASSERT(0);
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return INVALID_RANGE;
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}
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static uint64_t gicv3_read_iar(void)
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{
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uint64_t irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
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dsb(sy);
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return irqstat;
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}
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static void gicv3_write_eoir(uint32_t irq)
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{
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write_sysreg_s(irq, SYS_ICC_EOIR1_EL1);
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isb();
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}
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static void
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gicv3_config_irq(unsigned int intid, unsigned int offset)
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{
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uint32_t cpu = guest_get_vcpuid();
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uint32_t mask = 1 << (intid % 32);
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enum gicv3_intid_range intid_range = get_intid_range(intid);
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void *reg;
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/* We care about 'cpu' only for SGIs or PPIs */
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if (intid_range == SGI_RANGE || intid_range == PPI_RANGE) {
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GUEST_ASSERT(cpu < gicv3_data.nr_cpus);
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reg = sgi_base_from_redist(gicv3_data.redist_base[cpu]) +
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offset;
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writel(mask, reg);
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gicv3_gicr_wait_for_rwp(gicv3_data.redist_base[cpu]);
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} else if (intid_range == SPI_RANGE) {
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reg = gicv3_data.dist_base + offset + (intid / 32) * 4;
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writel(mask, reg);
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gicv3_gicd_wait_for_rwp();
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} else {
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GUEST_ASSERT(0);
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}
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}
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static void gicv3_irq_enable(unsigned int intid)
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{
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gicv3_config_irq(intid, GICD_ISENABLER);
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}
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static void gicv3_irq_disable(unsigned int intid)
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{
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gicv3_config_irq(intid, GICD_ICENABLER);
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}
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static void gicv3_enable_redist(void *redist_base)
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{
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uint32_t val = readl(redist_base + GICR_WAKER);
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unsigned int count = 100000; /* 1s */
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val &= ~GICR_WAKER_ProcessorSleep;
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writel(val, redist_base + GICR_WAKER);
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/* Wait until the processor is 'active' */
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while (readl(redist_base + GICR_WAKER) & GICR_WAKER_ChildrenAsleep) {
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GUEST_ASSERT(count--);
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udelay(10);
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}
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}
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static inline void *gicr_base_cpu(void *redist_base, uint32_t cpu)
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{
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/* Align all the redistributors sequentially */
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return redist_base + cpu * SZ_64K * 2;
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}
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static void gicv3_cpu_init(unsigned int cpu, void *redist_base)
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{
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void *sgi_base;
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unsigned int i;
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void *redist_base_cpu;
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GUEST_ASSERT(cpu < gicv3_data.nr_cpus);
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redist_base_cpu = gicr_base_cpu(redist_base, cpu);
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sgi_base = sgi_base_from_redist(redist_base_cpu);
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gicv3_enable_redist(redist_base_cpu);
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/*
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* Mark all the SGI and PPI interrupts as non-secure Group-1.
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* Also, deactivate and disable them.
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*/
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writel(~0, sgi_base + GICR_IGROUPR0);
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writel(~0, sgi_base + GICR_ICACTIVER0);
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writel(~0, sgi_base + GICR_ICENABLER0);
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/* Set a default priority for all the SGIs and PPIs */
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for (i = 0; i < 32; i += 4)
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writel(GICD_INT_DEF_PRI_X4,
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sgi_base + GICR_IPRIORITYR0 + i);
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gicv3_gicr_wait_for_rwp(redist_base_cpu);
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/* Enable the GIC system register (ICC_*) access */
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write_sysreg_s(read_sysreg_s(SYS_ICC_SRE_EL1) | ICC_SRE_EL1_SRE,
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SYS_ICC_SRE_EL1);
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/* Set a default priority threshold */
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write_sysreg_s(ICC_PMR_DEF_PRIO, SYS_ICC_PMR_EL1);
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/* Enable non-secure Group-1 interrupts */
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write_sysreg_s(ICC_IGRPEN1_EL1_ENABLE, SYS_ICC_GRPEN1_EL1);
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gicv3_data.redist_base[cpu] = redist_base_cpu;
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}
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static void gicv3_dist_init(void)
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{
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void *dist_base = gicv3_data.dist_base;
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unsigned int i;
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/* Disable the distributor until we set things up */
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writel(0, dist_base + GICD_CTLR);
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gicv3_gicd_wait_for_rwp();
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/*
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* Mark all the SPI interrupts as non-secure Group-1.
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* Also, deactivate and disable them.
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*/
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for (i = 32; i < gicv3_data.nr_spis; i += 32) {
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writel(~0, dist_base + GICD_IGROUPR + i / 8);
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writel(~0, dist_base + GICD_ICACTIVER + i / 8);
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writel(~0, dist_base + GICD_ICENABLER + i / 8);
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}
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/* Set a default priority for all the SPIs */
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for (i = 32; i < gicv3_data.nr_spis; i += 4)
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writel(GICD_INT_DEF_PRI_X4,
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dist_base + GICD_IPRIORITYR + i);
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/* Wait for the settings to sync-in */
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gicv3_gicd_wait_for_rwp();
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/* Finally, enable the distributor globally with ARE */
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writel(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A |
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GICD_CTLR_ENABLE_G1, dist_base + GICD_CTLR);
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gicv3_gicd_wait_for_rwp();
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}
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static void gicv3_init(unsigned int nr_cpus, void *dist_base)
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{
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GUEST_ASSERT(nr_cpus <= GICV3_MAX_CPUS);
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gicv3_data.nr_cpus = nr_cpus;
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gicv3_data.dist_base = dist_base;
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gicv3_data.nr_spis = GICD_TYPER_SPIS(
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readl(gicv3_data.dist_base + GICD_TYPER));
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if (gicv3_data.nr_spis > 1020)
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gicv3_data.nr_spis = 1020;
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/*
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* Initialize only the distributor for now.
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* The redistributor and CPU interfaces are initialized
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* later for every PE.
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*/
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gicv3_dist_init();
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}
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const struct gic_common_ops gicv3_ops = {
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.gic_init = gicv3_init,
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.gic_cpu_init = gicv3_cpu_init,
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.gic_irq_enable = gicv3_irq_enable,
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.gic_irq_disable = gicv3_irq_disable,
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.gic_read_iar = gicv3_read_iar,
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.gic_write_eoir = gicv3_write_eoir,
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};
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70
tools/testing/selftests/kvm/lib/aarch64/gic_v3.h
Normal file
70
tools/testing/selftests/kvm/lib/aarch64/gic_v3.h
Normal file
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* ARM Generic Interrupt Controller (GIC) v3 specific defines
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*/
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#ifndef SELFTEST_KVM_GICV3_H
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#define SELFTEST_KVM_GICV3_H
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#include <asm/sysreg.h>
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/*
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* Distributor registers
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*/
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#define GICD_CTLR 0x0000
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#define GICD_TYPER 0x0004
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#define GICD_IGROUPR 0x0080
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#define GICD_ISENABLER 0x0100
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#define GICD_ICENABLER 0x0180
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#define GICD_ICACTIVER 0x0380
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#define GICD_IPRIORITYR 0x0400
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/*
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* The assumption is that the guest runs in a non-secure mode.
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* The following bits of GICD_CTLR are defined accordingly.
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*/
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#define GICD_CTLR_RWP (1U << 31)
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#define GICD_CTLR_nASSGIreq (1U << 8)
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#define GICD_CTLR_ARE_NS (1U << 4)
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#define GICD_CTLR_ENABLE_G1A (1U << 1)
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#define GICD_CTLR_ENABLE_G1 (1U << 0)
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#define GICD_TYPER_SPIS(typer) ((((typer) & 0x1f) + 1) * 32)
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#define GICD_INT_DEF_PRI_X4 0xa0a0a0a0
|
||||
|
||||
/*
|
||||
* Redistributor registers
|
||||
*/
|
||||
#define GICR_CTLR 0x000
|
||||
#define GICR_WAKER 0x014
|
||||
|
||||
#define GICR_CTLR_RWP (1U << 3)
|
||||
|
||||
#define GICR_WAKER_ProcessorSleep (1U << 1)
|
||||
#define GICR_WAKER_ChildrenAsleep (1U << 2)
|
||||
|
||||
/*
|
||||
* Redistributor registers, offsets from SGI base
|
||||
*/
|
||||
#define GICR_IGROUPR0 GICD_IGROUPR
|
||||
#define GICR_ISENABLER0 GICD_ISENABLER
|
||||
#define GICR_ICENABLER0 GICD_ICENABLER
|
||||
#define GICR_ICACTIVER0 GICD_ICACTIVER
|
||||
#define GICR_IPRIORITYR0 GICD_IPRIORITYR
|
||||
|
||||
/* CPU interface registers */
|
||||
#define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0)
|
||||
#define SYS_ICC_IAR1_EL1 sys_reg(3, 0, 12, 12, 0)
|
||||
#define SYS_ICC_EOIR1_EL1 sys_reg(3, 0, 12, 12, 1)
|
||||
#define SYS_ICC_SRE_EL1 sys_reg(3, 0, 12, 12, 5)
|
||||
#define SYS_ICC_GRPEN1_EL1 sys_reg(3, 0, 12, 12, 7)
|
||||
|
||||
#define ICC_PMR_DEF_PRIO 0xf0
|
||||
|
||||
#define ICC_SRE_EL1_SRE (1U << 0)
|
||||
|
||||
#define ICC_IGRPEN1_EL1_ENABLE (1U << 0)
|
||||
|
||||
#define GICV3_MAX_CPUS 512
|
||||
|
||||
#endif /* SELFTEST_KVM_GICV3_H */
|
||||
Loading…
Reference in New Issue
Block a user