forked from Minki/linux
MFD: TPS65910: Add new mfd device for TPS65910
The TPS65910 chip is a power management IC for multimedia and handheld devices. It contains the following components: - Regulators - GPIO controller - RTC The tps65910 core driver is registered as a platform driver and provides communication through I2C with the host device for the different components. Signed-off-by: Graeme Gregory <gg@slimlogic.co.uk> Signed-off-by: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk> Acked-by: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Liam Girdwood <lrg@slimlogic.co.uk>
This commit is contained in:
Graeme Gregory
Liam Girdwood
parent
98ea5c218e
commit
27c6750ec5
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@ -719,6 +719,14 @@ config MFD_PM8XXX_IRQ
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This is required to use certain other PM 8xxx features, such as GPIO
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and MPP.
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config MFD_TPS65910
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tristate "TPS65910 Power Management chip"
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depends on I2C && GPIOLIB
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select MFD_CORE
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help
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if you say yes here you get support for the TPS65910 series of
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Power Management chips.
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endif # MFD_SUPPORT
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menu "Multimedia Capabilities Port drivers"
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@ -93,3 +93,4 @@ obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o
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obj-$(CONFIG_MFD_OMAP_USB_HOST) += omap-usb-host.o
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obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o
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obj-$(CONFIG_MFD_PM8XXX_IRQ) += pm8xxx-irq.o
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obj-$(CONFIG_MFD_TPS65910) += tps65910.o
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208
drivers/mfd/tps65910.c
Normal file
208
drivers/mfd/tps65910.c
Normal file
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@ -0,0 +1,208 @@
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/*
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* tps65910.c -- TI TPS6591x
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*
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* Copyright 2010 Texas Instruments Inc.
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*
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* Author: Graeme Gregory <gg@slimlogic.co.uk>
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* Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#include <linux/module.h>
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#include <linux/moduleparam.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/i2c.h>
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#include <linux/gpio.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/tps65910.h>
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static struct mfd_cell tps65910s[] = {
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{
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.name = "tps65910-pmic",
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},
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{
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.name = "tps65910-rtc",
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},
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{
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.name = "tps65910-power",
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},
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};
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static int tps65910_i2c_read(struct tps65910 *tps65910, u8 reg,
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int bytes, void *dest)
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{
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struct i2c_client *i2c = tps65910->i2c_client;
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struct i2c_msg xfer[2];
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int ret;
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/* Write register */
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xfer[0].addr = i2c->addr;
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xfer[0].flags = 0;
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xfer[0].len = 1;
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xfer[0].buf = ®
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/* Read data */
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xfer[1].addr = i2c->addr;
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xfer[1].flags = I2C_M_RD;
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xfer[1].len = bytes;
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xfer[1].buf = dest;
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ret = i2c_transfer(i2c->adapter, xfer, 2);
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if (ret == 2)
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ret = 0;
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else if (ret >= 0)
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ret = -EIO;
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return ret;
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}
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static int tps65910_i2c_write(struct tps65910 *tps65910, u8 reg,
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int bytes, void *src)
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{
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struct i2c_client *i2c = tps65910->i2c_client;
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/* we add 1 byte for device register */
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u8 msg[TPS65910_MAX_REGISTER + 1];
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int ret;
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if (bytes > (TPS65910_MAX_REGISTER + 1))
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return -EINVAL;
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msg[0] = reg;
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memcpy(&msg[1], src, bytes);
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ret = i2c_master_send(i2c, msg, bytes + 1);
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if (ret < 0)
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return ret;
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if (ret != bytes + 1)
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return -EIO;
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return 0;
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}
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int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask)
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{
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u8 data;
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int err;
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mutex_lock(&tps65910->io_mutex);
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err = tps65910_i2c_read(tps65910, reg, 1, &data);
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if (err) {
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dev_err(tps65910->dev, "read from reg %x failed\n", reg);
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goto out;
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}
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data |= mask;
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err = tps65910_i2c_write(tps65910, reg, 1, &data);
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if (err)
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dev_err(tps65910->dev, "write to reg %x failed\n", reg);
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out:
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mutex_unlock(&tps65910->io_mutex);
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return err;
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}
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EXPORT_SYMBOL_GPL(tps65910_set_bits);
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int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask)
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{
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u8 data;
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int err;
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mutex_lock(&tps65910->io_mutex);
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err = tps65910_i2c_read(tps65910, reg, 1, &data);
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if (err) {
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dev_err(tps65910->dev, "read from reg %x failed\n", reg);
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goto out;
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}
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data &= mask;
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err = tps65910_i2c_write(tps65910, reg, 1, &data);
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if (err)
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dev_err(tps65910->dev, "write to reg %x failed\n", reg);
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out:
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mutex_unlock(&tps65910->io_mutex);
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return err;
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}
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EXPORT_SYMBOL_GPL(tps65910_clear_bits);
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static int tps65910_i2c_probe(struct i2c_client *i2c,
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const struct i2c_device_id *id)
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{
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struct tps65910 *tps65910;
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int ret = 0;
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tps65910 = kzalloc(sizeof(struct tps65910), GFP_KERNEL);
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if (tps65910 == NULL)
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return -ENOMEM;
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i2c_set_clientdata(i2c, tps65910);
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tps65910->dev = &i2c->dev;
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tps65910->i2c_client = i2c;
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tps65910->read = tps65910_i2c_read;
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tps65910->write = tps65910_i2c_write;
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mutex_init(&tps65910->io_mutex);
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ret = mfd_add_devices(tps65910->dev, -1,
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tps65910s, ARRAY_SIZE(tps65910s),
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NULL, 0);
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if (ret < 0)
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goto err;
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return ret;
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err:
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mfd_remove_devices(tps65910->dev);
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kfree(tps65910);
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return ret;
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}
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static int tps65910_i2c_remove(struct i2c_client *i2c)
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{
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struct tps65910 *tps65910 = i2c_get_clientdata(i2c);
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mfd_remove_devices(tps65910->dev);
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kfree(tps65910);
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return 0;
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}
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static const struct i2c_device_id tps65910_i2c_id[] = {
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{ "tps65910", 0 },
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{ }
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};
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MODULE_DEVICE_TABLE(i2c, tps65910_i2c_id);
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static struct i2c_driver tps65910_i2c_driver = {
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.driver = {
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.name = "tps65910",
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.owner = THIS_MODULE,
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},
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.probe = tps65910_i2c_probe,
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.remove = tps65910_i2c_remove,
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.id_table = tps65910_i2c_id,
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};
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static int __init tps65910_i2c_init(void)
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{
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return i2c_add_driver(&tps65910_i2c_driver);
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}
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/* init early so consumer devices can complete system boot */
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subsys_initcall(tps65910_i2c_init);
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static void __exit tps65910_i2c_exit(void)
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{
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i2c_del_driver(&tps65910_i2c_driver);
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}
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module_exit(tps65910_i2c_exit);
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MODULE_AUTHOR("Graeme Gregory <gg@slimlogic.co.uk>");
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MODULE_AUTHOR("Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>");
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MODULE_DESCRIPTION("TPS6591x chip family multi-function driver");
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MODULE_LICENSE("GPL");
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753
include/linux/mfd/tps65910.h
Normal file
753
include/linux/mfd/tps65910.h
Normal file
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@ -0,0 +1,753 @@
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/*
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* tps65910.h -- TI TPS6591x
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*
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* Copyright 2010-2011 Texas Instruments Inc.
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*
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* Author: Graeme Gregory <gg@slimlogic.co.uk>
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* Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
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* Author: Arnaud Deconinck <a-deconinck@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __LINUX_MFD_TPS65910_H
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#define __LINUX_MFD_TPS65910_H
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/*
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* List of registers for component TPS65910
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*
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*/
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#define TPS65910_SECONDS 0x0
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#define TPS65910_MINUTES 0x1
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#define TPS65910_HOURS 0x2
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#define TPS65910_DAYS 0x3
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#define TPS65910_MONTHS 0x4
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#define TPS65910_YEARS 0x5
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#define TPS65910_WEEKS 0x6
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#define TPS65910_ALARM_SECONDS 0x8
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#define TPS65910_ALARM_MINUTES 0x9
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#define TPS65910_ALARM_HOURS 0xA
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#define TPS65910_ALARM_DAYS 0xB
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#define TPS65910_ALARM_MONTHS 0xC
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#define TPS65910_ALARM_YEARS 0xD
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#define TPS65910_RTC_CTRL 0x10
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#define TPS65910_RTC_STATUS 0x11
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#define TPS65910_RTC_INTERRUPTS 0x12
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#define TPS65910_RTC_COMP_LSB 0x13
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#define TPS65910_RTC_COMP_MSB 0x14
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#define TPS65910_RTC_RES_PROG 0x15
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#define TPS65910_RTC_RESET_STATUS 0x16
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#define TPS65910_BCK1 0x17
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#define TPS65910_BCK2 0x18
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#define TPS65910_BCK3 0x19
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#define TPS65910_BCK4 0x1A
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#define TPS65910_BCK5 0x1B
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#define TPS65910_PUADEN 0x1C
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#define TPS65910_REF 0x1D
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#define TPS65910_VRTC 0x1E
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#define TPS65910_VIO 0x20
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#define TPS65910_VDD1 0x21
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#define TPS65910_VDD1_OP 0x22
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#define TPS65910_VDD1_SR 0x23
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#define TPS65910_VDD2 0x24
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#define TPS65910_VDD2_OP 0x25
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#define TPS65910_VDD2_SR 0x26
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#define TPS65910_VDD3 0x27
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#define TPS65910_VDIG1 0x30
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#define TPS65910_VDIG2 0x31
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#define TPS65910_VAUX1 0x32
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#define TPS65910_VAUX2 0x33
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#define TPS65910_VAUX33 0x34
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#define TPS65910_VMMC 0x35
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#define TPS65910_VPLL 0x36
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#define TPS65910_VDAC 0x37
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#define TPS65910_THERM 0x38
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#define TPS65910_BBCH 0x39
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#define TPS65910_DCDCCTRL 0x3E
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#define TPS65910_DEVCTRL 0x3F
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#define TPS65910_DEVCTRL2 0x40
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#define TPS65910_SLEEP_KEEP_LDO_ON 0x41
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#define TPS65910_SLEEP_KEEP_RES_ON 0x42
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#define TPS65910_SLEEP_SET_LDO_OFF 0x43
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#define TPS65910_SLEEP_SET_RES_OFF 0x44
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#define TPS65910_EN1_LDO_ASS 0x45
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#define TPS65910_EN1_SMPS_ASS 0x46
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#define TPS65910_EN2_LDO_ASS 0x47
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#define TPS65910_EN2_SMPS_ASS 0x48
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#define TPS65910_EN3_LDO_ASS 0x49
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#define TPS65910_SPARE 0x4A
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#define TPS65910_INT_STS 0x50
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#define TPS65910_INT_MSK 0x51
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#define TPS65910_INT_STS2 0x52
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#define TPS65910_INT_MSK2 0x53
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#define TPS65910_INT_STS3 0x54
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#define TPS65910_INT_MSK3 0x55
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#define TPS65910_GPIO0 0x60
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#define TPS65910_GPIO1 0x61
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#define TPS65910_GPIO2 0x62
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#define TPS65910_GPIO3 0x63
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#define TPS65910_GPIO4 0x64
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#define TPS65910_GPIO5 0x65
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#define TPS65910_JTAGVERNUM 0x80
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#define TPS65910_MAX_REGISTER 0x80
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/*
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* List of register bitfields for component TPS65910
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*
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*/
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/*Register BCK1 (0x80) register.RegisterDescription */
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#define BCK1_BCKUP_MASK 0xFF
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#define BCK1_BCKUP_SHIFT 0
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/*Register BCK2 (0x80) register.RegisterDescription */
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#define BCK2_BCKUP_MASK 0xFF
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#define BCK2_BCKUP_SHIFT 0
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/*Register BCK3 (0x80) register.RegisterDescription */
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#define BCK3_BCKUP_MASK 0xFF
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#define BCK3_BCKUP_SHIFT 0
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/*Register BCK4 (0x80) register.RegisterDescription */
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#define BCK4_BCKUP_MASK 0xFF
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#define BCK4_BCKUP_SHIFT 0
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/*Register BCK5 (0x80) register.RegisterDescription */
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#define BCK5_BCKUP_MASK 0xFF
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#define BCK5_BCKUP_SHIFT 0
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/*Register PUADEN (0x80) register.RegisterDescription */
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#define PUADEN_EN3P_MASK 0x80
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#define PUADEN_EN3P_SHIFT 7
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#define PUADEN_I2CCTLP_MASK 0x40
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#define PUADEN_I2CCTLP_SHIFT 6
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#define PUADEN_I2CSRP_MASK 0x20
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#define PUADEN_I2CSRP_SHIFT 5
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#define PUADEN_PWRONP_MASK 0x10
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#define PUADEN_PWRONP_SHIFT 4
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#define PUADEN_SLEEPP_MASK 0x08
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#define PUADEN_SLEEPP_SHIFT 3
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#define PUADEN_PWRHOLDP_MASK 0x04
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#define PUADEN_PWRHOLDP_SHIFT 2
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#define PUADEN_BOOT1P_MASK 0x02
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#define PUADEN_BOOT1P_SHIFT 1
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#define PUADEN_BOOT0P_MASK 0x01
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#define PUADEN_BOOT0P_SHIFT 0
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/*Register REF (0x80) register.RegisterDescription */
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#define REF_VMBCH_SEL_MASK 0x0C
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#define REF_VMBCH_SEL_SHIFT 2
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#define REF_ST_MASK 0x03
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#define REF_ST_SHIFT 0
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/*Register VRTC (0x80) register.RegisterDescription */
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#define VRTC_VRTC_OFFMASK_MASK 0x08
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#define VRTC_VRTC_OFFMASK_SHIFT 3
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#define VRTC_ST_MASK 0x03
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#define VRTC_ST_SHIFT 0
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/*Register VIO (0x80) register.RegisterDescription */
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#define VIO_ILMAX_MASK 0xC0
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#define VIO_ILMAX_SHIFT 6
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#define VIO_SEL_MASK 0x0C
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#define VIO_SEL_SHIFT 2
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#define VIO_ST_MASK 0x03
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#define VIO_ST_SHIFT 0
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/*Register VDD1 (0x80) register.RegisterDescription */
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#define VDD1_VGAIN_SEL_MASK 0xC0
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#define VDD1_VGAIN_SEL_SHIFT 6
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#define VDD1_ILMAX_MASK 0x20
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#define VDD1_ILMAX_SHIFT 5
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#define VDD1_TSTEP_MASK 0x1C
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#define VDD1_TSTEP_SHIFT 2
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#define VDD1_ST_MASK 0x03
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#define VDD1_ST_SHIFT 0
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/*Register VDD1_OP (0x80) register.RegisterDescription */
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#define VDD1_OP_CMD_MASK 0x80
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#define VDD1_OP_CMD_SHIFT 7
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#define VDD1_OP_SEL_MASK 0x7F
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#define VDD1_OP_SEL_SHIFT 0
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/*Register VDD1_SR (0x80) register.RegisterDescription */
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#define VDD1_SR_SEL_MASK 0x7F
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#define VDD1_SR_SEL_SHIFT 0
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/*Register VDD2 (0x80) register.RegisterDescription */
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#define VDD2_VGAIN_SEL_MASK 0xC0
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#define VDD2_VGAIN_SEL_SHIFT 6
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#define VDD2_ILMAX_MASK 0x20
|
||||
#define VDD2_ILMAX_SHIFT 5
|
||||
#define VDD2_TSTEP_MASK 0x1C
|
||||
#define VDD2_TSTEP_SHIFT 2
|
||||
#define VDD2_ST_MASK 0x03
|
||||
#define VDD2_ST_SHIFT 0
|
||||
|
||||
|
||||
/*Register VDD2_OP (0x80) register.RegisterDescription */
|
||||
#define VDD2_OP_CMD_MASK 0x80
|
||||
#define VDD2_OP_CMD_SHIFT 7
|
||||
#define VDD2_OP_SEL_MASK 0x7F
|
||||
#define VDD2_OP_SEL_SHIFT 0
|
||||
|
||||
|
||||
/*Register VDD2_SR (0x80) register.RegisterDescription */
|
||||
#define VDD2_SR_SEL_MASK 0x7F
|
||||
#define VDD2_SR_SEL_SHIFT 0
|
||||
|
||||
|
||||
/*Register VDD3 (0x80) register.RegisterDescription */
|
||||
#define VDD3_CKINEN_MASK 0x04
|
||||
#define VDD3_CKINEN_SHIFT 2
|
||||
#define VDD3_ST_MASK 0x03
|
||||
#define VDD3_ST_SHIFT 0
|
||||
|
||||
|
||||
/*Register VDIG1 (0x80) register.RegisterDescription */
|
||||
#define VDIG1_SEL_MASK 0x0C
|
||||
#define VDIG1_SEL_SHIFT 2
|
||||
#define VDIG1_ST_MASK 0x03
|
||||
#define VDIG1_ST_SHIFT 0
|
||||
|
||||
|
||||
/*Register VDIG2 (0x80) register.RegisterDescription */
|
||||
#define VDIG2_SEL_MASK 0x0C
|
||||
#define VDIG2_SEL_SHIFT 2
|
||||
#define VDIG2_ST_MASK 0x03
|
||||
#define VDIG2_ST_SHIFT 0
|
||||
|
||||
|
||||
/*Register VAUX1 (0x80) register.RegisterDescription */
|
||||
#define VAUX1_SEL_MASK 0x0C
|
||||
#define VAUX1_SEL_SHIFT 2
|
||||
#define VAUX1_ST_MASK 0x03
|
||||
#define VAUX1_ST_SHIFT 0
|
||||
|
||||
|
||||
/*Register VAUX2 (0x80) register.RegisterDescription */
|
||||
#define VAUX2_SEL_MASK 0x0C
|
||||
#define VAUX2_SEL_SHIFT 2
|
||||
#define VAUX2_ST_MASK 0x03
|
||||
#define VAUX2_ST_SHIFT 0
|
||||
|
||||
|
||||
/*Register VAUX33 (0x80) register.RegisterDescription */
|
||||
#define VAUX33_SEL_MASK 0x0C
|
||||
#define VAUX33_SEL_SHIFT 2
|
||||
#define VAUX33_ST_MASK 0x03
|
||||
#define VAUX33_ST_SHIFT 0
|
||||
|
||||
|
||||
/*Register VMMC (0x80) register.RegisterDescription */
|
||||
#define VMMC_SEL_MASK 0x0C
|
||||
#define VMMC_SEL_SHIFT 2
|
||||
#define VMMC_ST_MASK 0x03
|
||||
#define VMMC_ST_SHIFT 0
|
||||
|
||||
|
||||
/*Register VPLL (0x80) register.RegisterDescription */
|
||||
#define VPLL_SEL_MASK 0x0C
|
||||
#define VPLL_SEL_SHIFT 2
|
||||
#define VPLL_ST_MASK 0x03
|
||||
#define VPLL_ST_SHIFT 0
|
||||
|
||||
|
||||
/*Register VDAC (0x80) register.RegisterDescription */
|
||||
#define VDAC_SEL_MASK 0x0C
|
||||
#define VDAC_SEL_SHIFT 2
|
||||
#define VDAC_ST_MASK 0x03
|
||||
#define VDAC_ST_SHIFT 0
|
||||
|
||||
|
||||
/*Register THERM (0x80) register.RegisterDescription */
|
||||
#define THERM_THERM_HD_MASK 0x20
|
||||
#define THERM_THERM_HD_SHIFT 5
|
||||
#define THERM_THERM_TS_MASK 0x10
|
||||
#define THERM_THERM_TS_SHIFT 4
|
||||
#define THERM_THERM_HDSEL_MASK 0x0C
|
||||
#define THERM_THERM_HDSEL_SHIFT 2
|
||||
#define THERM_RSVD1_MASK 0x02
|
||||
#define THERM_RSVD1_SHIFT 1
|
||||
#define THERM_THERM_STATE_MASK 0x01
|
||||
#define THERM_THERM_STATE_SHIFT 0
|
||||
|
||||
|
||||
/*Register BBCH (0x80) register.RegisterDescription */
|
||||
#define BBCH_BBSEL_MASK 0x06
|
||||
#define BBCH_BBSEL_SHIFT 1
|
||||
#define BBCH_BBCHEN_MASK 0x01
|
||||
#define BBCH_BBCHEN_SHIFT 0
|
||||
|
||||
|
||||
/*Register DCDCCTRL (0x80) register.RegisterDescription */
|
||||
#define DCDCCTRL_VDD2_PSKIP_MASK 0x20
|
||||
#define DCDCCTRL_VDD2_PSKIP_SHIFT 5
|
||||
#define DCDCCTRL_VDD1_PSKIP_MASK 0x10
|
||||
#define DCDCCTRL_VDD1_PSKIP_SHIFT 4
|
||||
#define DCDCCTRL_VIO_PSKIP_MASK 0x08
|
||||
#define DCDCCTRL_VIO_PSKIP_SHIFT 3
|
||||
#define DCDCCTRL_DCDCCKEXT_MASK 0x04
|
||||
#define DCDCCTRL_DCDCCKEXT_SHIFT 2
|
||||
#define DCDCCTRL_DCDCCKSYNC_MASK 0x03
|
||||
#define DCDCCTRL_DCDCCKSYNC_SHIFT 0
|
||||
|
||||
|
||||
/*Register DEVCTRL (0x80) register.RegisterDescription */
|
||||
#define DEVCTRL_RTC_PWDN_MASK 0x40
|
||||
#define DEVCTRL_RTC_PWDN_SHIFT 6
|
||||
#define DEVCTRL_CK32K_CTRL_MASK 0x20
|
||||
#define DEVCTRL_CK32K_CTRL_SHIFT 5
|
||||
#define DEVCTRL_SR_CTL_I2C_SEL_MASK 0x10
|
||||
#define DEVCTRL_SR_CTL_I2C_SEL_SHIFT 4
|
||||
#define DEVCTRL_DEV_OFF_RST_MASK 0x08
|
||||
#define DEVCTRL_DEV_OFF_RST_SHIFT 3
|
||||
#define DEVCTRL_DEV_ON_MASK 0x04
|
||||
#define DEVCTRL_DEV_ON_SHIFT 2
|
||||
#define DEVCTRL_DEV_SLP_MASK 0x02
|
||||
#define DEVCTRL_DEV_SLP_SHIFT 1
|
||||
#define DEVCTRL_DEV_OFF_MASK 0x01
|
||||
#define DEVCTRL_DEV_OFF_SHIFT 0
|
||||
|
||||
|
||||
/*Register DEVCTRL2 (0x80) register.RegisterDescription */
|
||||
#define DEVCTRL2_TSLOT_LENGTH_MASK 0x30
|
||||
#define DEVCTRL2_TSLOT_LENGTH_SHIFT 4
|
||||
#define DEVCTRL2_SLEEPSIG_POL_MASK 0x08
|
||||
#define DEVCTRL2_SLEEPSIG_POL_SHIFT 3
|
||||
#define DEVCTRL2_PWON_LP_OFF_MASK 0x04
|
||||
#define DEVCTRL2_PWON_LP_OFF_SHIFT 2
|
||||
#define DEVCTRL2_PWON_LP_RST_MASK 0x02
|
||||
#define DEVCTRL2_PWON_LP_RST_SHIFT 1
|
||||
#define DEVCTRL2_IT_POL_MASK 0x01
|
||||
#define DEVCTRL2_IT_POL_SHIFT 0
|
||||
|
||||
|
||||
/*Register SLEEP_KEEP_LDO_ON (0x80) register.RegisterDescription */
|
||||
#define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK 0x80
|
||||
#define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT 7
|
||||
#define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK 0x40
|
||||
#define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT 6
|
||||
#define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK 0x20
|
||||
#define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT 5
|
||||
#define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK 0x10
|
||||
#define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT 4
|
||||
#define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK 0x08
|
||||
#define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT 3
|
||||
#define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK 0x04
|
||||
#define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT 2
|
||||
#define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK 0x02
|
||||
#define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT 1
|
||||
#define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK 0x01
|
||||
#define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT 0
|
||||
|
||||
|
||||
/*Register SLEEP_KEEP_RES_ON (0x80) register.RegisterDescription */
|
||||
#define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK 0x80
|
||||
#define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT 7
|
||||
#define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK 0x40
|
||||
#define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT 6
|
||||
#define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK 0x20
|
||||
#define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT 5
|
||||
#define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK 0x10
|
||||
#define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT 4
|
||||
#define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK 0x08
|
||||
#define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT 3
|
||||
#define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK 0x04
|
||||
#define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT 2
|
||||
#define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK 0x02
|
||||
#define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT 1
|
||||
#define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK 0x01
|
||||
#define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT 0
|
||||
|
||||
|
||||
/*Register SLEEP_SET_LDO_OFF (0x80) register.RegisterDescription */
|
||||
#define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK 0x80
|
||||
#define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT 7
|
||||
#define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK 0x40
|
||||
#define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT 6
|
||||
#define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK 0x20
|
||||
#define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT 5
|
||||
#define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK 0x10
|
||||
#define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT 4
|
||||
#define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK 0x08
|
||||
#define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT 3
|
||||
#define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK 0x04
|
||||
#define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT 2
|
||||
#define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK 0x02
|
||||
#define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT 1
|
||||
#define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK 0x01
|
||||
#define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT 0
|
||||
|
||||
|
||||
/*Register SLEEP_SET_RES_OFF (0x80) register.RegisterDescription */
|
||||
#define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK 0x80
|
||||
#define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT 7
|
||||
#define SLEEP_SET_RES_OFF_RSVD_MASK 0x60
|
||||
#define SLEEP_SET_RES_OFF_RSVD_SHIFT 5
|
||||
#define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK 0x10
|
||||
#define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT 4
|
||||
#define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK 0x08
|
||||
#define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT 3
|
||||
#define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK 0x04
|
||||
#define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT 2
|
||||
#define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK 0x02
|
||||
#define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT 1
|
||||
#define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK 0x01
|
||||
#define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT 0
|
||||
|
||||
|
||||
/*Register EN1_LDO_ASS (0x80) register.RegisterDescription */
|
||||
#define EN1_LDO_ASS_VDAC_EN1_MASK 0x80
|
||||
#define EN1_LDO_ASS_VDAC_EN1_SHIFT 7
|
||||
#define EN1_LDO_ASS_VPLL_EN1_MASK 0x40
|
||||
#define EN1_LDO_ASS_VPLL_EN1_SHIFT 6
|
||||
#define EN1_LDO_ASS_VAUX33_EN1_MASK 0x20
|
||||
#define EN1_LDO_ASS_VAUX33_EN1_SHIFT 5
|
||||
#define EN1_LDO_ASS_VAUX2_EN1_MASK 0x10
|
||||
#define EN1_LDO_ASS_VAUX2_EN1_SHIFT 4
|
||||
#define EN1_LDO_ASS_VAUX1_EN1_MASK 0x08
|
||||
#define EN1_LDO_ASS_VAUX1_EN1_SHIFT 3
|
||||
#define EN1_LDO_ASS_VDIG2_EN1_MASK 0x04
|
||||
#define EN1_LDO_ASS_VDIG2_EN1_SHIFT 2
|
||||
#define EN1_LDO_ASS_VDIG1_EN1_MASK 0x02
|
||||
#define EN1_LDO_ASS_VDIG1_EN1_SHIFT 1
|
||||
#define EN1_LDO_ASS_VMMC_EN1_MASK 0x01
|
||||
#define EN1_LDO_ASS_VMMC_EN1_SHIFT 0
|
||||
|
||||
|
||||
/*Register EN1_SMPS_ASS (0x80) register.RegisterDescription */
|
||||
#define EN1_SMPS_ASS_RSVD_MASK 0xE0
|
||||
#define EN1_SMPS_ASS_RSVD_SHIFT 5
|
||||
#define EN1_SMPS_ASS_SPARE_EN1_MASK 0x10
|
||||
#define EN1_SMPS_ASS_SPARE_EN1_SHIFT 4
|
||||
#define EN1_SMPS_ASS_VDD3_EN1_MASK 0x08
|
||||
#define EN1_SMPS_ASS_VDD3_EN1_SHIFT 3
|
||||
#define EN1_SMPS_ASS_VDD2_EN1_MASK 0x04
|
||||
#define EN1_SMPS_ASS_VDD2_EN1_SHIFT 2
|
||||
#define EN1_SMPS_ASS_VDD1_EN1_MASK 0x02
|
||||
#define EN1_SMPS_ASS_VDD1_EN1_SHIFT 1
|
||||
#define EN1_SMPS_ASS_VIO_EN1_MASK 0x01
|
||||
#define EN1_SMPS_ASS_VIO_EN1_SHIFT 0
|
||||
|
||||
|
||||
/*Register EN2_LDO_ASS (0x80) register.RegisterDescription */
|
||||
#define EN2_LDO_ASS_VDAC_EN2_MASK 0x80
|
||||
#define EN2_LDO_ASS_VDAC_EN2_SHIFT 7
|
||||
#define EN2_LDO_ASS_VPLL_EN2_MASK 0x40
|
||||
#define EN2_LDO_ASS_VPLL_EN2_SHIFT 6
|
||||
#define EN2_LDO_ASS_VAUX33_EN2_MASK 0x20
|
||||
#define EN2_LDO_ASS_VAUX33_EN2_SHIFT 5
|
||||
#define EN2_LDO_ASS_VAUX2_EN2_MASK 0x10
|
||||
#define EN2_LDO_ASS_VAUX2_EN2_SHIFT 4
|
||||
#define EN2_LDO_ASS_VAUX1_EN2_MASK 0x08
|
||||
#define EN2_LDO_ASS_VAUX1_EN2_SHIFT 3
|
||||
#define EN2_LDO_ASS_VDIG2_EN2_MASK 0x04
|
||||
#define EN2_LDO_ASS_VDIG2_EN2_SHIFT 2
|
||||
#define EN2_LDO_ASS_VDIG1_EN2_MASK 0x02
|
||||
#define EN2_LDO_ASS_VDIG1_EN2_SHIFT 1
|
||||
#define EN2_LDO_ASS_VMMC_EN2_MASK 0x01
|
||||
#define EN2_LDO_ASS_VMMC_EN2_SHIFT 0
|
||||
|
||||
|
||||
/*Register EN2_SMPS_ASS (0x80) register.RegisterDescription */
|
||||
#define EN2_SMPS_ASS_RSVD_MASK 0xE0
|
||||
#define EN2_SMPS_ASS_RSVD_SHIFT 5
|
||||
#define EN2_SMPS_ASS_SPARE_EN2_MASK 0x10
|
||||
#define EN2_SMPS_ASS_SPARE_EN2_SHIFT 4
|
||||
#define EN2_SMPS_ASS_VDD3_EN2_MASK 0x08
|
||||
#define EN2_SMPS_ASS_VDD3_EN2_SHIFT 3
|
||||
#define EN2_SMPS_ASS_VDD2_EN2_MASK 0x04
|
||||
#define EN2_SMPS_ASS_VDD2_EN2_SHIFT 2
|
||||
#define EN2_SMPS_ASS_VDD1_EN2_MASK 0x02
|
||||
#define EN2_SMPS_ASS_VDD1_EN2_SHIFT 1
|
||||
#define EN2_SMPS_ASS_VIO_EN2_MASK 0x01
|
||||
#define EN2_SMPS_ASS_VIO_EN2_SHIFT 0
|
||||
|
||||
|
||||
/*Register EN3_LDO_ASS (0x80) register.RegisterDescription */
|
||||
#define EN3_LDO_ASS_VDAC_EN3_MASK 0x80
|
||||
#define EN3_LDO_ASS_VDAC_EN3_SHIFT 7
|
||||
#define EN3_LDO_ASS_VPLL_EN3_MASK 0x40
|
||||
#define EN3_LDO_ASS_VPLL_EN3_SHIFT 6
|
||||
#define EN3_LDO_ASS_VAUX33_EN3_MASK 0x20
|
||||
#define EN3_LDO_ASS_VAUX33_EN3_SHIFT 5
|
||||
#define EN3_LDO_ASS_VAUX2_EN3_MASK 0x10
|
||||
#define EN3_LDO_ASS_VAUX2_EN3_SHIFT 4
|
||||
#define EN3_LDO_ASS_VAUX1_EN3_MASK 0x08
|
||||
#define EN3_LDO_ASS_VAUX1_EN3_SHIFT 3
|
||||
#define EN3_LDO_ASS_VDIG2_EN3_MASK 0x04
|
||||
#define EN3_LDO_ASS_VDIG2_EN3_SHIFT 2
|
||||
#define EN3_LDO_ASS_VDIG1_EN3_MASK 0x02
|
||||
#define EN3_LDO_ASS_VDIG1_EN3_SHIFT 1
|
||||
#define EN3_LDO_ASS_VMMC_EN3_MASK 0x01
|
||||
#define EN3_LDO_ASS_VMMC_EN3_SHIFT 0
|
||||
|
||||
|
||||
/*Register SPARE (0x80) register.RegisterDescription */
|
||||
#define SPARE_SPARE_MASK 0xFF
|
||||
#define SPARE_SPARE_SHIFT 0
|
||||
|
||||
|
||||
/*Register INT_STS (0x80) register.RegisterDescription */
|
||||
#define INT_STS_RTC_PERIOD_IT_MASK 0x80
|
||||
#define INT_STS_RTC_PERIOD_IT_SHIFT 7
|
||||
#define INT_STS_RTC_ALARM_IT_MASK 0x40
|
||||
#define INT_STS_RTC_ALARM_IT_SHIFT 6
|
||||
#define INT_STS_HOTDIE_IT_MASK 0x20
|
||||
#define INT_STS_HOTDIE_IT_SHIFT 5
|
||||
#define INT_STS_PWRHOLD_IT_MASK 0x10
|
||||
#define INT_STS_PWRHOLD_IT_SHIFT 4
|
||||
#define INT_STS_PWRON_LP_IT_MASK 0x08
|
||||
#define INT_STS_PWRON_LP_IT_SHIFT 3
|
||||
#define INT_STS_PWRON_IT_MASK 0x04
|
||||
#define INT_STS_PWRON_IT_SHIFT 2
|
||||
#define INT_STS_VMBHI_IT_MASK 0x02
|
||||
#define INT_STS_VMBHI_IT_SHIFT 1
|
||||
#define INT_STS_VMBDCH_IT_MASK 0x01
|
||||
#define INT_STS_VMBDCH_IT_SHIFT 0
|
||||
|
||||
|
||||
/*Register INT_MSK (0x80) register.RegisterDescription */
|
||||
#define INT_MSK_RTC_PERIOD_IT_MSK_MASK 0x80
|
||||
#define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT 7
|
||||
#define INT_MSK_RTC_ALARM_IT_MSK_MASK 0x40
|
||||
#define INT_MSK_RTC_ALARM_IT_MSK_SHIFT 6
|
||||
#define INT_MSK_HOTDIE_IT_MSK_MASK 0x20
|
||||
#define INT_MSK_HOTDIE_IT_MSK_SHIFT 5
|
||||
#define INT_MSK_PWRHOLD_IT_MSK_MASK 0x10
|
||||
#define INT_MSK_PWRHOLD_IT_MSK_SHIFT 4
|
||||
#define INT_MSK_PWRON_LP_IT_MSK_MASK 0x08
|
||||
#define INT_MSK_PWRON_LP_IT_MSK_SHIFT 3
|
||||
#define INT_MSK_PWRON_IT_MSK_MASK 0x04
|
||||
#define INT_MSK_PWRON_IT_MSK_SHIFT 2
|
||||
#define INT_MSK_VMBHI_IT_MSK_MASK 0x02
|
||||
#define INT_MSK_VMBHI_IT_MSK_SHIFT 1
|
||||
#define INT_MSK_VMBDCH_IT_MSK_MASK 0x01
|
||||
#define INT_MSK_VMBDCH_IT_MSK_SHIFT 0
|
||||
|
||||
|
||||
/*Register INT_STS2 (0x80) register.RegisterDescription */
|
||||
#define INT_STS2_GPIO3_F_IT_MASK 0x80
|
||||
#define INT_STS2_GPIO3_F_IT_SHIFT 7
|
||||
#define INT_STS2_GPIO3_R_IT_MASK 0x40
|
||||
#define INT_STS2_GPIO3_R_IT_SHIFT 6
|
||||
#define INT_STS2_GPIO2_F_IT_MASK 0x20
|
||||
#define INT_STS2_GPIO2_F_IT_SHIFT 5
|
||||
#define INT_STS2_GPIO2_R_IT_MASK 0x10
|
||||
#define INT_STS2_GPIO2_R_IT_SHIFT 4
|
||||
#define INT_STS2_GPIO1_F_IT_MASK 0x08
|
||||
#define INT_STS2_GPIO1_F_IT_SHIFT 3
|
||||
#define INT_STS2_GPIO1_R_IT_MASK 0x04
|
||||
#define INT_STS2_GPIO1_R_IT_SHIFT 2
|
||||
#define INT_STS2_GPIO0_F_IT_MASK 0x02
|
||||
#define INT_STS2_GPIO0_F_IT_SHIFT 1
|
||||
#define INT_STS2_GPIO0_R_IT_MASK 0x01
|
||||
#define INT_STS2_GPIO0_R_IT_SHIFT 0
|
||||
|
||||
|
||||
/*Register INT_MSK2 (0x80) register.RegisterDescription */
|
||||
#define INT_MSK2_GPIO3_F_IT_MSK_MASK 0x80
|
||||
#define INT_MSK2_GPIO3_F_IT_MSK_SHIFT 7
|
||||
#define INT_MSK2_GPIO3_R_IT_MSK_MASK 0x40
|
||||
#define INT_MSK2_GPIO3_R_IT_MSK_SHIFT 6
|
||||
#define INT_MSK2_GPIO2_F_IT_MSK_MASK 0x20
|
||||
#define INT_MSK2_GPIO2_F_IT_MSK_SHIFT 5
|
||||
#define INT_MSK2_GPIO2_R_IT_MSK_MASK 0x10
|
||||
#define INT_MSK2_GPIO2_R_IT_MSK_SHIFT 4
|
||||
#define INT_MSK2_GPIO1_F_IT_MSK_MASK 0x08
|
||||
#define INT_MSK2_GPIO1_F_IT_MSK_SHIFT 3
|
||||
#define INT_MSK2_GPIO1_R_IT_MSK_MASK 0x04
|
||||
#define INT_MSK2_GPIO1_R_IT_MSK_SHIFT 2
|
||||
#define INT_MSK2_GPIO0_F_IT_MSK_MASK 0x02
|
||||
#define INT_MSK2_GPIO0_F_IT_MSK_SHIFT 1
|
||||
#define INT_MSK2_GPIO0_R_IT_MSK_MASK 0x01
|
||||
#define INT_MSK2_GPIO0_R_IT_MSK_SHIFT 0
|
||||
|
||||
|
||||
/*Register INT_STS3 (0x80) register.RegisterDescription */
|
||||
#define INT_STS3_GPIO5_F_IT_MASK 0x08
|
||||
#define INT_STS3_GPIO5_F_IT_SHIFT 3
|
||||
#define INT_STS3_GPIO5_R_IT_MASK 0x04
|
||||
#define INT_STS3_GPIO5_R_IT_SHIFT 2
|
||||
#define INT_STS3_GPIO4_F_IT_MASK 0x02
|
||||
#define INT_STS3_GPIO4_F_IT_SHIFT 1
|
||||
#define INT_STS3_GPIO4_R_IT_MASK 0x01
|
||||
#define INT_STS3_GPIO4_R_IT_SHIFT 0
|
||||
|
||||
|
||||
/*Register INT_MSK3 (0x80) register.RegisterDescription */
|
||||
#define INT_MSK3_GPIO5_F_IT_MSK_MASK 0x08
|
||||
#define INT_MSK3_GPIO5_F_IT_MSK_SHIFT 3
|
||||
#define INT_MSK3_GPIO5_R_IT_MSK_MASK 0x04
|
||||
#define INT_MSK3_GPIO5_R_IT_MSK_SHIFT 2
|
||||
#define INT_MSK3_GPIO4_F_IT_MSK_MASK 0x02
|
||||
#define INT_MSK3_GPIO4_F_IT_MSK_SHIFT 1
|
||||
#define INT_MSK3_GPIO4_R_IT_MSK_MASK 0x01
|
||||
#define INT_MSK3_GPIO4_R_IT_MSK_SHIFT 0
|
||||
|
||||
|
||||
/*Register GPIO0 (0x80) register.RegisterDescription */
|
||||
#define GPIO0_GPIO_DEB_MASK 0x10
|
||||
#define GPIO0_GPIO_DEB_SHIFT 4
|
||||
#define GPIO0_GPIO_PUEN_MASK 0x08
|
||||
#define GPIO0_GPIO_PUEN_SHIFT 3
|
||||
#define GPIO0_GPIO_CFG_MASK 0x04
|
||||
#define GPIO0_GPIO_CFG_SHIFT 2
|
||||
#define GPIO0_GPIO_STS_MASK 0x02
|
||||
#define GPIO0_GPIO_STS_SHIFT 1
|
||||
#define GPIO0_GPIO_SET_MASK 0x01
|
||||
#define GPIO0_GPIO_SET_SHIFT 0
|
||||
|
||||
|
||||
/*Register GPIO1 (0x80) register.RegisterDescription */
|
||||
#define GPIO1_GPIO_DEB_MASK 0x10
|
||||
#define GPIO1_GPIO_DEB_SHIFT 4
|
||||
#define GPIO1_GPIO_PUEN_MASK 0x08
|
||||
#define GPIO1_GPIO_PUEN_SHIFT 3
|
||||
#define GPIO1_GPIO_CFG_MASK 0x04
|
||||
#define GPIO1_GPIO_CFG_SHIFT 2
|
||||
#define GPIO1_GPIO_STS_MASK 0x02
|
||||
#define GPIO1_GPIO_STS_SHIFT 1
|
||||
#define GPIO1_GPIO_SET_MASK 0x01
|
||||
#define GPIO1_GPIO_SET_SHIFT 0
|
||||
|
||||
|
||||
/*Register GPIO2 (0x80) register.RegisterDescription */
|
||||
#define GPIO2_GPIO_DEB_MASK 0x10
|
||||
#define GPIO2_GPIO_DEB_SHIFT 4
|
||||
#define GPIO2_GPIO_PUEN_MASK 0x08
|
||||
#define GPIO2_GPIO_PUEN_SHIFT 3
|
||||
#define GPIO2_GPIO_CFG_MASK 0x04
|
||||
#define GPIO2_GPIO_CFG_SHIFT 2
|
||||
#define GPIO2_GPIO_STS_MASK 0x02
|
||||
#define GPIO2_GPIO_STS_SHIFT 1
|
||||
#define GPIO2_GPIO_SET_MASK 0x01
|
||||
#define GPIO2_GPIO_SET_SHIFT 0
|
||||
|
||||
|
||||
/*Register GPIO3 (0x80) register.RegisterDescription */
|
||||
#define GPIO3_GPIO_DEB_MASK 0x10
|
||||
#define GPIO3_GPIO_DEB_SHIFT 4
|
||||
#define GPIO3_GPIO_PUEN_MASK 0x08
|
||||
#define GPIO3_GPIO_PUEN_SHIFT 3
|
||||
#define GPIO3_GPIO_CFG_MASK 0x04
|
||||
#define GPIO3_GPIO_CFG_SHIFT 2
|
||||
#define GPIO3_GPIO_STS_MASK 0x02
|
||||
#define GPIO3_GPIO_STS_SHIFT 1
|
||||
#define GPIO3_GPIO_SET_MASK 0x01
|
||||
#define GPIO3_GPIO_SET_SHIFT 0
|
||||
|
||||
|
||||
/*Register GPIO4 (0x80) register.RegisterDescription */
|
||||
#define GPIO4_GPIO_DEB_MASK 0x10
|
||||
#define GPIO4_GPIO_DEB_SHIFT 4
|
||||
#define GPIO4_GPIO_PUEN_MASK 0x08
|
||||
#define GPIO4_GPIO_PUEN_SHIFT 3
|
||||
#define GPIO4_GPIO_CFG_MASK 0x04
|
||||
#define GPIO4_GPIO_CFG_SHIFT 2
|
||||
#define GPIO4_GPIO_STS_MASK 0x02
|
||||
#define GPIO4_GPIO_STS_SHIFT 1
|
||||
#define GPIO4_GPIO_SET_MASK 0x01
|
||||
#define GPIO4_GPIO_SET_SHIFT 0
|
||||
|
||||
|
||||
/*Register GPIO5 (0x80) register.RegisterDescription */
|
||||
#define GPIO5_GPIO_DEB_MASK 0x10
|
||||
#define GPIO5_GPIO_DEB_SHIFT 4
|
||||
#define GPIO5_GPIO_PUEN_MASK 0x08
|
||||
#define GPIO5_GPIO_PUEN_SHIFT 3
|
||||
#define GPIO5_GPIO_CFG_MASK 0x04
|
||||
#define GPIO5_GPIO_CFG_SHIFT 2
|
||||
#define GPIO5_GPIO_STS_MASK 0x02
|
||||
#define GPIO5_GPIO_STS_SHIFT 1
|
||||
#define GPIO5_GPIO_SET_MASK 0x01
|
||||
#define GPIO5_GPIO_SET_SHIFT 0
|
||||
|
||||
|
||||
/*Register JTAGVERNUM (0x80) register.RegisterDescription */
|
||||
#define JTAGVERNUM_VERNUM_MASK 0x0F
|
||||
#define JTAGVERNUM_VERNUM_SHIFT 0
|
||||
|
||||
|
||||
/* IRQ Definitions */
|
||||
#define TPS65910_IRQ_VBAT_VMBDCH 0
|
||||
#define TPS65910_IRQ_VBAT_VMHI 1
|
||||
#define TPS65910_IRQ_PWRON 2
|
||||
#define TPS65910_IRQ_PWRON_LP 3
|
||||
#define TPS65910_IRQ_PWRHOLD 4
|
||||
#define TPS65910_IRQ_HOTDIE 5
|
||||
#define TPS65910_IRQ_RTC_ALARM 6
|
||||
#define TPS65910_IRQ_RTC_PERIOD 7
|
||||
#define TPS65910_IRQ_GPIO_R 8
|
||||
#define TPS65910_IRQ_GPIO_F 9
|
||||
#define TPS65910_NUM_IRQ 10
|
||||
|
||||
/* GPIO Register Definitions */
|
||||
#define TPS65910_GPIO_DEB BIT(2)
|
||||
#define TPS65910_GPIO_PUEN BIT(3)
|
||||
#define TPS65910_GPIO_CFG BIT(2)
|
||||
#define TPS65910_GPIO_STS BIT(1)
|
||||
#define TPS65910_GPIO_SET BIT(0)
|
||||
|
||||
/**
|
||||
* struct tps65910_board
|
||||
* Board platform data may be used to initialize regulators.
|
||||
*/
|
||||
|
||||
struct tps65910_board {
|
||||
struct regulator_init_data *tps65910_pmic_init_data;
|
||||
};
|
||||
|
||||
/**
|
||||
* struct tps65910 - tps65910 sub-driver chip access routines
|
||||
*/
|
||||
|
||||
struct tps65910 {
|
||||
struct device *dev;
|
||||
struct i2c_client *i2c_client;
|
||||
struct mutex io_mutex;
|
||||
int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest);
|
||||
int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src);
|
||||
|
||||
/* Client devices */
|
||||
struct tps65910_pmic *pmic;
|
||||
struct tps65910_rtc *rtc;
|
||||
struct tps65910_power *power;
|
||||
|
||||
/* GPIO Handling */
|
||||
struct gpio_chip gpio;
|
||||
|
||||
/* IRQ Handling */
|
||||
struct mutex irq_lock;
|
||||
int chip_irq;
|
||||
int irq_base;
|
||||
u16 irq_mask;
|
||||
};
|
||||
|
||||
struct tps65910_platform_data {
|
||||
int irq_base;
|
||||
};
|
||||
|
||||
int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
|
||||
int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
|
||||
|
||||
#endif /* __LINUX_MFD_TPS65910_H */
|
||||
Loading…
Reference in New Issue
Block a user