forked from Minki/linux
ARM: LPC32xx: serial.c: HW bug workaround
This patch fixes a HW bug by flushing RX FIFOs of the UARTs on init. It was ported from NXP's git.lpclinux.com tree. Signed-off-by: Roland Stigge <stigge@antcom.de> Cc: stable@vger.kernel.org
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@ -88,6 +88,7 @@ struct uartinit {
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char *uart_ck_name;
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u32 ck_mode_mask;
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void __iomem *pdiv_clk_reg;
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resource_size_t mapbase;
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};
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static struct uartinit uartinit_data[] __initdata = {
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@ -97,6 +98,7 @@ static struct uartinit uartinit_data[] __initdata = {
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.ck_mode_mask =
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LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 5),
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.pdiv_clk_reg = LPC32XX_CLKPWR_UART5_CLK_CTRL,
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.mapbase = LPC32XX_UART5_BASE,
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},
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#endif
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#ifdef CONFIG_ARCH_LPC32XX_UART3_SELECT
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@ -105,6 +107,7 @@ static struct uartinit uartinit_data[] __initdata = {
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.ck_mode_mask =
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LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 3),
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.pdiv_clk_reg = LPC32XX_CLKPWR_UART3_CLK_CTRL,
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.mapbase = LPC32XX_UART3_BASE,
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},
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#endif
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#ifdef CONFIG_ARCH_LPC32XX_UART4_SELECT
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@ -113,6 +116,7 @@ static struct uartinit uartinit_data[] __initdata = {
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.ck_mode_mask =
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LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 4),
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.pdiv_clk_reg = LPC32XX_CLKPWR_UART4_CLK_CTRL,
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.mapbase = LPC32XX_UART4_BASE,
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},
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#endif
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#ifdef CONFIG_ARCH_LPC32XX_UART6_SELECT
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@ -121,6 +125,7 @@ static struct uartinit uartinit_data[] __initdata = {
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.ck_mode_mask =
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LPC32XX_UART_CLKMODE_LOAD(LPC32XX_UART_CLKMODE_ON, 6),
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.pdiv_clk_reg = LPC32XX_CLKPWR_UART6_CLK_CTRL,
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.mapbase = LPC32XX_UART6_BASE,
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},
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#endif
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};
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@ -165,6 +170,19 @@ void __init lpc32xx_serial_init(void)
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/* pre-UART clock divider set to 1 */
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__raw_writel(0x0101, uartinit_data[i].pdiv_clk_reg);
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/*
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* Force a flush of the RX FIFOs to work around a
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* HW bug
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*/
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puart = uartinit_data[i].mapbase;
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__raw_writel(0xC1, LPC32XX_UART_IIR_FCR(puart));
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__raw_writel(0x00, LPC32XX_UART_DLL_FIFO(puart));
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j = LPC32XX_SUART_FIFO_SIZE;
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while (j--)
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tmp = __raw_readl(
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LPC32XX_UART_DLL_FIFO(puart));
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__raw_writel(0, LPC32XX_UART_IIR_FCR(puart));
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}
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/* This needs to be done after all UART clocks are setup */
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