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drm/i915/psr: Cache sink synchronization latency

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This value do not change overtime so better cache it than
fetch it every PSR enable.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180328223046.16125-8-jose.souza@intel.com
This commit is contained in:
José Roberto de Souza 2018-03-28 15:30:44 -07:00 committed by Rodrigo Vivi
parent fe36181be3
commit 26e5378d11
2 changed files with 17 additions and 12 deletions
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1
drivers/gpu/drm/i915/i915_drv.h
View File

@ -608,6 +608,7 @@ struct i915_psr {
bool alpm; bool alpm;
bool has_hw_tracking; bool has_hw_tracking;
bool psr2_enabled; bool psr2_enabled;
u8 sink_sync_latency;
void (*enable_source)(struct intel_dp *, void (*enable_source)(struct intel_dp *,
const struct intel_crtc_state *); const struct intel_crtc_state *);

28
drivers/gpu/drm/i915/intel_psr.c
View File

@ -122,6 +122,18 @@ static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
return alpm_caps & DP_ALPM_CAP; return alpm_caps & DP_ALPM_CAP;
} }
static u8 intel_dp_get_sink_sync_latency(struct intel_dp *intel_dp)
{
u8 val = 0;
if (drm_dp_dpcd_readb(&intel_dp->aux,
DP_SYNCHRONIZATION_LATENCY_IN_SINK, &val) == 1)
val &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
else
DRM_ERROR("Unable to get sink synchronization latency\n");
return val;
}
void intel_psr_init_dpcd(struct intel_dp *intel_dp) void intel_psr_init_dpcd(struct intel_dp *intel_dp)
{ {
struct drm_i915_private *dev_priv = struct drm_i915_private *dev_priv =
@ -158,6 +170,8 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp)
intel_dp_get_colorimetry_status(intel_dp); intel_dp_get_colorimetry_status(intel_dp);
dev_priv->psr.alpm = dev_priv->psr.alpm =
intel_dp_get_alpm_status(intel_dp); intel_dp_get_alpm_status(intel_dp);
dev_priv->psr.sink_sync_latency =
intel_dp_get_sink_sync_latency(intel_dp);
} }
} }
} }
@ -379,10 +393,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
* with the 5 or 6 idle patterns. * with the 5 or 6 idle patterns.
*/ */
uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames); uint32_t idle_frames = max(6, dev_priv->vbt.psr.idle_frames);
uint32_t val; u32 val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
uint8_t sink_latency;
val = idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
/* FIXME: selective update is probably totally broken because it doesn't /* FIXME: selective update is probably totally broken because it doesn't
* mesh at all with our frontbuffer tracking. And the hw alone isn't * mesh at all with our frontbuffer tracking. And the hw alone isn't
@ -392,14 +403,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
val |= EDP_Y_COORDINATE_VALID | EDP_Y_COORDINATE_ENABLE; val |= EDP_Y_COORDINATE_VALID | EDP_Y_COORDINATE_ENABLE;
} }
if (drm_dp_dpcd_readb(&intel_dp->aux, val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
DP_SYNCHRONIZATION_LATENCY_IN_SINK,
&sink_latency) == 1) {
sink_latency &= DP_MAX_RESYNC_FRAME_COUNT_MASK;
} else {
sink_latency = 0;
}
val |= EDP_PSR2_FRAME_BEFORE_SU(sink_latency + 1);
if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5) if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
val |= EDP_PSR2_TP2_TIME_2500; val |= EDP_PSR2_TP2_TIME_2500;