[POWERPC] Handle alignment faults on SPE load/store instructions
This adds code to handle alignment traps generated by the following SPE (signal processing engine) load/store instructions, by emulating the instruction in the kernel (as is done for other instructions that generate alignment traps): evldd[x] Vector Load Double Word into Double Word [Indexed] evldw[x] Vector Load Double into Two Words [Indexed] evldh[x] Vector Load Double into Four Half Words [Indexed] evlhhesplat[x] Vector Load Half Word into Half Words Even and Splat [Indexed] evlhhousplat[x] Vector Load Half Word into Half Word Odd Unsigned and Splat [Indexed] evlhhossplat[x] Vector Load Half Word into Half Word Odd Signed and Splat [Indexed] evlwhe[x] Vector Load Word into Two Half Words Even [Indexed] evlwhou[x] Vector Load Word into Two Half Words Odd Unsigned (zero-extended) [Indexed] evlwhos[x] Vector Load Word into Two Half Words Odd Signed (with sign extension) [Indexed] evlwwsplat[x] Vector Load Word into Word and Splat [Indexed] evlwhsplat[x] Vector Load Word into Two Half Words and Splat [Indexed] evstdd[x] Vector Store Double of Double [Indexed] evstdw[x] Vector Store Double of Two Words [Indexed] evstdh[x] Vector Store Double of Four Half Words [Indexed] evstwhe[x] Vector Store Word of Two Half Words from Even [Indexed] evstwho[x] Vector Store Word of Two Half Words from Odd [Indexed] evstwwe[x] Vector Store Word of Word from Even [Indexed] evstwwo[x] Vector Store Word of Word from Odd [Indexed] Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala
parent
f923473611
commit
26caeb2ee1
@ -46,6 +46,8 @@ struct aligninfo {
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#define S 0x40 /* single-precision fp or... */
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#define SX 0x40 /* ... byte count in XER */
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#define HARD 0x80 /* string, stwcx. */
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#define E4 0x40 /* SPE endianness is word */
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#define E8 0x80 /* SPE endianness is double word */
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/* DSISR bits reported for a DCBZ instruction: */
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#define DCBZ 0x5f /* 8xx/82xx dcbz faults when cache not enabled */
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@ -392,6 +394,248 @@ static int emulate_fp_pair(struct pt_regs *regs, unsigned char __user *addr,
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return 1; /* exception handled and fixed up */
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}
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#ifdef CONFIG_SPE
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static struct aligninfo spe_aligninfo[32] = {
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{ 8, LD+E8 }, /* 0 00 00: evldd[x] */
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{ 8, LD+E4 }, /* 0 00 01: evldw[x] */
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{ 8, LD }, /* 0 00 10: evldh[x] */
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INVALID, /* 0 00 11 */
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{ 2, LD }, /* 0 01 00: evlhhesplat[x] */
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INVALID, /* 0 01 01 */
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{ 2, LD }, /* 0 01 10: evlhhousplat[x] */
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{ 2, LD+SE }, /* 0 01 11: evlhhossplat[x] */
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{ 4, LD }, /* 0 10 00: evlwhe[x] */
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INVALID, /* 0 10 01 */
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{ 4, LD }, /* 0 10 10: evlwhou[x] */
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{ 4, LD+SE }, /* 0 10 11: evlwhos[x] */
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{ 4, LD+E4 }, /* 0 11 00: evlwwsplat[x] */
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INVALID, /* 0 11 01 */
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{ 4, LD }, /* 0 11 10: evlwhsplat[x] */
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INVALID, /* 0 11 11 */
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{ 8, ST+E8 }, /* 1 00 00: evstdd[x] */
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{ 8, ST+E4 }, /* 1 00 01: evstdw[x] */
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{ 8, ST }, /* 1 00 10: evstdh[x] */
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INVALID, /* 1 00 11 */
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INVALID, /* 1 01 00 */
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INVALID, /* 1 01 01 */
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INVALID, /* 1 01 10 */
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INVALID, /* 1 01 11 */
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{ 4, ST }, /* 1 10 00: evstwhe[x] */
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INVALID, /* 1 10 01 */
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{ 4, ST }, /* 1 10 10: evstwho[x] */
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INVALID, /* 1 10 11 */
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{ 4, ST+E4 }, /* 1 11 00: evstwwe[x] */
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INVALID, /* 1 11 01 */
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{ 4, ST+E4 }, /* 1 11 10: evstwwo[x] */
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INVALID, /* 1 11 11 */
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};
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#define EVLDD 0x00
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#define EVLDW 0x01
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#define EVLDH 0x02
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#define EVLHHESPLAT 0x04
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#define EVLHHOUSPLAT 0x06
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#define EVLHHOSSPLAT 0x07
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#define EVLWHE 0x08
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#define EVLWHOU 0x0A
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#define EVLWHOS 0x0B
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#define EVLWWSPLAT 0x0C
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#define EVLWHSPLAT 0x0E
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#define EVSTDD 0x10
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#define EVSTDW 0x11
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#define EVSTDH 0x12
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#define EVSTWHE 0x18
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#define EVSTWHO 0x1A
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#define EVSTWWE 0x1C
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#define EVSTWWO 0x1E
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/*
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* Emulate SPE loads and stores.
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* Only Book-E has these instructions, and it does true little-endian,
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* so we don't need the address swizzling.
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*/
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static int emulate_spe(struct pt_regs *regs, unsigned int reg,
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unsigned int instr)
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{
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int t, ret;
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union {
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u64 ll;
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u32 w[2];
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u16 h[4];
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u8 v[8];
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} data, temp;
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unsigned char __user *p, *addr;
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unsigned long *evr = ¤t->thread.evr[reg];
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unsigned int nb, flags;
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instr = (instr >> 1) & 0x1f;
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/* DAR has the operand effective address */
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addr = (unsigned char __user *)regs->dar;
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nb = spe_aligninfo[instr].len;
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flags = spe_aligninfo[instr].flags;
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/* Verify the address of the operand */
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if (unlikely(user_mode(regs) &&
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!access_ok((flags & ST ? VERIFY_WRITE : VERIFY_READ),
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addr, nb)))
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return -EFAULT;
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/* userland only */
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if (unlikely(!user_mode(regs)))
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return 0;
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flush_spe_to_thread(current);
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/* If we are loading, get the data from user space, else
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* get it from register values
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*/
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if (flags & ST) {
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data.ll = 0;
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switch (instr) {
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case EVSTDD:
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case EVSTDW:
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case EVSTDH:
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data.w[0] = *evr;
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data.w[1] = regs->gpr[reg];
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break;
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case EVSTWHE:
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data.h[2] = *evr >> 16;
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data.h[3] = regs->gpr[reg] >> 16;
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break;
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case EVSTWHO:
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data.h[2] = *evr & 0xffff;
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data.h[3] = regs->gpr[reg] & 0xffff;
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break;
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case EVSTWWE:
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data.w[1] = *evr;
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break;
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case EVSTWWO:
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data.w[1] = regs->gpr[reg];
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break;
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default:
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return -EINVAL;
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}
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} else {
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temp.ll = data.ll = 0;
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ret = 0;
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p = addr;
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switch (nb) {
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case 8:
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ret |= __get_user_inatomic(temp.v[0], p++);
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ret |= __get_user_inatomic(temp.v[1], p++);
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ret |= __get_user_inatomic(temp.v[2], p++);
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ret |= __get_user_inatomic(temp.v[3], p++);
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case 4:
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ret |= __get_user_inatomic(temp.v[4], p++);
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ret |= __get_user_inatomic(temp.v[5], p++);
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case 2:
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ret |= __get_user_inatomic(temp.v[6], p++);
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ret |= __get_user_inatomic(temp.v[7], p++);
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if (unlikely(ret))
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return -EFAULT;
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}
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switch (instr) {
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case EVLDD:
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case EVLDW:
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case EVLDH:
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data.ll = temp.ll;
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break;
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case EVLHHESPLAT:
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data.h[0] = temp.h[3];
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data.h[2] = temp.h[3];
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break;
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case EVLHHOUSPLAT:
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case EVLHHOSSPLAT:
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data.h[1] = temp.h[3];
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data.h[3] = temp.h[3];
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break;
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case EVLWHE:
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data.h[0] = temp.h[2];
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data.h[2] = temp.h[3];
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break;
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case EVLWHOU:
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case EVLWHOS:
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data.h[1] = temp.h[2];
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data.h[3] = temp.h[3];
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break;
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case EVLWWSPLAT:
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data.w[0] = temp.w[1];
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data.w[1] = temp.w[1];
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break;
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case EVLWHSPLAT:
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data.h[0] = temp.h[2];
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data.h[1] = temp.h[2];
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data.h[2] = temp.h[3];
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data.h[3] = temp.h[3];
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break;
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default:
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return -EINVAL;
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}
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}
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if (flags & SW) {
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switch (flags & 0xf0) {
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case E8:
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SWAP(data.v[0], data.v[7]);
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SWAP(data.v[1], data.v[6]);
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SWAP(data.v[2], data.v[5]);
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SWAP(data.v[3], data.v[4]);
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break;
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case E4:
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SWAP(data.v[0], data.v[3]);
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SWAP(data.v[1], data.v[2]);
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SWAP(data.v[4], data.v[7]);
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SWAP(data.v[5], data.v[6]);
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break;
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/* Its half word endian */
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default:
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SWAP(data.v[0], data.v[1]);
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SWAP(data.v[2], data.v[3]);
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SWAP(data.v[4], data.v[5]);
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SWAP(data.v[6], data.v[7]);
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break;
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}
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}
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if (flags & SE) {
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data.w[0] = (s16)data.h[1];
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data.w[1] = (s16)data.h[3];
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}
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/* Store result to memory or update registers */
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if (flags & ST) {
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ret = 0;
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p = addr;
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switch (nb) {
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case 8:
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ret |= __put_user_inatomic(data.v[0], p++);
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ret |= __put_user_inatomic(data.v[1], p++);
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ret |= __put_user_inatomic(data.v[2], p++);
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ret |= __put_user_inatomic(data.v[3], p++);
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case 4:
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ret |= __put_user_inatomic(data.v[4], p++);
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ret |= __put_user_inatomic(data.v[5], p++);
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case 2:
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ret |= __put_user_inatomic(data.v[6], p++);
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ret |= __put_user_inatomic(data.v[7], p++);
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}
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if (unlikely(ret))
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return -EFAULT;
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} else {
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*evr = data.w[0];
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regs->gpr[reg] = data.w[1];
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}
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return 1;
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}
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#endif /* CONFIG_SPE */
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/*
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* Called on alignment exception. Attempts to fixup
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@ -450,6 +694,12 @@ int fix_alignment(struct pt_regs *regs)
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/* extract the operation and registers from the dsisr */
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reg = (dsisr >> 5) & 0x1f; /* source/dest register */
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areg = dsisr & 0x1f; /* register to update */
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#ifdef CONFIG_SPE
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if ((instr >> 26) == 0x4)
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return emulate_spe(regs, reg, instr);
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#endif
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instr = (dsisr >> 10) & 0x7f;
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instr |= (dsisr >> 13) & 0x60;
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