leandrof/linux
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Allwinner clock changes for 4.17

Browse Source 
Our usual bunch of changes for the next merge window. The most significant
 addition is the support of the H6 clock unit. Other than that, there's a
 bunch of fixes for the video clocks on the H3 and H5, and some Kconfig
 cleanup.
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEE0VqZU19dR2zEVaqr0rTAlCFNr3QFAlqz020ACgkQ0rTAlCFN
 r3SrhQ//dCFkn/8f/KUlZBhdlVBMfZchqAfHKSuN8ie3Khyx5TsF5WW/AzgHrtV/
 VOiy89SEO/FHdJSz2P/lUgwzVUmv2+5nTLIDi6L9QASVA6gjsaarthrdhRldSFh6
 bMq0PjHL9bsUriazQmYbEPWNRvgIZ2eQtLg1/hTx3E07E3TnipnGGcfIFBB99hol
 RHNWmVP9lPfqRBQaKjVHWWWDcFG5laKN4axKpEgYP3K0zoIdYVjkjk2yqL+qTpxY
 waYB2iz6u6SaHxXCti5LPMNeeQSEBSeSLU7oJIQkALs3mVw1ArJGjQHCI6SEaeKQ
 OlLYUQHHjvKJSfzTmfRABhzSJQZokTkwJa1rfvG1uM13DaFI3p95Ggq/uDDCtixV
 QOuLGinCRpX/DstTmwRsoH0UGMnrrg7rR37Lb4a5UvCVUbH+I/3kOFjFKD65Je5Z
 wqsxjBei5SvEjS3W8Mxhd2SAMHaM5xtYol3m83JTb6EV853PyVw3fB3IntVoyqOz
 Lr2aQtDvVQ/2lBTc+nHAgVhcmGUA3/HjV4zK6o/zF1gGnDoEI0LlbnmZF2MuTtzQ
 bc7NrCKT3HR63Ul5YTGJsYGpx+VF5G44dRPRMQ4szaJI1X/W0LV7BRkOUM+VEasx
 AB7Yx2Qf+ITVDPmd5hzGH8QFM2IkMHWcgoeLsDRShGK6n0weLEc=
 =W4h1
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-clk-for-4.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner clock changes from Maxime Ripard:

Our usual bunch of changes for the next merge window. The most significant
addition is the support of the H6 clock unit. Other than that, there's a
bunch of fixes for the video clocks on the H3 and H5, and some Kconfig
cleanup.

* tag 'sunxi-clk-for-4.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux:
  clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU
  clk: sunxi-ng: add support for the Allwinner H6 CCU
  dt-bindings: add device tree binding for Allwinner H6 main CCU
  clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks
  clk: sunxi-ng: h3: h5: export CLK_PLL_VIDEO
  clk: sunxi-ng: h3: h5: Allow some clocks to set parent rate
  clk: sunxi-ng: h3: h5: Add minimal rate for video PLL
  clk: sunxi-ng: Add check for minimal rate to NM PLLs
  clk: sunxi-ng: Use u64 for calculation of nkmp rate
  clk: sunxi-ng: Mask nkmp factors when setting register
  clk: sunxi-ng: remove select on obsolete SUNXI_CCU_X kconfig name
This commit is contained in:
Stephen Boyd 2018-03-23 09:35:40 -07:00
commit 26b99db0b6
14 changed files with 1578 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
Documentation/devicetree/bindings/clock/sunxi-ccu.txt
View File

@ -20,6 +20,7 @@ Required properties :
- "allwinner,sun50i-a64-ccu"
- "allwinner,sun50i-a64-r-ccu"
- "allwinner,sun50i-h5-ccu"
- "allwinner,sun50i-h6-ccu"
- "nextthing,gr8-ccu"
- reg: Must contain the registers base address and length
@ -31,6 +32,9 @@ Required properties :
- #clock-cells : must contain 1
- #reset-cells : must contain 1
For the main CCU on H6, one more clock is needed:
- "iosc": the SoC's internal frequency oscillator
For the PRCM CCUs on A83T/H3/A64, two more clocks are needed:
- "pll-periph": the SoC's peripheral PLL from the main CCU
- "iosc": the SoC's internal frequency oscillator

12
drivers/clk/sunxi-ng/Kconfig
View File

@ -11,15 +11,13 @@ config SUN50I_A64_CCU
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
config SUN50I_H6_CCU
bool "Support for the Allwinner H6 CCU"
default ARM64 && ARCH_SUNXI
depends on (ARM64 && ARCH_SUNXI) || COMPILE_TEST
config SUN4I_A10_CCU
bool "Support for the Allwinner A10/A20 CCU"
select SUNXI_CCU_DIV
select SUNXI_CCU_MULT
select SUNXI_CCU_NK
select SUNXI_CCU_NKM
select SUNXI_CCU_NM
select SUNXI_CCU_MP
select SUNXI_CCU_PHASE
default MACH_SUN4I
default MACH_SUN7I
depends on MACH_SUN4I || MACH_SUN7I || COMPILE_TEST

1
drivers/clk/sunxi-ng/Makefile
View File

@ -22,6 +22,7 @@ lib-$(CONFIG_SUNXI_CCU) += ccu_mp.o
# SoC support
obj-$(CONFIG_SUN50I_A64_CCU) += ccu-sun50i-a64.o
obj-$(CONFIG_SUN50I_H6_CCU) += ccu-sun50i-h6.o
obj-$(CONFIG_SUN4I_A10_CCU) += ccu-sun4i-a10.o
obj-$(CONFIG_SUN5I_CCU) += ccu-sun5i.o
obj-$(CONFIG_SUN6I_A31_CCU) += ccu-sun6i-a31.o

1211
drivers/clk/sunxi-ng/ccu-sun50i-h6.c Normal file
View File

File diff suppressed because it is too large Load Diff

56
drivers/clk/sunxi-ng/ccu-sun50i-h6.h Normal file
View File

@ -0,0 +1,56 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2016 Icenowy Zheng <icenowy@aosc.io>
*/
#ifndef _CCU_SUN50I_H6_H_
#define _CCU_SUN50I_H6_H_
#include <dt-bindings/clock/sun50i-h6-ccu.h>
#include <dt-bindings/reset/sun50i-h6-ccu.h>
#define CLK_OSC12M 0
#define CLK_PLL_CPUX 1
#define CLK_PLL_DDR0 2
/* PLL_PERIPH0 exported for PRCM */
#define CLK_PLL_PERIPH0_2X 4
#define CLK_PLL_PERIPH0_4X 5
#define CLK_PLL_PERIPH1 6
#define CLK_PLL_PERIPH1_2X 7
#define CLK_PLL_PERIPH1_4X 8
#define CLK_PLL_GPU 9
#define CLK_PLL_VIDEO0 10
#define CLK_PLL_VIDEO0_4X 11
#define CLK_PLL_VIDEO1 12
#define CLK_PLL_VIDEO1_4X 13
#define CLK_PLL_VE 14
#define CLK_PLL_DE 15
#define CLK_PLL_HSIC 16
#define CLK_PLL_AUDIO_BASE 17
#define CLK_PLL_AUDIO 18
#define CLK_PLL_AUDIO_2X 19
#define CLK_PLL_AUDIO_4X 20
/* CPUX clock exported for DVFS */
#define CLK_AXI 22
#define CLK_CPUX_APB 23
#define CLK_PSI_AHB1_AHB2 24
#define CLK_AHB3 25
/* APB1 clock exported for PIO */
#define CLK_APB2 27
#define CLK_MBUS 28
/* All module clocks and bus gates are exported except DRAM */
#define CLK_DRAM 52
#define CLK_BUS_DRAM 60
#define CLK_NUMBER (CLK_BUS_HDCP + 1)
#endif /* _CCU_SUN50I_H6_H_ */

32
drivers/clk/sunxi-ng/ccu-sun8i-h3.c
View File

@ -69,17 +69,18 @@ static SUNXI_CCU_NM_WITH_SDM_GATE_LOCK(pll_audio_base_clk, "pll-audio-base",
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video_clk, "pll-video",
"osc24M", 0x0010,
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video_clk, "pll-video",
"osc24M", 0x0010,
192000000, /* Minimum rate */
8, 7, /* N */
0, 4, /* M */
BIT(24), /* frac enable */
BIT(25), /* frac select */
270000000, /* frac rate 0 */
297000000, /* frac rate 1 */
BIT(31), /* gate */
BIT(28), /* lock */
CLK_SET_RATE_UNGATE);
static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve",
"osc24M", 0x0018,
@ -451,11 +452,13 @@ static SUNXI_CCU_GATE(dram_ts_clk, "dram-ts", "dram",
static const char * const de_parents[] = { "pll-periph0-2x", "pll-de" };
static SUNXI_CCU_M_WITH_MUX_GATE(de_clk, "de", de_parents,
0x104, 0, 4, 24, 3, BIT(31), 0);
0x104, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static const char * const tcon_parents[] = { "pll-video" };
static SUNXI_CCU_M_WITH_MUX_GATE(tcon_clk, "tcon", tcon_parents,
0x118, 0, 4, 24, 3, BIT(31), 0);
0x118, 0, 4, 24, 3, BIT(31),
CLK_SET_RATE_PARENT);
static const char * const tve_parents[] = { "pll-de", "pll-periph1" };
static SUNXI_CCU_M_WITH_MUX_GATE(tve_clk, "tve", tve_parents,
@ -486,7 +489,8 @@ static SUNXI_CCU_GATE(avs_clk, "avs", "osc24M",
static const char * const hdmi_parents[] = { "pll-video" };
static SUNXI_CCU_M_WITH_MUX_GATE(hdmi_clk, "hdmi", hdmi_parents,
0x150, 0, 4, 24, 2, BIT(31), 0);
0x150, 0, 4, 24, 2, BIT(31),
CLK_SET_RATE_PARENT);
static SUNXI_CCU_GATE(hdmi_ddc_clk, "hdmi-ddc", "osc24M",
0x154, BIT(31), 0);

4
drivers/clk/sunxi-ng/ccu-sun8i-h3.h
View File

@ -26,7 +26,9 @@
#define CLK_PLL_AUDIO_2X 3
#define CLK_PLL_AUDIO_4X 4
#define CLK_PLL_AUDIO_8X 5
#define CLK_PLL_VIDEO 6
/* PLL_VIDEO is exported */
#define CLK_PLL_VE 7
#define CLK_PLL_DDR 8

56
drivers/clk/sunxi-ng/ccu_nkmp.c
View File

@ -20,6 +20,18 @@ struct _ccu_nkmp {
unsigned long p, min_p, max_p;
};
static unsigned long ccu_nkmp_calc_rate(unsigned long parent,
unsigned long n, unsigned long k,
unsigned long m, unsigned long p)
{
u64 rate = parent;
rate *= n * k;
do_div(rate, m * p);
return rate;
}
static void ccu_nkmp_find_best(unsigned long parent, unsigned long rate,
struct _ccu_nkmp *nkmp)
{
@ -33,7 +45,9 @@ static void ccu_nkmp_find_best(unsigned long parent, unsigned long rate,
for (_p = nkmp->min_p; _p <= nkmp->max_p; _p <<= 1) {
unsigned long tmp_rate;
tmp_rate = parent * _n * _k / (_m * _p);
tmp_rate = ccu_nkmp_calc_rate(parent,
_n, _k,
_m, _p);
if (tmp_rate > rate)
continue;
@ -81,7 +95,7 @@ static unsigned long ccu_nkmp_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
unsigned long n, m, k, p;
unsigned long n, m, k, p, rate;
u32 reg;
reg = readl(nkmp->common.base + nkmp->common.reg);
@ -107,7 +121,11 @@ static unsigned long ccu_nkmp_recalc_rate(struct clk_hw *hw,
p = reg >> nkmp->p.shift;
p &= (1 << nkmp->p.width) - 1;
return (parent_rate * n * k >> p) / m;
rate = ccu_nkmp_calc_rate(parent_rate, n, k, m, 1 << p);
if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nkmp->fixed_post_div;
return rate;
}
static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
@ -116,6 +134,9 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
struct _ccu_nkmp _nkmp;
if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= nkmp->fixed_post_div;
_nkmp.min_n = nkmp->n.min ?: 1;
_nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width;
_nkmp.min_k = nkmp->k.min ?: 1;
@ -127,17 +148,26 @@ static long ccu_nkmp_round_rate(struct clk_hw *hw, unsigned long rate,
ccu_nkmp_find_best(*parent_rate, rate, &_nkmp);
return *parent_rate * _nkmp.n * _nkmp.k / (_nkmp.m * _nkmp.p);
rate = ccu_nkmp_calc_rate(*parent_rate, _nkmp.n, _nkmp.k,
_nkmp.m, _nkmp.p);
if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate = rate / nkmp->fixed_post_div;
return rate;
}
static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct ccu_nkmp *nkmp = hw_to_ccu_nkmp(hw);
u32 n_mask, k_mask, m_mask, p_mask;
struct _ccu_nkmp _nkmp;
unsigned long flags;
u32 reg;
if (nkmp->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate = rate * nkmp->fixed_post_div;
_nkmp.min_n = nkmp->n.min ?: 1;
_nkmp.max_n = nkmp->n.max ?: 1 << nkmp->n.width;
_nkmp.min_k = nkmp->k.min ?: 1;
@ -149,18 +179,20 @@ static int ccu_nkmp_set_rate(struct clk_hw *hw, unsigned long rate,
ccu_nkmp_find_best(parent_rate, rate, &_nkmp);
n_mask = GENMASK(nkmp->n.width + nkmp->n.shift - 1, nkmp->n.shift);
k_mask = GENMASK(nkmp->k.width + nkmp->k.shift - 1, nkmp->k.shift);
m_mask = GENMASK(nkmp->m.width + nkmp->m.shift - 1, nkmp->m.shift);
p_mask = GENMASK(nkmp->p.width + nkmp->p.shift - 1, nkmp->p.shift);
spin_lock_irqsave(nkmp->common.lock, flags);
reg = readl(nkmp->common.base + nkmp->common.reg);
reg &= ~GENMASK(nkmp->n.width + nkmp->n.shift - 1, nkmp->n.shift);
reg &= ~GENMASK(nkmp->k.width + nkmp->k.shift - 1, nkmp->k.shift);
reg &= ~GENMASK(nkmp->m.width + nkmp->m.shift - 1, nkmp->m.shift);
reg &= ~GENMASK(nkmp->p.width + nkmp->p.shift - 1, nkmp->p.shift);
reg &= ~(n_mask | k_mask | m_mask | p_mask);
reg |= (_nkmp.n - nkmp->n.offset) << nkmp->n.shift;
reg |= (_nkmp.k - nkmp->k.offset) << nkmp->k.shift;
reg |= (_nkmp.m - nkmp->m.offset) << nkmp->m.shift;
reg |= ilog2(_nkmp.p) << nkmp->p.shift;
reg |= ((_nkmp.n - nkmp->n.offset) << nkmp->n.shift) & n_mask;
reg |= ((_nkmp.k - nkmp->k.offset) << nkmp->k.shift) & k_mask;
reg |= ((_nkmp.m - nkmp->m.offset) << nkmp->m.shift) & m_mask;
reg |= (ilog2(_nkmp.p) << nkmp->p.shift) & p_mask;
writel(reg, nkmp->common.base + nkmp->common.reg);

2
drivers/clk/sunxi-ng/ccu_nkmp.h
View File

@ -34,6 +34,8 @@ struct ccu_nkmp {
struct ccu_div_internal m;
struct ccu_div_internal p;
unsigned int fixed_post_div;
struct ccu_common common;
};

7
drivers/clk/sunxi-ng/ccu_nm.c
View File

@ -117,6 +117,13 @@ static long ccu_nm_round_rate(struct clk_hw *hw, unsigned long rate,
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate *= nm->fixed_post_div;
if (rate < nm->min_rate) {
rate = nm->min_rate;
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nm->fixed_post_div;
return rate;
}
if (ccu_frac_helper_has_rate(&nm->common, &nm->frac, rate)) {
if (nm->common.features & CCU_FEATURE_FIXED_POSTDIV)
rate /= nm->fixed_post_div;

27
drivers/clk/sunxi-ng/ccu_nm.h
View File

@ -37,6 +37,7 @@ struct ccu_nm {
struct ccu_sdm_internal sdm;
unsigned int fixed_post_div;
unsigned int min_rate;
struct ccu_common common;
};
@ -88,6 +89,32 @@ struct ccu_nm {
}, \
}
#define SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(_struct, _name, _parent, \
_reg, _min_rate, \
_nshift, _nwidth, \
_mshift, _mwidth, \
_frac_en, _frac_sel, \
_frac_rate_0, _frac_rate_1,\
_gate, _lock, _flags) \
struct ccu_nm _struct = { \
.enable = _gate, \
.lock = _lock, \
.n = _SUNXI_CCU_MULT(_nshift, _nwidth), \
.m = _SUNXI_CCU_DIV(_mshift, _mwidth), \
.frac = _SUNXI_CCU_FRAC(_frac_en, _frac_sel, \
_frac_rate_0, \
_frac_rate_1), \
.min_rate = _min_rate, \
.common = { \
.reg = _reg, \
.features = CCU_FEATURE_FRACTIONAL, \
.hw.init = CLK_HW_INIT(_name, \
_parent, \
&ccu_nm_ops, \
_flags), \
}, \
}
#define SUNXI_CCU_NM_WITH_GATE_LOCK(_struct, _name, _parent, _reg, \
_nshift, _nwidth, \
_mshift, _mwidth, \

125
include/dt-bindings/clock/sun50i-h6-ccu.h Normal file
View File

@ -0,0 +1,125 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
*/
#ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_
#define _DT_BINDINGS_CLK_SUN50I_H6_H_
#define CLK_PLL_PERIPH0 3
#define CLK_CPUX 21
#define CLK_APB1 26
#define CLK_DE 29
#define CLK_BUS_DE 30
#define CLK_DEINTERLACE 31
#define CLK_BUS_DEINTERLACE 32
#define CLK_GPU 33
#define CLK_BUS_GPU 34
#define CLK_CE 35
#define CLK_BUS_CE 36
#define CLK_VE 37
#define CLK_BUS_VE 38
#define CLK_EMCE 39
#define CLK_BUS_EMCE 40
#define CLK_VP9 41
#define CLK_BUS_VP9 42
#define CLK_BUS_DMA 43
#define CLK_BUS_MSGBOX 44
#define CLK_BUS_SPINLOCK 45
#define CLK_BUS_HSTIMER 46
#define CLK_AVS 47
#define CLK_BUS_DBG 48
#define CLK_BUS_PSI 49
#define CLK_BUS_PWM 50
#define CLK_BUS_IOMMU 51
#define CLK_MBUS_DMA 53
#define CLK_MBUS_VE 54
#define CLK_MBUS_CE 55
#define CLK_MBUS_TS 56
#define CLK_MBUS_NAND 57
#define CLK_MBUS_CSI 58
#define CLK_MBUS_DEINTERLACE 59
#define CLK_NAND0 61
#define CLK_NAND1 62
#define CLK_BUS_NAND 63
#define CLK_MMC0 64
#define CLK_MMC1 65
#define CLK_MMC2 66
#define CLK_BUS_MMC0 67
#define CLK_BUS_MMC1 68
#define CLK_BUS_MMC2 69
#define CLK_BUS_UART0 70
#define CLK_BUS_UART1 71
#define CLK_BUS_UART2 72
#define CLK_BUS_UART3 73
#define CLK_BUS_I2C0 74
#define CLK_BUS_I2C1 75
#define CLK_BUS_I2C2 76
#define CLK_BUS_I2C3 77
#define CLK_BUS_SCR0 78
#define CLK_BUS_SCR1 79
#define CLK_SPI0 80
#define CLK_SPI1 81
#define CLK_BUS_SPI0 82
#define CLK_BUS_SPI1 83
#define CLK_BUS_EMAC 84
#define CLK_TS 85
#define CLK_BUS_TS 86
#define CLK_IR_TX 87
#define CLK_BUS_IR_TX 88
#define CLK_BUS_THS 89
#define CLK_I2S3 90
#define CLK_I2S0 91
#define CLK_I2S1 92
#define CLK_I2S2 93
#define CLK_BUS_I2S0 94
#define CLK_BUS_I2S1 95
#define CLK_BUS_I2S2 96
#define CLK_BUS_I2S3 97
#define CLK_SPDIF 98
#define CLK_BUS_SPDIF 99
#define CLK_DMIC 100
#define CLK_BUS_DMIC 101
#define CLK_AUDIO_HUB 102
#define CLK_BUS_AUDIO_HUB 103
#define CLK_USB_OHCI0 104
#define CLK_USB_PHY0 105
#define CLK_USB_PHY1 106
#define CLK_USB_OHCI3 107
#define CLK_USB_PHY3 108
#define CLK_USB_HSIC_12M 109
#define CLK_USB_HSIC 110
#define CLK_BUS_OHCI0 111
#define CLK_BUS_OHCI3 112
#define CLK_BUS_EHCI0 113
#define CLK_BUS_XHCI 114
#define CLK_BUS_EHCI3 115
#define CLK_BUS_OTG 116
#define CLK_PCIE_REF_100M 117
#define CLK_PCIE_REF 118
#define CLK_PCIE_REF_OUT 119
#define CLK_PCIE_MAXI 120
#define CLK_PCIE_AUX 121
#define CLK_BUS_PCIE 122
#define CLK_HDMI 123
#define CLK_HDMI_SLOW 124
#define CLK_HDMI_CEC 125
#define CLK_BUS_HDMI 126
#define CLK_BUS_TCON_TOP 127
#define CLK_TCON_LCD0 128
#define CLK_BUS_TCON_LCD0 129
#define CLK_TCON_TV0 130
#define CLK_BUS_TCON_TV0 131
#define CLK_CSI_CCI 132
#define CLK_CSI_TOP 133
#define CLK_CSI_MCLK 134
#define CLK_BUS_CSI 135
#define CLK_HDCP 136
#define CLK_BUS_HDCP 137
#endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */

2
include/dt-bindings/clock/sun8i-h3-ccu.h
View File

@ -43,6 +43,8 @@
#ifndef _DT_BINDINGS_CLK_SUN8I_H3_H_
#define _DT_BINDINGS_CLK_SUN8I_H3_H_
#define CLK_PLL_VIDEO 6
#define CLK_PLL_PERIPH0 9
#define CLK_CPUX 14

73
include/dt-bindings/reset/sun50i-h6-ccu.h Normal file
View File

@ -0,0 +1,73 @@
// SPDX-License-Identifier: (GPL-2.0+ or MIT)
/*
* Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
*/
#ifndef _DT_BINDINGS_RESET_SUN50I_H6_H_
#define _DT_BINDINGS_RESET_SUN50I_H6_H_
#define RST_MBUS 0
#define RST_BUS_DE 1
#define RST_BUS_DEINTERLACE 2
#define RST_BUS_GPU 3
#define RST_BUS_CE 4
#define RST_BUS_VE 5
#define RST_BUS_EMCE 6
#define RST_BUS_VP9 7
#define RST_BUS_DMA 8
#define RST_BUS_MSGBOX 9
#define RST_BUS_SPINLOCK 10
#define RST_BUS_HSTIMER 11
#define RST_BUS_DBG 12
#define RST_BUS_PSI 13
#define RST_BUS_PWM 14
#define RST_BUS_IOMMU 15
#define RST_BUS_DRAM 16
#define RST_BUS_NAND 17
#define RST_BUS_MMC0 18
#define RST_BUS_MMC1 19
#define RST_BUS_MMC2 20
#define RST_BUS_UART0 21
#define RST_BUS_UART1 22
#define RST_BUS_UART2 23
#define RST_BUS_UART3 24
#define RST_BUS_I2C0 25
#define RST_BUS_I2C1 26
#define RST_BUS_I2C2 27
#define RST_BUS_I2C3 28
#define RST_BUS_SCR0 29
#define RST_BUS_SCR1 30
#define RST_BUS_SPI0 31
#define RST_BUS_SPI1 32
#define RST_BUS_EMAC 33
#define RST_BUS_TS 34
#define RST_BUS_IR_TX 35
#define RST_BUS_THS 36
#define RST_BUS_I2S0 37
#define RST_BUS_I2S1 38
#define RST_BUS_I2S2 39
#define RST_BUS_I2S3 40
#define RST_BUS_SPDIF 41
#define RST_BUS_DMIC 42
#define RST_BUS_AUDIO_HUB 43
#define RST_USB_PHY0 44
#define RST_USB_PHY1 45
#define RST_USB_PHY3 46
#define RST_USB_HSIC 47
#define RST_BUS_OHCI0 48
#define RST_BUS_OHCI3 49
#define RST_BUS_EHCI0 50
#define RST_BUS_XHCI 51
#define RST_BUS_EHCI3 52
#define RST_BUS_OTG 53
#define RST_BUS_PCIE 54
#define RST_PCIE_POWERUP 55
#define RST_BUS_HDMI 56
#define RST_BUS_HDMI_SUB 57
#define RST_BUS_TCON_TOP 58
#define RST_BUS_TCON_LCD0 59
#define RST_BUS_TCON_TV0 60
#define RST_BUS_CSI 61
#define RST_BUS_HDCP 62
#endif /* _DT_BINDINGS_RESET_SUN50I_H6_H_ */