forked from Minki/linux
Merge branch 'mt7986-support'
Jakub Kicinski says: ==================== introduce mt7986 ethernet support Add support for mt7986-eth driver available on mt7986 soc. Changes since v2: - rely on GFP_KERNEL whenever possible - define mtk_reg_map struct to introduce soc register map and avoid macros - improve comments Changes since v1: - drop SRAM option - convert ring->dma to void - convert scratch_ring to void - enable port4 - fix irq dts bindings - drop gmac1 support from mt7986a-rfb dts for the moment ==================== Acked-by: Jakub Kicinski <kuba@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
commit
265f58f60a
@ -21,6 +21,7 @@ properties:
|
||||
- mediatek,mt7623-eth
|
||||
- mediatek,mt7622-eth
|
||||
- mediatek,mt7629-eth
|
||||
- mediatek,mt7986-eth
|
||||
- ralink,rt5350-eth
|
||||
|
||||
reg:
|
||||
@ -28,7 +29,7 @@ properties:
|
||||
|
||||
interrupts:
|
||||
minItems: 3
|
||||
maxItems: 3
|
||||
maxItems: 4
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
@ -88,6 +89,9 @@ allOf:
|
||||
- mediatek,mt7623-eth
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
maxItems: 3
|
||||
|
||||
clocks:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
@ -112,6 +116,9 @@ allOf:
|
||||
const: mediatek,mt7622-eth
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
maxItems: 3
|
||||
|
||||
clocks:
|
||||
minItems: 11
|
||||
maxItems: 11
|
||||
@ -155,6 +162,9 @@ allOf:
|
||||
const: mediatek,mt7629-eth
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
maxItems: 3
|
||||
|
||||
clocks:
|
||||
minItems: 17
|
||||
maxItems: 17
|
||||
@ -189,6 +199,42 @@ allOf:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt7986-eth
|
||||
then:
|
||||
properties:
|
||||
interrupts:
|
||||
minItems: 4
|
||||
|
||||
clocks:
|
||||
minItems: 15
|
||||
maxItems: 15
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: fe
|
||||
- const: gp2
|
||||
- const: gp1
|
||||
- const: wocpu1
|
||||
- const: wocpu0
|
||||
- const: sgmii_tx250m
|
||||
- const: sgmii_rx250m
|
||||
- const: sgmii_cdr_ref
|
||||
- const: sgmii_cdr_fb
|
||||
- const: sgmii2_tx250m
|
||||
- const: sgmii2_rx250m
|
||||
- const: sgmii2_cdr_ref
|
||||
- const: sgmii2_cdr_fb
|
||||
- const: netsys0
|
||||
- const: netsys1
|
||||
|
||||
mediatek,sgmiisys:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
|
||||
patternProperties:
|
||||
"^mac@[0-1]$":
|
||||
type: object
|
||||
@ -219,7 +265,6 @@ required:
|
||||
- interrupts
|
||||
- clocks
|
||||
- clock-names
|
||||
- power-domains
|
||||
- mediatek,ethsys
|
||||
|
||||
unevaluatedProperties: false
|
||||
@ -295,3 +340,95 @@ examples:
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/clock/mt7622-clk.h>
|
||||
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
eth: ethernet@15100000 {
|
||||
#define CLK_ETH_FE_EN 0
|
||||
#define CLK_ETH_WOCPU1_EN 3
|
||||
#define CLK_ETH_WOCPU0_EN 4
|
||||
#define CLK_TOP_NETSYS_SEL 43
|
||||
#define CLK_TOP_NETSYS_500M_SEL 44
|
||||
#define CLK_TOP_NETSYS_2X_SEL 46
|
||||
#define CLK_TOP_SGM_325M_SEL 47
|
||||
#define CLK_APMIXED_NET2PLL 1
|
||||
#define CLK_APMIXED_SGMPLL 3
|
||||
|
||||
compatible = "mediatek,mt7986-eth";
|
||||
reg = <0 0x15100000 0 0x80000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <ðsys CLK_ETH_FE_EN>,
|
||||
<ðsys CLK_ETH_GP2_EN>,
|
||||
<ðsys CLK_ETH_GP1_EN>,
|
||||
<ðsys CLK_ETH_WOCPU1_EN>,
|
||||
<ðsys CLK_ETH_WOCPU0_EN>,
|
||||
<&sgmiisys0 CLK_SGMII_TX250M_EN>,
|
||||
<&sgmiisys0 CLK_SGMII_RX250M_EN>,
|
||||
<&sgmiisys0 CLK_SGMII_CDR_REF>,
|
||||
<&sgmiisys0 CLK_SGMII_CDR_FB>,
|
||||
<&sgmiisys1 CLK_SGMII_TX250M_EN>,
|
||||
<&sgmiisys1 CLK_SGMII_RX250M_EN>,
|
||||
<&sgmiisys1 CLK_SGMII_CDR_REF>,
|
||||
<&sgmiisys1 CLK_SGMII_CDR_FB>,
|
||||
<&topckgen CLK_TOP_NETSYS_SEL>,
|
||||
<&topckgen CLK_TOP_NETSYS_SEL>;
|
||||
clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
|
||||
"sgmii_tx250m", "sgmii_rx250m",
|
||||
"sgmii_cdr_ref", "sgmii_cdr_fb",
|
||||
"sgmii2_tx250m", "sgmii2_rx250m",
|
||||
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
|
||||
"netsys0", "netsys1";
|
||||
mediatek,ethsys = <ðsys>;
|
||||
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
|
||||
assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
|
||||
<&topckgen CLK_TOP_SGM_325M_SEL>;
|
||||
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
|
||||
<&apmixedsys CLK_APMIXED_SGMPLL>;
|
||||
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mdio: mdio-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy5: ethernet-phy@0 {
|
||||
compatible = "ethernet-phy-id67c9.de0a";
|
||||
phy-mode = "2500base-x";
|
||||
reset-gpios = <&pio 6 1>;
|
||||
reset-deassert-us = <20000>;
|
||||
reg = <5>;
|
||||
};
|
||||
|
||||
phy6: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-id67c9.de0a";
|
||||
phy-mode = "2500base-x";
|
||||
reg = <6>;
|
||||
};
|
||||
};
|
||||
|
||||
mac0: mac@0 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
phy-mode = "2500base-x";
|
||||
phy-handle = <&phy5>;
|
||||
reg = <0>;
|
||||
};
|
||||
|
||||
mac1: mac@1 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
phy-mode = "2500base-x";
|
||||
phy-handle = <&phy6>;
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
@ -25,6 +25,80 @@
|
||||
};
|
||||
};
|
||||
|
||||
ð {
|
||||
status = "okay";
|
||||
|
||||
gmac0: mac@0 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <0>;
|
||||
phy-mode = "2500base-x";
|
||||
|
||||
fixed-link {
|
||||
speed = <2500>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
|
||||
mdio: mdio-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&mdio {
|
||||
switch: switch@0 {
|
||||
compatible = "mediatek,mt7531";
|
||||
reg = <31>;
|
||||
reset-gpios = <&pio 5 0>;
|
||||
};
|
||||
};
|
||||
|
||||
&switch {
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan0";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
label = "cpu";
|
||||
ethernet = <&gmac0>;
|
||||
phy-mode = "2500base-x";
|
||||
|
||||
fixed-link {
|
||||
speed = <2500>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
@ -222,6 +222,45 @@
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
eth: ethernet@15100000 {
|
||||
compatible = "mediatek,mt7986-eth";
|
||||
reg = <0 0x15100000 0 0x80000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <ðsys CLK_ETH_FE_EN>,
|
||||
<ðsys CLK_ETH_GP2_EN>,
|
||||
<ðsys CLK_ETH_GP1_EN>,
|
||||
<ðsys CLK_ETH_WOCPU1_EN>,
|
||||
<ðsys CLK_ETH_WOCPU0_EN>,
|
||||
<&sgmiisys0 CLK_SGMII0_TX250M_EN>,
|
||||
<&sgmiisys0 CLK_SGMII0_RX250M_EN>,
|
||||
<&sgmiisys0 CLK_SGMII0_CDR_REF>,
|
||||
<&sgmiisys0 CLK_SGMII0_CDR_FB>,
|
||||
<&sgmiisys1 CLK_SGMII1_TX250M_EN>,
|
||||
<&sgmiisys1 CLK_SGMII1_RX250M_EN>,
|
||||
<&sgmiisys1 CLK_SGMII1_CDR_REF>,
|
||||
<&sgmiisys1 CLK_SGMII1_CDR_FB>,
|
||||
<&topckgen CLK_TOP_NETSYS_SEL>,
|
||||
<&topckgen CLK_TOP_NETSYS_500M_SEL>;
|
||||
clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
|
||||
"sgmii_tx250m", "sgmii_rx250m",
|
||||
"sgmii_cdr_ref", "sgmii_cdr_fb",
|
||||
"sgmii2_tx250m", "sgmii2_rx250m",
|
||||
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
|
||||
"netsys0", "netsys1";
|
||||
assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
|
||||
<&topckgen CLK_TOP_SGM_325M_SEL>;
|
||||
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
|
||||
<&apmixedsys CLK_APMIXED_SGMPLL>;
|
||||
mediatek,ethsys = <ðsys>;
|
||||
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
|
||||
#reset-cells = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
@ -28,3 +28,73 @@
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ð {
|
||||
status = "okay";
|
||||
|
||||
gmac0: mac@0 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <0>;
|
||||
phy-mode = "2500base-x";
|
||||
|
||||
fixed-link {
|
||||
speed = <2500>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
|
||||
mdio: mdio-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
switch@0 {
|
||||
compatible = "mediatek,mt7531";
|
||||
reg = <31>;
|
||||
reset-gpios = <&pio 5 0>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan0";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@4 {
|
||||
reg = <4>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
label = "cpu";
|
||||
ethernet = <&gmac0>;
|
||||
phy-mode = "2500base-x";
|
||||
|
||||
fixed-link {
|
||||
speed = <2500>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -24,6 +24,7 @@
|
||||
#define MTK_MAX_RX_LENGTH 1536
|
||||
#define MTK_MAX_RX_LENGTH_2K 2048
|
||||
#define MTK_TX_DMA_BUF_LEN 0x3fff
|
||||
#define MTK_TX_DMA_BUF_LEN_V2 0xffff
|
||||
#define MTK_DMA_SIZE 512
|
||||
#define MTK_MAC_COUNT 2
|
||||
#define MTK_RX_ETH_HLEN (ETH_HLEN + ETH_FCS_LEN)
|
||||
@ -48,6 +49,8 @@
|
||||
#define MTK_HW_FEATURES_MT7628 (NETIF_F_SG | NETIF_F_RXCSUM)
|
||||
#define NEXT_DESP_IDX(X, Y) (((X) + 1) & ((Y) - 1))
|
||||
|
||||
#define MTK_QRX_OFFSET 0x10
|
||||
|
||||
#define MTK_MAX_RX_RING_NUM 4
|
||||
#define MTK_HW_LRO_DMA_SIZE 8
|
||||
|
||||
@ -81,6 +84,10 @@
|
||||
#define MTK_CDMQ_IG_CTRL 0x1400
|
||||
#define MTK_CDMQ_STAG_EN BIT(0)
|
||||
|
||||
/* CDMP Ingress Control Register */
|
||||
#define MTK_CDMP_IG_CTRL 0x400
|
||||
#define MTK_CDMP_STAG_EN BIT(0)
|
||||
|
||||
/* CDMP Exgress Control Register */
|
||||
#define MTK_CDMP_EG_CTRL 0x404
|
||||
|
||||
@ -100,25 +107,38 @@
|
||||
/* Unicast Filter MAC Address Register - High */
|
||||
#define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
|
||||
|
||||
/* PDMA RX Base Pointer Register */
|
||||
#define MTK_PRX_BASE_PTR0 0x900
|
||||
#define MTK_PRX_BASE_PTR_CFG(x) (MTK_PRX_BASE_PTR0 + (x * 0x10))
|
||||
/* FE global misc reg*/
|
||||
#define MTK_FE_GLO_MISC 0x124
|
||||
|
||||
/* PDMA RX Maximum Count Register */
|
||||
#define MTK_PRX_MAX_CNT0 0x904
|
||||
#define MTK_PRX_MAX_CNT_CFG(x) (MTK_PRX_MAX_CNT0 + (x * 0x10))
|
||||
/* PSE Free Queue Flow Control */
|
||||
#define PSE_FQFC_CFG1 0x100
|
||||
#define PSE_FQFC_CFG2 0x104
|
||||
#define PSE_DROP_CFG 0x108
|
||||
|
||||
/* PDMA RX CPU Pointer Register */
|
||||
#define MTK_PRX_CRX_IDX0 0x908
|
||||
#define MTK_PRX_CRX_IDX_CFG(x) (MTK_PRX_CRX_IDX0 + (x * 0x10))
|
||||
/* PSE Input Queue Reservation Register*/
|
||||
#define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2))
|
||||
|
||||
/* PSE Output Queue Threshold Register*/
|
||||
#define PSE_OQ_TH(x) (0x160 + (((x) - 1) << 2))
|
||||
|
||||
/* GDM and CDM Threshold */
|
||||
#define MTK_GDM2_THRES 0x1530
|
||||
#define MTK_CDMW0_THRES 0x164c
|
||||
#define MTK_CDMW1_THRES 0x1650
|
||||
#define MTK_CDME0_THRES 0x1654
|
||||
#define MTK_CDME1_THRES 0x1658
|
||||
#define MTK_CDMM_THRES 0x165c
|
||||
|
||||
/* PDMA HW LRO Control Registers */
|
||||
#define MTK_PDMA_LRO_CTRL_DW0 0x980
|
||||
#define MTK_LRO_EN BIT(0)
|
||||
#define MTK_L3_CKS_UPD_EN BIT(7)
|
||||
#define MTK_L3_CKS_UPD_EN_V2 BIT(19)
|
||||
#define MTK_LRO_ALT_PKT_CNT_MODE BIT(21)
|
||||
#define MTK_LRO_RING_RELINQUISH_REQ (0x7 << 26)
|
||||
#define MTK_LRO_RING_RELINQUISH_REQ_V2 (0xf << 24)
|
||||
#define MTK_LRO_RING_RELINQUISH_DONE (0x7 << 29)
|
||||
#define MTK_LRO_RING_RELINQUISH_DONE_V2 (0xf << 28)
|
||||
|
||||
#define MTK_PDMA_LRO_CTRL_DW1 0x984
|
||||
#define MTK_PDMA_LRO_CTRL_DW2 0x988
|
||||
@ -126,18 +146,19 @@
|
||||
#define MTK_ADMA_MODE BIT(15)
|
||||
#define MTK_LRO_MIN_RXD_SDL (MTK_HW_LRO_SDL_REMAIN_ROOM << 16)
|
||||
|
||||
/* PDMA Global Configuration Register */
|
||||
#define MTK_PDMA_GLO_CFG 0xa04
|
||||
#define MTK_RX_DMA_LRO_EN BIT(8)
|
||||
#define MTK_MULTI_EN BIT(10)
|
||||
#define MTK_PDMA_SIZE_8DWORDS (1 << 4)
|
||||
|
||||
/* PDMA Global Configuration Register */
|
||||
#define MTK_PDMA_LRO_SDL 0x3000
|
||||
#define MTK_RX_CFG_SDL_OFFSET 16
|
||||
|
||||
/* PDMA Reset Index Register */
|
||||
#define MTK_PDMA_RST_IDX 0xa08
|
||||
#define MTK_PST_DRX_IDX0 BIT(16)
|
||||
#define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x))
|
||||
|
||||
/* PDMA Delay Interrupt Register */
|
||||
#define MTK_PDMA_DELAY_INT 0xa0c
|
||||
#define MTK_PDMA_DELAY_RX_MASK GENMASK(15, 0)
|
||||
#define MTK_PDMA_DELAY_RX_EN BIT(15)
|
||||
#define MTK_PDMA_DELAY_RX_PINT_SHIFT 8
|
||||
@ -151,19 +172,9 @@
|
||||
#define MTK_PDMA_DELAY_PINT_MASK 0x7f
|
||||
#define MTK_PDMA_DELAY_PTIME_MASK 0xff
|
||||
|
||||
/* PDMA Interrupt Status Register */
|
||||
#define MTK_PDMA_INT_STATUS 0xa20
|
||||
|
||||
/* PDMA Interrupt Mask Register */
|
||||
#define MTK_PDMA_INT_MASK 0xa28
|
||||
|
||||
/* PDMA HW LRO Alter Flow Delta Register */
|
||||
#define MTK_PDMA_LRO_ALT_SCORE_DELTA 0xa4c
|
||||
|
||||
/* PDMA Interrupt grouping registers */
|
||||
#define MTK_PDMA_INT_GRP1 0xa50
|
||||
#define MTK_PDMA_INT_GRP2 0xa54
|
||||
|
||||
/* PDMA HW LRO IP Setting Registers */
|
||||
#define MTK_LRO_RX_RING0_DIP_DW0 0xb04
|
||||
#define MTK_LRO_DIP_DW0_CFG(x) (MTK_LRO_RX_RING0_DIP_DW0 + (x * 0x40))
|
||||
@ -185,26 +196,9 @@
|
||||
#define MTK_RING_MAX_AGG_CNT_H ((MTK_HW_LRO_MAX_AGG_CNT >> 6) & 0x3)
|
||||
|
||||
/* QDMA TX Queue Configuration Registers */
|
||||
#define MTK_QTX_CFG(x) (0x1800 + (x * 0x10))
|
||||
#define QDMA_RES_THRES 4
|
||||
|
||||
/* QDMA TX Queue Scheduler Registers */
|
||||
#define MTK_QTX_SCH(x) (0x1804 + (x * 0x10))
|
||||
|
||||
/* QDMA RX Base Pointer Register */
|
||||
#define MTK_QRX_BASE_PTR0 0x1900
|
||||
|
||||
/* QDMA RX Maximum Count Register */
|
||||
#define MTK_QRX_MAX_CNT0 0x1904
|
||||
|
||||
/* QDMA RX CPU Pointer Register */
|
||||
#define MTK_QRX_CRX_IDX0 0x1908
|
||||
|
||||
/* QDMA RX DMA Pointer Register */
|
||||
#define MTK_QRX_DRX_IDX0 0x190C
|
||||
|
||||
/* QDMA Global Configuration Register */
|
||||
#define MTK_QDMA_GLO_CFG 0x1A04
|
||||
#define MTK_RX_2B_OFFSET BIT(31)
|
||||
#define MTK_RX_BT_32DWORDS (3 << 11)
|
||||
#define MTK_NDP_CO_PRO BIT(10)
|
||||
@ -216,20 +210,19 @@
|
||||
#define MTK_TX_DMA_EN BIT(0)
|
||||
#define MTK_DMA_BUSY_TIMEOUT_US 1000000
|
||||
|
||||
/* QDMA Reset Index Register */
|
||||
#define MTK_QDMA_RST_IDX 0x1A08
|
||||
|
||||
/* QDMA Delay Interrupt Register */
|
||||
#define MTK_QDMA_DELAY_INT 0x1A0C
|
||||
/* QDMA V2 Global Configuration Register */
|
||||
#define MTK_CHK_DDONE_EN BIT(28)
|
||||
#define MTK_DMAD_WR_WDONE BIT(26)
|
||||
#define MTK_WCOMP_EN BIT(24)
|
||||
#define MTK_RESV_BUF (0x40 << 16)
|
||||
#define MTK_MUTLI_CNT (0x4 << 12)
|
||||
|
||||
/* QDMA Flow Control Register */
|
||||
#define MTK_QDMA_FC_THRES 0x1A10
|
||||
#define FC_THRES_DROP_MODE BIT(20)
|
||||
#define FC_THRES_DROP_EN (7 << 16)
|
||||
#define FC_THRES_MIN 0x4444
|
||||
|
||||
/* QDMA Interrupt Status Register */
|
||||
#define MTK_QDMA_INT_STATUS 0x1A18
|
||||
#define MTK_RX_DONE_DLY BIT(30)
|
||||
#define MTK_TX_DONE_DLY BIT(28)
|
||||
#define MTK_RX_DONE_INT3 BIT(19)
|
||||
@ -243,58 +236,32 @@
|
||||
#define MTK_RX_DONE_INT MTK_RX_DONE_DLY
|
||||
#define MTK_TX_DONE_INT MTK_TX_DONE_DLY
|
||||
|
||||
#define MTK_RX_DONE_INT_V2 BIT(14)
|
||||
|
||||
/* QDMA Interrupt grouping registers */
|
||||
#define MTK_QDMA_INT_GRP1 0x1a20
|
||||
#define MTK_QDMA_INT_GRP2 0x1a24
|
||||
#define MTK_RLS_DONE_INT BIT(0)
|
||||
|
||||
/* QDMA Interrupt Status Register */
|
||||
#define MTK_QDMA_INT_MASK 0x1A1C
|
||||
|
||||
/* QDMA Interrupt Mask Register */
|
||||
#define MTK_QDMA_HRED2 0x1A44
|
||||
|
||||
/* QDMA TX Forward CPU Pointer Register */
|
||||
#define MTK_QTX_CTX_PTR 0x1B00
|
||||
|
||||
/* QDMA TX Forward DMA Pointer Register */
|
||||
#define MTK_QTX_DTX_PTR 0x1B04
|
||||
|
||||
/* QDMA TX Release CPU Pointer Register */
|
||||
#define MTK_QTX_CRX_PTR 0x1B10
|
||||
|
||||
/* QDMA TX Release DMA Pointer Register */
|
||||
#define MTK_QTX_DRX_PTR 0x1B14
|
||||
|
||||
/* QDMA FQ Head Pointer Register */
|
||||
#define MTK_QDMA_FQ_HEAD 0x1B20
|
||||
|
||||
/* QDMA FQ Head Pointer Register */
|
||||
#define MTK_QDMA_FQ_TAIL 0x1B24
|
||||
|
||||
/* QDMA FQ Free Page Counter Register */
|
||||
#define MTK_QDMA_FQ_CNT 0x1B28
|
||||
|
||||
/* QDMA FQ Free Page Buffer Length Register */
|
||||
#define MTK_QDMA_FQ_BLEN 0x1B2C
|
||||
|
||||
/* GMA1 counter / statics register */
|
||||
#define MTK_GDM1_RX_GBCNT_L 0x2400
|
||||
#define MTK_GDM1_RX_GBCNT_H 0x2404
|
||||
#define MTK_GDM1_RX_GPCNT 0x2408
|
||||
#define MTK_GDM1_RX_OERCNT 0x2410
|
||||
#define MTK_GDM1_RX_FERCNT 0x2414
|
||||
#define MTK_GDM1_RX_SERCNT 0x2418
|
||||
#define MTK_GDM1_RX_LENCNT 0x241c
|
||||
#define MTK_GDM1_RX_CERCNT 0x2420
|
||||
#define MTK_GDM1_RX_FCCNT 0x2424
|
||||
#define MTK_GDM1_TX_SKIPCNT 0x2428
|
||||
#define MTK_GDM1_TX_COLCNT 0x242c
|
||||
#define MTK_GDM1_TX_GBCNT_L 0x2430
|
||||
#define MTK_GDM1_TX_GBCNT_H 0x2434
|
||||
#define MTK_GDM1_TX_GPCNT 0x2438
|
||||
#define MTK_STAT_OFFSET 0x40
|
||||
|
||||
/* QDMA TX NUM */
|
||||
#define MTK_QDMA_TX_NUM 16
|
||||
#define MTK_QDMA_TX_MASK (MTK_QDMA_TX_NUM - 1)
|
||||
#define QID_BITS_V2(x) (((x) & 0x3f) << 16)
|
||||
#define MTK_QDMA_GMAC2_QID 8
|
||||
|
||||
#define MTK_TX_DMA_BUF_SHIFT 8
|
||||
|
||||
/* QDMA V2 descriptor txd6 */
|
||||
#define TX_DMA_INS_VLAN_V2 BIT(16)
|
||||
/* QDMA V2 descriptor txd5 */
|
||||
#define TX_DMA_CHKSUM_V2 (0x7 << 28)
|
||||
#define TX_DMA_TSO_V2 BIT(31)
|
||||
|
||||
/* QDMA V2 descriptor txd4 */
|
||||
#define TX_DMA_FPORT_SHIFT_V2 8
|
||||
#define TX_DMA_FPORT_MASK_V2 0xf
|
||||
#define TX_DMA_SWC_V2 BIT(30)
|
||||
|
||||
#define MTK_WDMA0_BASE 0x2800
|
||||
#define MTK_WDMA1_BASE 0x2c00
|
||||
|
||||
@ -308,10 +275,9 @@
|
||||
/* QDMA descriptor txd3 */
|
||||
#define TX_DMA_OWNER_CPU BIT(31)
|
||||
#define TX_DMA_LS0 BIT(30)
|
||||
#define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16)
|
||||
#define TX_DMA_PLEN1(_x) ((_x) & MTK_TX_DMA_BUF_LEN)
|
||||
#define TX_DMA_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
|
||||
#define TX_DMA_PLEN1(x) ((x) & eth->soc->txrx.dma_max_len)
|
||||
#define TX_DMA_SWC BIT(14)
|
||||
#define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16)
|
||||
|
||||
/* PDMA on MT7628 */
|
||||
#define TX_DMA_DONE BIT(31)
|
||||
@ -321,12 +287,14 @@
|
||||
/* QDMA descriptor rxd2 */
|
||||
#define RX_DMA_DONE BIT(31)
|
||||
#define RX_DMA_LSO BIT(30)
|
||||
#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
|
||||
#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
|
||||
#define RX_DMA_PREP_PLEN0(x) (((x) & eth->soc->txrx.dma_max_len) << eth->soc->txrx.dma_len_offset)
|
||||
#define RX_DMA_GET_PLEN0(x) (((x) >> eth->soc->txrx.dma_len_offset) & eth->soc->txrx.dma_max_len)
|
||||
#define RX_DMA_VTAG BIT(15)
|
||||
|
||||
/* QDMA descriptor rxd3 */
|
||||
#define RX_DMA_VID(_x) ((_x) & 0xfff)
|
||||
#define RX_DMA_VID(x) ((x) & VLAN_VID_MASK)
|
||||
#define RX_DMA_TCI(x) ((x) & (VLAN_PRIO_MASK | VLAN_VID_MASK))
|
||||
#define RX_DMA_VPID(x) (((x) >> 16) & 0xffff)
|
||||
|
||||
/* QDMA descriptor rxd4 */
|
||||
#define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
|
||||
@ -337,10 +305,15 @@
|
||||
/* QDMA descriptor rxd4 */
|
||||
#define RX_DMA_L4_VALID BIT(24)
|
||||
#define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
|
||||
#define RX_DMA_FPORT_SHIFT 19
|
||||
#define RX_DMA_FPORT_MASK 0x7
|
||||
#define RX_DMA_SPECIAL_TAG BIT(22)
|
||||
|
||||
#define RX_DMA_GET_SPORT(x) (((x) >> 19) & 0xf)
|
||||
#define RX_DMA_GET_SPORT_V2(x) (((x) >> 26) & 0x7)
|
||||
|
||||
/* PDMA V2 descriptor rxd3 */
|
||||
#define RX_DMA_VTAG_V2 BIT(0)
|
||||
#define RX_DMA_L4_VALID_V2 BIT(2)
|
||||
|
||||
/* PHY Indirect Access Control registers */
|
||||
#define MTK_PHY_IAC 0x10004
|
||||
#define PHY_IAC_ACCESS BIT(31)
|
||||
@ -463,6 +436,16 @@
|
||||
#define ETHSYS_TRGMII_MT7621_APLL BIT(6)
|
||||
#define ETHSYS_TRGMII_MT7621_DDR_PLL BIT(5)
|
||||
|
||||
/* ethernet reset control register */
|
||||
#define ETHSYS_RSTCTRL 0x34
|
||||
#define RSTCTRL_FE BIT(6)
|
||||
#define RSTCTRL_PPE BIT(31)
|
||||
#define RSTCTRL_PPE1 BIT(30)
|
||||
#define RSTCTRL_ETH BIT(23)
|
||||
|
||||
/* ethernet reset check idle register */
|
||||
#define ETHSYS_FE_RST_CHK_IDLE_EN 0x28
|
||||
|
||||
/* ethernet reset control register */
|
||||
#define ETHSYS_RSTCTRL 0x34
|
||||
#define RSTCTRL_FE BIT(6)
|
||||
@ -548,6 +531,17 @@ struct mtk_rx_dma {
|
||||
unsigned int rxd4;
|
||||
} __packed __aligned(4);
|
||||
|
||||
struct mtk_rx_dma_v2 {
|
||||
unsigned int rxd1;
|
||||
unsigned int rxd2;
|
||||
unsigned int rxd3;
|
||||
unsigned int rxd4;
|
||||
unsigned int rxd5;
|
||||
unsigned int rxd6;
|
||||
unsigned int rxd7;
|
||||
unsigned int rxd8;
|
||||
} __packed __aligned(4);
|
||||
|
||||
struct mtk_tx_dma {
|
||||
unsigned int txd1;
|
||||
unsigned int txd2;
|
||||
@ -555,6 +549,17 @@ struct mtk_tx_dma {
|
||||
unsigned int txd4;
|
||||
} __packed __aligned(4);
|
||||
|
||||
struct mtk_tx_dma_v2 {
|
||||
unsigned int txd1;
|
||||
unsigned int txd2;
|
||||
unsigned int txd3;
|
||||
unsigned int txd4;
|
||||
unsigned int txd5;
|
||||
unsigned int txd6;
|
||||
unsigned int txd7;
|
||||
unsigned int txd8;
|
||||
} __packed __aligned(4);
|
||||
|
||||
struct mtk_eth;
|
||||
struct mtk_mac;
|
||||
|
||||
@ -622,6 +627,10 @@ enum mtk_clks_map {
|
||||
MTK_CLK_SGMII2_CDR_FB,
|
||||
MTK_CLK_SGMII_CK,
|
||||
MTK_CLK_ETH2PLL,
|
||||
MTK_CLK_WOCPU0,
|
||||
MTK_CLK_WOCPU1,
|
||||
MTK_CLK_NETSYS0,
|
||||
MTK_CLK_NETSYS1,
|
||||
MTK_CLK_MAX
|
||||
};
|
||||
|
||||
@ -652,6 +661,16 @@ enum mtk_clks_map {
|
||||
BIT(MTK_CLK_SGMII2_CDR_FB) | \
|
||||
BIT(MTK_CLK_SGMII_CK) | \
|
||||
BIT(MTK_CLK_ETH2PLL) | BIT(MTK_CLK_SGMIITOP))
|
||||
#define MT7986_CLKS_BITMAP (BIT(MTK_CLK_FE) | BIT(MTK_CLK_GP2) | BIT(MTK_CLK_GP1) | \
|
||||
BIT(MTK_CLK_WOCPU1) | BIT(MTK_CLK_WOCPU0) | \
|
||||
BIT(MTK_CLK_SGMII_TX_250M) | \
|
||||
BIT(MTK_CLK_SGMII_RX_250M) | \
|
||||
BIT(MTK_CLK_SGMII_CDR_REF) | \
|
||||
BIT(MTK_CLK_SGMII_CDR_FB) | \
|
||||
BIT(MTK_CLK_SGMII2_TX_250M) | \
|
||||
BIT(MTK_CLK_SGMII2_RX_250M) | \
|
||||
BIT(MTK_CLK_SGMII2_CDR_REF) | \
|
||||
BIT(MTK_CLK_SGMII2_CDR_FB))
|
||||
|
||||
enum mtk_dev_state {
|
||||
MTK_HW_INIT,
|
||||
@ -687,7 +706,7 @@ struct mtk_tx_buf {
|
||||
* are present
|
||||
*/
|
||||
struct mtk_tx_ring {
|
||||
struct mtk_tx_dma *dma;
|
||||
void *dma;
|
||||
struct mtk_tx_buf *buf;
|
||||
dma_addr_t phys;
|
||||
struct mtk_tx_dma *next_free;
|
||||
@ -717,7 +736,7 @@ enum mtk_rx_flags {
|
||||
* @calc_idx: The current head of ring
|
||||
*/
|
||||
struct mtk_rx_ring {
|
||||
struct mtk_rx_dma *dma;
|
||||
void *dma;
|
||||
u8 **data;
|
||||
dma_addr_t phys;
|
||||
u16 frag_size;
|
||||
@ -741,7 +760,9 @@ enum mkt_eth_capabilities {
|
||||
MTK_SHARED_INT_BIT,
|
||||
MTK_TRGMII_MT7621_CLK_BIT,
|
||||
MTK_QDMA_BIT,
|
||||
MTK_NETSYS_V2_BIT,
|
||||
MTK_SOC_MT7628_BIT,
|
||||
MTK_RSTCTRL_PPE1_BIT,
|
||||
|
||||
/* MUX BITS*/
|
||||
MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
|
||||
@ -773,7 +794,9 @@ enum mkt_eth_capabilities {
|
||||
#define MTK_SHARED_INT BIT(MTK_SHARED_INT_BIT)
|
||||
#define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT)
|
||||
#define MTK_QDMA BIT(MTK_QDMA_BIT)
|
||||
#define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT)
|
||||
#define MTK_SOC_MT7628 BIT(MTK_SOC_MT7628_BIT)
|
||||
#define MTK_RSTCTRL_PPE1 BIT(MTK_RSTCTRL_PPE1_BIT)
|
||||
|
||||
#define MTK_ETH_MUX_GDM1_TO_GMAC1_ESW \
|
||||
BIT(MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT)
|
||||
@ -846,8 +869,62 @@ enum mkt_eth_capabilities {
|
||||
MTK_MUX_U3_GMAC2_TO_QPHY | \
|
||||
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA)
|
||||
|
||||
#define MT7986_CAPS (MTK_GMAC1_SGMII | MTK_GMAC2_SGMII | \
|
||||
MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
|
||||
MTK_NETSYS_V2 | MTK_RSTCTRL_PPE1)
|
||||
|
||||
struct mtk_tx_dma_desc_info {
|
||||
dma_addr_t addr;
|
||||
u32 size;
|
||||
u16 vlan_tci;
|
||||
u16 qid;
|
||||
u8 gso:1;
|
||||
u8 csum:1;
|
||||
u8 vlan:1;
|
||||
u8 first:1;
|
||||
u8 last:1;
|
||||
};
|
||||
|
||||
struct mtk_reg_map {
|
||||
u32 tx_irq_mask;
|
||||
u32 tx_irq_status;
|
||||
struct {
|
||||
u32 rx_ptr; /* rx base pointer */
|
||||
u32 rx_cnt_cfg; /* rx max count configuration */
|
||||
u32 pcrx_ptr; /* rx cpu pointer */
|
||||
u32 glo_cfg; /* global configuration */
|
||||
u32 rst_idx; /* reset index */
|
||||
u32 delay_irq; /* delay interrupt */
|
||||
u32 irq_status; /* interrupt status */
|
||||
u32 irq_mask; /* interrupt mask */
|
||||
u32 int_grp;
|
||||
} pdma;
|
||||
struct {
|
||||
u32 qtx_cfg; /* tx queue configuration */
|
||||
u32 rx_ptr; /* rx base pointer */
|
||||
u32 rx_cnt_cfg; /* rx max count configuration */
|
||||
u32 qcrx_ptr; /* rx cpu pointer */
|
||||
u32 glo_cfg; /* global configuration */
|
||||
u32 rst_idx; /* reset index */
|
||||
u32 delay_irq; /* delay interrupt */
|
||||
u32 fc_th; /* flow control */
|
||||
u32 int_grp;
|
||||
u32 hred; /* interrupt mask */
|
||||
u32 ctx_ptr; /* tx acquire cpu pointer */
|
||||
u32 dtx_ptr; /* tx acquire dma pointer */
|
||||
u32 crx_ptr; /* tx release cpu pointer */
|
||||
u32 drx_ptr; /* tx release dma pointer */
|
||||
u32 fq_head; /* fq head pointer */
|
||||
u32 fq_tail; /* fq tail pointer */
|
||||
u32 fq_count; /* fq free page count */
|
||||
u32 fq_blen; /* fq free page buffer length */
|
||||
} qdma;
|
||||
u32 gdm1_cnt;
|
||||
};
|
||||
|
||||
/* struct mtk_eth_data - This is the structure holding all differences
|
||||
* among various plaforms
|
||||
* @reg_map Soc register map.
|
||||
* @ana_rgc3: The offset for register ANA_RGC3 related to
|
||||
* sgmiisys syscon
|
||||
* @caps Flags shown the extra capability for the SoC
|
||||
@ -856,14 +933,29 @@ enum mkt_eth_capabilities {
|
||||
* the target SoC
|
||||
* @required_pctl A bool value to show whether the SoC requires
|
||||
* the extra setup for those pins used by GMAC.
|
||||
* @txd_size Tx DMA descriptor size.
|
||||
* @rxd_size Rx DMA descriptor size.
|
||||
* @rx_irq_done_mask Rx irq done register mask.
|
||||
* @rx_dma_l4_valid Rx DMA valid register mask.
|
||||
* @dma_max_len Max DMA tx/rx buffer length.
|
||||
* @dma_len_offset Tx/Rx DMA length field offset.
|
||||
*/
|
||||
struct mtk_soc_data {
|
||||
const struct mtk_reg_map *reg_map;
|
||||
u32 ana_rgc3;
|
||||
u32 caps;
|
||||
u32 required_clks;
|
||||
bool required_pctl;
|
||||
u8 offload_version;
|
||||
netdev_features_t hw_features;
|
||||
struct {
|
||||
u32 txd_size;
|
||||
u32 rxd_size;
|
||||
u32 rx_irq_done_mask;
|
||||
u32 rx_dma_l4_valid;
|
||||
u32 dma_max_len;
|
||||
u32 dma_len_offset;
|
||||
} txrx;
|
||||
};
|
||||
|
||||
/* currently no SoC has more than 2 macs */
|
||||
@ -959,7 +1051,7 @@ struct mtk_eth {
|
||||
struct mtk_rx_ring rx_ring_qdma;
|
||||
struct napi_struct tx_napi;
|
||||
struct napi_struct rx_napi;
|
||||
struct mtk_tx_dma *scratch_ring;
|
||||
void *scratch_ring;
|
||||
dma_addr_t phy_scratch_ring;
|
||||
void *scratch_head;
|
||||
struct clk *clks[MTK_CLK_MAX];
|
||||
@ -982,9 +1074,6 @@ struct mtk_eth {
|
||||
u32 tx_bytes;
|
||||
struct dim tx_dim;
|
||||
|
||||
u32 tx_int_mask_reg;
|
||||
u32 tx_int_status_reg;
|
||||
u32 rx_dma_l4_valid;
|
||||
int ip_align;
|
||||
|
||||
struct mtk_ppe *ppe;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user