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drm/i915: Fix HSW power well control state read

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Fix power well control state by reading real register offset.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Zhenyu Wang 2012-10-30 19:16:34 +08:00 committed by Daniel Vetter
parent 14f86147a9
commit 263b30d4b1
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/intel_pm.c
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@ -3842,7 +3842,7 @@ void intel_init_power_wells(struct drm_device *dev)
if ((well & HSW_PWR_WELL_STATE) == 0) {
I915_WRITE(power_wells[i], well & HSW_PWR_WELL_ENABLE);
if (wait_for(I915_READ(power_wells[i] & HSW_PWR_WELL_STATE), 20))
if (wait_for((I915_READ(power_wells[i]) & HSW_PWR_WELL_STATE), 20))
DRM_ERROR("Error enabling power well %lx\n", power_wells[i]);
}
}