Allwinner DT changes for 4.20
Our usual bunch of DT patches for the Allwinner arm32 SoCs. The most notable changes are: - Support for the video decoding / encoding engine on the A10s/A13/A20/A33 - IR support for the A83t - SATA support for the R40 -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEE0VqZU19dR2zEVaqr0rTAlCFNr3QFAluvkSIACgkQ0rTAlCFN r3Snkw/9FtNLppZKqT2l5NdU7eRE2nUGNvBBh1Dgw2lIlWyzpffjsdMBzZRGahTT wK/uZwvrLmdtb2WKWCnEJ4k2Vrp3nPGGNlOdonsf9I5CqR/Cl88Z6HPIdEI1FwMC bNgrC8LENP+zsDPjMZkgOJ/JBlOmPco9l42mC8c2kfLtSiKdiQWNZ88oPgCoiRbJ VCWnxnxU7pQkX10yj/aIu1bhcFgxLYa1M2C0rj4AkxIdWChVaDZxiDCncuSIqcHt 7a4NchkBXOZeqYY2Dz3ppdxFnQWOhvR0qQJjHzVcGdKNDKurNv0Ud6Mq2v4+Doo9 gJUKGy0PcbvMwm3spOK/CdcW+c3IfO2bJaOz36mE3S3d6a78Ku7UeIc2GnlL9zfx EYsowLaERm3213ZsbXWB07vfOxoJtk7cmCRIdnuk2S9sFaTZzB65/x+0lNCdxAbL 6Pc4/ZBYVp596T2fGjjnPho6bx9SQ2+ybz9/epEHVRTBYja2zIfJ/Pw4D8ofxDBR bDZznX3EmE4L1m1w6FaDQzDsoQNv6pS/fiTfsXD35OnzNY0KplbFfcOCZQpF31Mi 7s6iADszYEcefXOwmuIekG5Zw2qcCt4sNkWu/U0hjPXf3TVMnaImPce5K6PBXJHt zu9DabmboEHicazYPlvJflWD9gkbM5lHdNGAmqWVm/eQ7IDH0Z8= =vyaf -----END PGP SIGNATURE----- Merge tag 'sunxi-dt-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into next/dt Allwinner DT changes for 4.20 Our usual bunch of DT patches for the Allwinner arm32 SoCs. The most notable changes are: - Support for the video decoding / encoding engine on the A10s/A13/A20/A33 - IR support for the A83t - SATA support for the R40 * tag 'sunxi-dt-for-4.20' of git://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: ARM: dts: sun9i: Fix I2C bus warnings ARM: dts: sunxi: Fix I2C bus warnings ARM: dts: sun8i-a33: Add Video Engine and reserved memory nodes ARM: dts: sun7i-a20: Add Video Engine and reserved memory nodes ARM: dts: sun5i: Add Video Engine and reserved memory nodes ARM: dts: sun8i: sun8i-r40-bananapi-m2-ultra: enable AHCI ARM: dts: sun8i: r40: add sata node ARM: dts: sunxi: Don't use cd-inverted in sun8i-r40-bananapi-m2-ultra ARM: dts: sun8i: a83t: bananapi-m3: Enable IR controller ARM: dts: sun8i: a83t: Add support for the cir interface ARM: dts: sun8i: a83t: Add the cir pin for the A83T Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
26220da2ab
@ -92,7 +92,8 @@
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*/
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clock-frequency = <400000>;
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touchscreen: touchscreen {
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touchscreen: touchscreen@40 {
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reg = <0x40>;
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interrupt-parent = <&pio>;
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interrupts = <6 11 IRQ_TYPE_EDGE_FALLING>; /* EINT11 (PG11) */
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pinctrl-names = "default";
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@ -108,6 +108,21 @@
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};
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
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cma_pool: cma@4a000000 {
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compatible = "shared-dma-pool";
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size = <0x6000000>;
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alloc-ranges = <0x4a000000 0x6000000>;
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reusable;
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linux,cma-default;
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};
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};
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soc@1c00000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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@ -294,6 +309,17 @@
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};
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};
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video-codec@1c0e000 {
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compatible = "allwinner,sun5i-a13-video-engine";
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reg = <0x01c0e000 0x1000>;
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clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
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<&ccu CLK_DRAM_VE>;
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clock-names = "ahb", "mod", "ram";
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resets = <&ccu RST_VE>;
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interrupts = <53>;
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allwinner,sram = <&ve_sram 1>;
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};
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun5i-a13-mmc";
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reg = <0x01c0f000 0x1000>;
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@ -174,6 +174,21 @@
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reg = <0x40000000 0x80000000>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
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cma_pool: cma@4a000000 {
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compatible = "shared-dma-pool";
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size = <0x6000000>;
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alloc-ranges = <0x4a000000 0x6000000>;
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reusable;
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linux,cma-default;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
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@ -479,6 +494,17 @@
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};
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};
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video-codec@1c0e000 {
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compatible = "allwinner,sun7i-a20-video-engine";
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reg = <0x01c0e000 0x1000>;
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clocks = <&ccu CLK_AHB_VE>, <&ccu CLK_VE>,
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<&ccu CLK_DRAM_VE>;
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clock-names = "ahb", "mod", "ram";
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resets = <&ccu RST_VE>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
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allwinner,sram = <&ve_sram 1>;
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};
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mmc0: mmc@1c0f000 {
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compatible = "allwinner,sun7i-a20-mmc";
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reg = <0x01c0f000 0x1000>;
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@ -190,6 +190,21 @@
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reg = <0x40000000 0x80000000>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* Address must be kept in the lower 256 MiBs of DRAM for VE. */
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cma_pool: cma@4a000000 {
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compatible = "shared-dma-pool";
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size = <0x6000000>;
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alloc-ranges = <0x4a000000 0x6000000>;
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reusable;
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linux,cma-default;
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};
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};
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sound: sound {
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compatible = "simple-audio-card";
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simple-audio-card,name = "sun8i-a33-audio";
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@ -254,6 +269,17 @@
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};
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};
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video-codec@01c0e000 {
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compatible = "allwinner,sun8i-a33-video-engine";
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reg = <0x01c0e000 0x1000>;
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clocks = <&ccu CLK_BUS_VE>, <&ccu CLK_VE>,
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<&ccu CLK_DRAM_VE>;
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clock-names = "ahb", "mod", "ram";
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resets = <&ccu RST_BUS_VE>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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allwinner,sram = <&ve_sram 1>;
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};
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crypto: crypto-engine@1c15000 {
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compatible = "allwinner,sun4i-a10-crypto";
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reg = <0x01c15000 0x1000>;
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@ -191,6 +191,11 @@
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status = "okay";
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};
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&r_cir {
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clock-frequency = <3000000>;
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status = "okay";
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};
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&r_rsb {
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status = "okay";
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@ -990,6 +990,19 @@
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reg = <0x1f01c00 0x400>;
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};
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r_cir: ir@1f02000 {
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compatible = "allwinner,sun8i-a83t-ir",
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"allwinner,sun5i-a13-ir";
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clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
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clock-names = "apb", "ir";
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resets = <&r_ccu RST_APB0_IR>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0x01f02000 0x400>;
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pinctrl-names = "default";
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pinctrl-0 = <&r_cir_pin>;
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status = "disabled";
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};
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r_pio: pinctrl@1f02c00 {
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compatible = "allwinner,sun8i-a83t-r-pinctrl";
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reg = <0x01f02c00 0x400>;
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@ -1002,6 +1015,11 @@
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interrupt-controller;
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#interrupt-cells = <3>;
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r_cir_pin: r-cir-pin {
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pins = "PL12";
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function = "s_cir_rx";
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};
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r_rsb_pins: r-rsb-pins {
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pins = "PL0", "PL1";
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function = "s_rsb";
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@ -105,6 +105,12 @@
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};
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};
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&ahci {
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ahci-supply = <®_dldo4>;
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phy-supply = <®_eldo3>;
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status = "okay";
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};
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&de {
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status = "okay";
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};
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@ -159,8 +165,7 @@
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&mmc0 {
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vmmc-supply = <®_dcdc1>;
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bus-width = <4>;
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cd-gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */
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cd-inverted;
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cd-gpios = <&pio 7 13 GPIO_ACTIVE_LOW>; /* PH13 */
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status = "okay";
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};
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@ -251,6 +256,18 @@
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regulator-name = "vcc-wifi";
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};
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®_dldo4 {
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regulator-min-microvolt = <2500000>;
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regulator-max-microvolt = <2500000>;
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regulator-name = "vdd2v5-sata";
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};
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®_eldo3 {
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regulator-min-microvolt = <1200000>;
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regulator-max-microvolt = <1200000>;
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regulator-name = "vdd1v2-sata";
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};
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&tcon_tv0 {
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status = "okay";
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};
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#size-cells = <0>;
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};
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ahci: sata@1c18000 {
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compatible = "allwinner,sun8i-r40-ahci";
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reg = <0x01c18000 0x1000>;
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interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_SATA>, <&ccu CLK_SATA>;
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resets = <&ccu RST_BUS_SATA>;
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resets-name = "ahci";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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gmac: ethernet@1c50000 {
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compatible = "allwinner,sun8i-r40-gmac";
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syscon = <&ccu>;
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@ -69,7 +69,8 @@
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*/
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clock-frequency = <400000>;
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touchscreen: touchscreen@0 {
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touchscreen: touchscreen@40 {
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reg = <0x40>;
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interrupt-parent = <&pio>;
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interrupts = <1 5 IRQ_TYPE_EDGE_FALLING>; /* PB5 */
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pinctrl-names = "default";
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@ -95,7 +95,7 @@
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&i2c0 {
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status = "okay";
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axp22x: pmic@68 {
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axp22x: pmic@34 {
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compatible = "x-powers,axp221";
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reg = <0x34>;
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interrupt-parent = <&nmi_intc>;
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@ -1196,7 +1196,7 @@
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};
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};
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r_rsb: i2c@8003400 {
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r_rsb: rsb@8003400 {
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compatible = "allwinner,sun8i-a23-rsb";
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reg = <0x08003400 0x400>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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