ARM: 8602/1: factor out CSSELR/CCSIDR operations that use cp15 directly
Currently we use raw cp15 operations to access the cache setup data. This patch abstracts the CSSELR and CCSIDR accessors out to a header so that the implementation for them can be switched out as we do with other cpu/cachetype operations. Signed-off-by: Jonathan Austin <jonathan.austin@arm.com> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Tested-by: Andras Szemzo <sza@esh.hu> Tested-by: Joachim Eastwood <manabian@gmail.com> Tested-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -56,4 +56,28 @@ static inline unsigned int __attribute__((pure)) cacheid_is(unsigned int mask)
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(~__CACHEID_NEVER & __CACHEID_ARCH_MIN & mask & cacheid);
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}
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#define CSSELR_ICACHE 1
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#define CSSELR_DCACHE 0
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#define CSSELR_L1 (0 << 1)
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#define CSSELR_L2 (1 << 1)
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#define CSSELR_L3 (2 << 1)
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#define CSSELR_L4 (3 << 1)
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#define CSSELR_L5 (4 << 1)
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#define CSSELR_L6 (5 << 1)
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#define CSSELR_L7 (6 << 1)
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static inline void set_csselr(unsigned int cache_selector)
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{
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asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (cache_selector));
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}
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static inline unsigned int read_ccsidr(void)
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{
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unsigned int val;
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asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (val));
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return val;
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}
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#endif
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@ -290,12 +290,9 @@ static int cpu_has_aliasing_icache(unsigned int arch)
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/* arch specifies the register format */
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switch (arch) {
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case CPU_ARCH_ARMv7:
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asm("mcr p15, 2, %0, c0, c0, 0 @ set CSSELR"
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: /* No output operands */
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: "r" (1));
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set_csselr(CSSELR_ICACHE | CSSELR_L1);
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isb();
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asm("mrc p15, 1, %0, c0, c0, 0 @ read CCSIDR"
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: "=r" (id_reg));
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id_reg = read_ccsidr();
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line_size = 4 << ((id_reg & 0x7) + 2);
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num_sets = ((id_reg >> 13) & 0x7fff) + 1;
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aliasing_icache = (line_size * num_sets) > PAGE_SIZE;
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