ARM: EXYNOS: remove system mmu initialization from exynos tree
This removes System MMU initialization from arch/arm/mach-exynos/ to move them to DT and the exynos-iommu driver except gating clock definitions. Signed-off-by: KyongHo Cho <pullip.cho@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Joerg Roedel <joro@8bytes.org>
This commit is contained in:
Cho KyongHo
Joerg Roedel
parent
9931faca02
commit
25e9d28d92
@ -105,11 +105,6 @@ config EXYNOS4_SETUP_FIMD0
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help
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Common setup code for FIMD0.
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config EXYNOS_DEV_SYSMMU
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bool
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help
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Common setup code for SYSTEM MMU in EXYNOS platforms
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config EXYNOS4_DEV_USB_OHCI
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bool
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help
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@ -52,7 +52,6 @@ obj-$(CONFIG_ARCH_EXYNOS4) += dev-audio.o
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obj-$(CONFIG_EXYNOS4_DEV_AHCI) += dev-ahci.o
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obj-$(CONFIG_EXYNOS_DEV_DMA) += dma.o
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obj-$(CONFIG_EXYNOS4_DEV_USB_OHCI) += dev-ohci.o
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obj-$(CONFIG_EXYNOS_DEV_SYSMMU) += dev-sysmmu.o
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obj-$(CONFIG_ARCH_EXYNOS) += setup-i2c0.o
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obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
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@ -24,7 +24,6 @@
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/sysmmu.h>
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#include "common.h"
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#include "clock-exynos4.h"
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@ -709,53 +708,53 @@ static struct clk exynos4_init_clocks_off[] = {
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.enable = exynos4_clk_ip_peril_ctrl,
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.ctrlbit = (1 << 14),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.0",
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.enable = exynos4_clk_ip_mfc_ctrl,
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.ctrlbit = (1 << 1),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.1",
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.enable = exynos4_clk_ip_mfc_ctrl,
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.ctrlbit = (1 << 2),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.2",
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.enable = exynos4_clk_ip_tv_ctrl,
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.ctrlbit = (1 << 4),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.3",
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.enable = exynos4_clk_ip_cam_ctrl,
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.ctrlbit = (1 << 11),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.4",
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.enable = exynos4_clk_ip_image_ctrl,
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.ctrlbit = (1 << 4),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(fimc0, 5),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.5",
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.enable = exynos4_clk_ip_cam_ctrl,
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.ctrlbit = (1 << 7),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(fimc1, 6),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.6",
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.enable = exynos4_clk_ip_cam_ctrl,
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.ctrlbit = (1 << 8),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(fimc2, 7),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.7",
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.enable = exynos4_clk_ip_cam_ctrl,
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.ctrlbit = (1 << 9),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(fimc3, 8),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.8",
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.enable = exynos4_clk_ip_cam_ctrl,
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.ctrlbit = (1 << 10),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(fimd0, 10),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.10",
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.enable = exynos4_clk_ip_lcd0_ctrl,
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.ctrlbit = (1 << 4),
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}
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@ -26,7 +26,6 @@
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/sysmmu.h>
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#include "common.h"
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#include "clock-exynos4.h"
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@ -129,13 +128,13 @@ static struct clk init_clocks_off[] = {
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.enable = exynos4_clk_ip_lcd1_ctrl,
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.ctrlbit = (1 << 0),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.9",
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.enable = exynos4_clk_ip_image_ctrl,
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.ctrlbit = (1 << 3),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(fimd1, 11),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.11",
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.enable = exynos4_clk_ip_lcd1_ctrl,
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.ctrlbit = (1 << 4),
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}, {
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@ -26,7 +26,6 @@
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#include <mach/hardware.h>
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/sysmmu.h>
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#include "common.h"
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#include "clock-exynos4.h"
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@ -111,20 +110,30 @@ static struct clksrc_clk clksrcs[] = {
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static struct clk init_clocks_off[] = {
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{
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.9",
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.enable = exynos4_clk_ip_dmc_ctrl,
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.ctrlbit = (1 << 24),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.12",
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.enable = exynos4212_clk_ip_isp0_ctrl,
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.ctrlbit = (7 << 8),
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}, {
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.name = SYSMMU_CLOCK_NAME2,
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.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.13",
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.enable = exynos4212_clk_ip_isp1_ctrl,
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.ctrlbit = (1 << 4),
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}, {
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.name = "sysmmu",
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.devname = "exynos-sysmmu.14",
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.enable = exynos4212_clk_ip_isp0_ctrl,
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.ctrlbit = (1 << 11),
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}, {
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.name = "sysmmu",
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.devname = "exynos-sysmmu.15",
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.enable = exynos4212_clk_ip_isp0_ctrl,
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.ctrlbit = (1 << 12),
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}, {
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.name = "flite",
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.devname = "exynos-fimc-lite.0",
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@ -24,7 +24,6 @@
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#include <mach/map.h>
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#include <mach/regs-clock.h>
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#include <mach/sysmmu.h>
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#include "common.h"
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@ -859,73 +858,78 @@ static struct clk exynos5_init_clocks_off[] = {
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.enable = exynos5_clk_ip_gscl_ctrl,
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.ctrlbit = (1 << 3),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(mfc_l, 0),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.1",
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.enable = &exynos5_clk_ip_mfc_ctrl,
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.ctrlbit = (1 << 1),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(mfc_r, 1),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.0",
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.enable = &exynos5_clk_ip_mfc_ctrl,
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.ctrlbit = (1 << 2),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(tv, 2),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.2",
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.enable = &exynos5_clk_ip_disp1_ctrl,
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.ctrlbit = (1 << 9)
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(jpeg, 3),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.3",
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.enable = &exynos5_clk_ip_gen_ctrl,
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.ctrlbit = (1 << 7),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(rot, 4),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.4",
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.enable = &exynos5_clk_ip_gen_ctrl,
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.ctrlbit = (1 << 6)
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(gsc0, 5),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.5",
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.enable = &exynos5_clk_ip_gscl_ctrl,
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.ctrlbit = (1 << 7),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(gsc1, 6),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.6",
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.enable = &exynos5_clk_ip_gscl_ctrl,
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.ctrlbit = (1 << 8),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(gsc2, 7),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.7",
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.enable = &exynos5_clk_ip_gscl_ctrl,
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.ctrlbit = (1 << 9),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(gsc3, 8),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.8",
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.enable = &exynos5_clk_ip_gscl_ctrl,
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.ctrlbit = (1 << 10),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.9",
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.enable = &exynos5_clk_ip_isp0_ctrl,
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.ctrlbit = (0x3F << 8),
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}, {
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.name = SYSMMU_CLOCK_NAME2,
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.devname = SYSMMU_CLOCK_DEVNAME(isp, 9),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.10",
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.enable = &exynos5_clk_ip_isp1_ctrl,
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.ctrlbit = (0xF << 4),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(camif0, 12),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.11",
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.enable = &exynos5_clk_ip_disp1_ctrl,
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.ctrlbit = (1 << 8)
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}, {
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.name = "sysmmu",
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.devname = "exynos-sysmmu.12",
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.enable = &exynos5_clk_ip_gscl_ctrl,
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.ctrlbit = (1 << 11),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(camif1, 13),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.13",
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.enable = &exynos5_clk_ip_gscl_ctrl,
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.ctrlbit = (1 << 12),
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}, {
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.name = SYSMMU_CLOCK_NAME,
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.devname = SYSMMU_CLOCK_DEVNAME(2d, 14),
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.name = "sysmmu",
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.devname = "exynos-sysmmu.14",
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.enable = &exynos5_clk_ip_acp_ctrl,
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.ctrlbit = (1 << 7)
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}
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@ -1,274 +0,0 @@
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/* linux/arch/arm/mach-exynos/dev-sysmmu.c
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*
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* Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS - System MMU support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/platform_device.h>
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#include <linux/dma-mapping.h>
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#include <plat/cpu.h>
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#include <mach/map.h>
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#include <mach/irqs.h>
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#include <mach/sysmmu.h>
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static u64 exynos_sysmmu_dma_mask = DMA_BIT_MASK(32);
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#define SYSMMU_PLATFORM_DEVICE(ipname, devid) \
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static struct sysmmu_platform_data platdata_##ipname = { \
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.dbgname = #ipname, \
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}; \
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struct platform_device SYSMMU_PLATDEV(ipname) = \
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{ \
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.name = SYSMMU_DEVNAME_BASE, \
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.id = devid, \
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.dev = { \
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.dma_mask = &exynos_sysmmu_dma_mask, \
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.coherent_dma_mask = DMA_BIT_MASK(32), \
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.platform_data = &platdata_##ipname, \
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}, \
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}
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SYSMMU_PLATFORM_DEVICE(mfc_l, 0);
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SYSMMU_PLATFORM_DEVICE(mfc_r, 1);
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SYSMMU_PLATFORM_DEVICE(tv, 2);
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SYSMMU_PLATFORM_DEVICE(jpeg, 3);
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SYSMMU_PLATFORM_DEVICE(rot, 4);
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SYSMMU_PLATFORM_DEVICE(fimc0, 5); /* fimc* and gsc* exist exclusively */
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SYSMMU_PLATFORM_DEVICE(fimc1, 6);
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SYSMMU_PLATFORM_DEVICE(fimc2, 7);
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SYSMMU_PLATFORM_DEVICE(fimc3, 8);
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SYSMMU_PLATFORM_DEVICE(gsc0, 5);
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SYSMMU_PLATFORM_DEVICE(gsc1, 6);
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SYSMMU_PLATFORM_DEVICE(gsc2, 7);
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SYSMMU_PLATFORM_DEVICE(gsc3, 8);
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SYSMMU_PLATFORM_DEVICE(isp, 9);
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SYSMMU_PLATFORM_DEVICE(fimd0, 10);
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SYSMMU_PLATFORM_DEVICE(fimd1, 11);
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SYSMMU_PLATFORM_DEVICE(camif0, 12);
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SYSMMU_PLATFORM_DEVICE(camif1, 13);
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SYSMMU_PLATFORM_DEVICE(2d, 14);
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#define SYSMMU_RESOURCE_NAME(core, ipname) sysmmures_##core##_##ipname
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#define SYSMMU_RESOURCE(core, ipname) \
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static struct resource SYSMMU_RESOURCE_NAME(core, ipname)[] __initdata =
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#define DEFINE_SYSMMU_RESOURCE(core, mem, irq) \
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DEFINE_RES_MEM_NAMED(core##_PA_SYSMMU_##mem, SZ_4K, #mem), \
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DEFINE_RES_IRQ_NAMED(core##_IRQ_SYSMMU_##irq##_0, #mem)
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#define SYSMMU_RESOURCE_DEFINE(core, ipname, mem, irq) \
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SYSMMU_RESOURCE(core, ipname) { \
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DEFINE_SYSMMU_RESOURCE(core, mem, irq) \
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}
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struct sysmmu_resource_map {
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struct platform_device *pdev;
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struct resource *res;
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u32 rnum;
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struct device *pdd;
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char *clocknames;
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};
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#define SYSMMU_RESOURCE_MAPPING(core, ipname, resname) { \
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.pdev = &SYSMMU_PLATDEV(ipname), \
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.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
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.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
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.clocknames = SYSMMU_CLOCK_NAME, \
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}
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#define SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata) { \
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.pdev = &SYSMMU_PLATDEV(ipname), \
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.res = SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
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.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
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.clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2, \
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}
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#ifdef CONFIG_EXYNOS_DEV_PD
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#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) { \
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.pdev = &SYSMMU_PLATDEV(ipname), \
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.res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
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.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
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.clocknames = SYSMMU_CLOCK_NAME, \
|
||||
.pdd = &exynos##core##_device_pd[pd].dev, \
|
||||
}
|
||||
|
||||
#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) {\
|
||||
.pdev = &SYSMMU_PLATDEV(ipname), \
|
||||
.res = &SYSMMU_RESOURCE_NAME(EXYNOS##core, resname), \
|
||||
.rnum = ARRAY_SIZE(SYSMMU_RESOURCE_NAME(EXYNOS##core, resname)),\
|
||||
.clocknames = SYSMMU_CLOCK_NAME "," SYSMMU_CLOCK_NAME2, \
|
||||
.pdd = &exynos##core##_device_pd[pd].dev, \
|
||||
}
|
||||
#else
|
||||
#define SYSMMU_RESOURCE_MAPPING_PD(core, ipname, resname, pd) \
|
||||
SYSMMU_RESOURCE_MAPPING(core, ipname, resname)
|
||||
#define SYSMMU_RESOURCE_MAPPING_MCPD(core, ipname, resname, pd, pdata) \
|
||||
SYSMMU_RESOURCE_MAPPING_MC(core, ipname, resname, pdata)
|
||||
|
||||
#endif /* CONFIG_EXYNOS_DEV_PD */
|
||||
|
||||
#ifdef CONFIG_ARCH_EXYNOS4
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc0, FIMC0, FIMC0);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc1, FIMC1, FIMC1);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc2, FIMC2, FIMC2);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimc3, FIMC3, FIMC3);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS4, jpeg, JPEG, JPEG);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d, G2D, 2D);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS4, tv, TV, TV_M0);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS4, 2d_acp, 2D_ACP, 2D);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS4, rot, ROTATOR, ROTATOR);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd0, FIMD0, LCD0_M0);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS4, fimd1, FIMD1, LCD1_M1);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite0, FIMC_LITE0, FIMC_LITE0);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS4, flite1, FIMC_LITE1, FIMC_LITE1);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_r, MFC_R, MFC_M0);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS4, mfc_l, MFC_L, MFC_M1);
|
||||
SYSMMU_RESOURCE(EXYNOS4, isp) {
|
||||
DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_ISP, FIMC_ISP),
|
||||
DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_DRC, FIMC_DRC),
|
||||
DEFINE_SYSMMU_RESOURCE(EXYNOS4, FIMC_FD, FIMC_FD),
|
||||
DEFINE_SYSMMU_RESOURCE(EXYNOS4, ISPCPU, FIMC_CX),
|
||||
};
|
||||
|
||||
static struct sysmmu_resource_map sysmmu_resmap4[] __initdata = {
|
||||
SYSMMU_RESOURCE_MAPPING_PD(4, fimc0, fimc0, PD_CAM),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(4, fimc1, fimc1, PD_CAM),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(4, fimc2, fimc2, PD_CAM),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(4, fimc3, fimc3, PD_CAM),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(4, tv, tv, PD_TV),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(4, mfc_r, mfc_r, PD_MFC),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(4, mfc_l, mfc_l, PD_MFC),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(4, rot, rot, PD_LCD0),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(4, jpeg, jpeg, PD_CAM),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(4, fimd0, fimd0, PD_LCD0),
|
||||
};
|
||||
|
||||
static struct sysmmu_resource_map sysmmu_resmap4210[] __initdata = {
|
||||
SYSMMU_RESOURCE_MAPPING_PD(4, 2d, 2d, PD_LCD0),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(4, fimd1, fimd1, PD_LCD1),
|
||||
};
|
||||
|
||||
static struct sysmmu_resource_map sysmmu_resmap4212[] __initdata = {
|
||||
SYSMMU_RESOURCE_MAPPING(4, 2d, 2d_acp),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(4, camif0, flite0, PD_ISP),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(4, camif1, flite1, PD_ISP),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(4, isp, isp, PD_ISP),
|
||||
};
|
||||
#endif /* CONFIG_ARCH_EXYNOS4 */
|
||||
|
||||
#ifdef CONFIG_ARCH_EXYNOS5
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS5, jpeg, JPEG, JPEG);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS5, fimd1, FIMD1, FIMD1);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS5, 2d, 2D, 2D);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS5, rot, ROTATOR, ROTATOR);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS5, tv, TV, TV);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite0, LITE0, LITE0);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS5, flite1, LITE1, LITE1);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc0, GSC0, GSC0);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc1, GSC1, GSC1);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc2, GSC2, GSC2);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS5, gsc3, GSC3, GSC3);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_r, MFC_R, MFC_R);
|
||||
SYSMMU_RESOURCE_DEFINE(EXYNOS5, mfc_l, MFC_L, MFC_L);
|
||||
SYSMMU_RESOURCE(EXYNOS5, isp) {
|
||||
DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISP, ISP),
|
||||
DEFINE_SYSMMU_RESOURCE(EXYNOS5, DRC, DRC),
|
||||
DEFINE_SYSMMU_RESOURCE(EXYNOS5, FD, FD),
|
||||
DEFINE_SYSMMU_RESOURCE(EXYNOS5, ISPCPU, MCUISP),
|
||||
DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERC, SCALERCISP),
|
||||
DEFINE_SYSMMU_RESOURCE(EXYNOS5, SCALERP, SCALERPISP),
|
||||
DEFINE_SYSMMU_RESOURCE(EXYNOS5, ODC, ODC),
|
||||
DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS0, DIS0),
|
||||
DEFINE_SYSMMU_RESOURCE(EXYNOS5, DIS1, DIS1),
|
||||
DEFINE_SYSMMU_RESOURCE(EXYNOS5, 3DNR, 3DNR),
|
||||
};
|
||||
|
||||
static struct sysmmu_resource_map sysmmu_resmap5[] __initdata = {
|
||||
SYSMMU_RESOURCE_MAPPING(5, jpeg, jpeg),
|
||||
SYSMMU_RESOURCE_MAPPING(5, fimd1, fimd1),
|
||||
SYSMMU_RESOURCE_MAPPING(5, 2d, 2d),
|
||||
SYSMMU_RESOURCE_MAPPING(5, rot, rot),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(5, tv, tv, PD_DISP1),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(5, camif0, flite0, PD_GSCL),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(5, camif1, flite1, PD_GSCL),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(5, gsc0, gsc0, PD_GSCL),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(5, gsc1, gsc1, PD_GSCL),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(5, gsc2, gsc2, PD_GSCL),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(5, gsc3, gsc3, PD_GSCL),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(5, mfc_r, mfc_r, PD_MFC),
|
||||
SYSMMU_RESOURCE_MAPPING_PD(5, mfc_l, mfc_l, PD_MFC),
|
||||
SYSMMU_RESOURCE_MAPPING_MCPD(5, isp, isp, PD_ISP, mc_platdata),
|
||||
};
|
||||
#endif /* CONFIG_ARCH_EXYNOS5 */
|
||||
|
||||
static int __init init_sysmmu_platform_device(void)
|
||||
{
|
||||
int i, j;
|
||||
struct sysmmu_resource_map *resmap[2] = {NULL, NULL};
|
||||
int nmap[2] = {0, 0};
|
||||
|
||||
#ifdef CONFIG_ARCH_EXYNOS5
|
||||
if (soc_is_exynos5250()) {
|
||||
resmap[0] = sysmmu_resmap5;
|
||||
nmap[0] = ARRAY_SIZE(sysmmu_resmap5);
|
||||
nmap[1] = 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_EXYNOS4
|
||||
if (resmap[0] == NULL) {
|
||||
resmap[0] = sysmmu_resmap4;
|
||||
nmap[0] = ARRAY_SIZE(sysmmu_resmap4);
|
||||
}
|
||||
|
||||
if (soc_is_exynos4210()) {
|
||||
resmap[1] = sysmmu_resmap4210;
|
||||
nmap[1] = ARRAY_SIZE(sysmmu_resmap4210);
|
||||
}
|
||||
|
||||
if (soc_is_exynos4412() || soc_is_exynos4212()) {
|
||||
resmap[1] = sysmmu_resmap4212;
|
||||
nmap[1] = ARRAY_SIZE(sysmmu_resmap4212);
|
||||
}
|
||||
#endif
|
||||
|
||||
for (j = 0; j < 2; j++) {
|
||||
for (i = 0; i < nmap[j]; i++) {
|
||||
struct sysmmu_resource_map *map;
|
||||
struct sysmmu_platform_data *platdata;
|
||||
|
||||
map = &resmap[j][i];
|
||||
|
||||
map->pdev->dev.parent = map->pdd;
|
||||
|
||||
platdata = map->pdev->dev.platform_data;
|
||||
platdata->clockname = map->clocknames;
|
||||
|
||||
if (platform_device_add_resources(map->pdev, map->res,
|
||||
map->rnum)) {
|
||||
pr_err("%s: Failed to add device resources for "
|
||||
"%s.%d\n", __func__,
|
||||
map->pdev->name, map->pdev->id);
|
||||
continue;
|
||||
}
|
||||
|
||||
if (platform_device_register(map->pdev)) {
|
||||
pr_err("%s: Failed to register %s.%d\n",
|
||||
__func__, map->pdev->name,
|
||||
map->pdev->id);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(init_sysmmu_platform_device);
|
||||
@ -1,66 +0,0 @@
|
||||
/*
|
||||
* Copyright (c) 2011-2012 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS - System MMU support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef _ARM_MACH_EXYNOS_SYSMMU_H_
|
||||
#define _ARM_MACH_EXYNOS_SYSMMU_H_
|
||||
|
||||
struct sysmmu_platform_data {
|
||||
char *dbgname;
|
||||
/* comma(,) separated list of clock names for clock gating */
|
||||
char *clockname;
|
||||
};
|
||||
|
||||
#define SYSMMU_DEVNAME_BASE "exynos-sysmmu"
|
||||
|
||||
#define SYSMMU_CLOCK_NAME "sysmmu"
|
||||
#define SYSMMU_CLOCK_NAME2 "sysmmu_mc"
|
||||
|
||||
#ifdef CONFIG_EXYNOS_DEV_SYSMMU
|
||||
#include <linux/device.h>
|
||||
struct platform_device;
|
||||
|
||||
#define SYSMMU_PLATDEV(ipname) exynos_device_sysmmu_##ipname
|
||||
|
||||
extern struct platform_device SYSMMU_PLATDEV(mfc_l);
|
||||
extern struct platform_device SYSMMU_PLATDEV(mfc_r);
|
||||
extern struct platform_device SYSMMU_PLATDEV(tv);
|
||||
extern struct platform_device SYSMMU_PLATDEV(jpeg);
|
||||
extern struct platform_device SYSMMU_PLATDEV(rot);
|
||||
extern struct platform_device SYSMMU_PLATDEV(fimc0);
|
||||
extern struct platform_device SYSMMU_PLATDEV(fimc1);
|
||||
extern struct platform_device SYSMMU_PLATDEV(fimc2);
|
||||
extern struct platform_device SYSMMU_PLATDEV(fimc3);
|
||||
extern struct platform_device SYSMMU_PLATDEV(gsc0);
|
||||
extern struct platform_device SYSMMU_PLATDEV(gsc1);
|
||||
extern struct platform_device SYSMMU_PLATDEV(gsc2);
|
||||
extern struct platform_device SYSMMU_PLATDEV(gsc3);
|
||||
extern struct platform_device SYSMMU_PLATDEV(isp);
|
||||
extern struct platform_device SYSMMU_PLATDEV(fimd0);
|
||||
extern struct platform_device SYSMMU_PLATDEV(fimd1);
|
||||
extern struct platform_device SYSMMU_PLATDEV(camif0);
|
||||
extern struct platform_device SYSMMU_PLATDEV(camif1);
|
||||
extern struct platform_device SYSMMU_PLATDEV(2d);
|
||||
|
||||
#ifdef CONFIG_IOMMU_API
|
||||
static inline void platform_set_sysmmu(
|
||||
struct device *sysmmu, struct device *dev)
|
||||
{
|
||||
dev->archdata.iommu = sysmmu;
|
||||
}
|
||||
#endif
|
||||
|
||||
#else /* !CONFIG_EXYNOS_DEV_SYSMMU */
|
||||
#define platform_set_sysmmu(sysmmu, dev) do { } while (0)
|
||||
#endif
|
||||
|
||||
#define SYSMMU_CLOCK_DEVNAME(ipname, id) (SYSMMU_DEVNAME_BASE "." #id)
|
||||
|
||||
#endif /* _ARM_MACH_EXYNOS_SYSMMU_H_ */
|
||||
@ -80,6 +80,40 @@ static const struct of_dev_auxdata exynos4_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("arm,pl330", EXYNOS4_PA_MDMA1, "dma-pl330.2", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos4210-tmu", EXYNOS4_PA_TMU,
|
||||
"exynos-tmu", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13620000,
|
||||
"exynos-sysmmu.0", NULL), /* MFC_L */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13630000,
|
||||
"exynos-sysmmu.1", NULL), /* MFC_R */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E20000,
|
||||
"exynos-sysmmu.2", NULL), /* TV */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A60000,
|
||||
"exynos-sysmmu.3", NULL), /* JPEG */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A30000,
|
||||
"exynos-sysmmu.4", NULL), /* ROTATOR */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A20000,
|
||||
"exynos-sysmmu.5", NULL), /* FIMC0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A30000,
|
||||
"exynos-sysmmu.6", NULL), /* FIMC1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A40000,
|
||||
"exynos-sysmmu.7", NULL), /* FIMC2 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11A50000,
|
||||
"exynos-sysmmu.8", NULL), /* FIMC3 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12A20000,
|
||||
"exynos-sysmmu.9", NULL), /* G2D(4210) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A40000,
|
||||
"exynos-sysmmu.9", NULL), /* G2D(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11E20000,
|
||||
"exynos-sysmmu.10", NULL), /* FIMD0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12220000,
|
||||
"exynos-sysmmu.11", NULL), /* FIMD1(4210) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x12260000,
|
||||
"exynos-sysmmu.12", NULL), /* IS0(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x122B0000,
|
||||
"exynos-sysmmu.13", NULL), /* IS1(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123B0000,
|
||||
"exynos-sysmmu.14", NULL), /* FIMC-LITE0(4x12) */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x123C0000,
|
||||
"exynos-sysmmu.15", NULL), /* FIMC-LITE1(4x12) */
|
||||
{},
|
||||
};
|
||||
|
||||
|
||||
@ -104,6 +104,36 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
|
||||
OF_DEV_AUXDATA("samsung,mfc-v6", 0x11000000, "s5p-mfc-v6", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos5250-tmu", 0x10060000,
|
||||
"exynos-tmu", NULL),
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11210000,
|
||||
"exynos-sysmmu.0", "mfc"), /* MFC_L */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11200000,
|
||||
"exynos-sysmmu.1", "mfc"), /* MFC_R */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14650000,
|
||||
"exynos-sysmmu.2", NULL), /* TV */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11F20000,
|
||||
"exynos-sysmmu.3", "jpeg"), /* JPEG */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x11D40000,
|
||||
"exynos-sysmmu.4", NULL), /* ROTATOR */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E80000,
|
||||
"exynos-sysmmu.5", "gscl"), /* GSCL0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13E90000,
|
||||
"exynos-sysmmu.6", "gscl"), /* GSCL1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EA0000,
|
||||
"exynos-sysmmu.7", "gscl"), /* GSCL2 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13EB0000,
|
||||
"exynos-sysmmu.8", "gscl"), /* GSCL3 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13260000,
|
||||
"exynos-sysmmu.9", NULL), /* FIMC-IS0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x132C0000,
|
||||
"exynos-sysmmu.10", NULL), /* FIMC-IS1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x14640000,
|
||||
"exynos-sysmmu.11", NULL), /* FIMD1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C40000,
|
||||
"exynos-sysmmu.12", NULL), /* FIMC-LITE0 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x13C50000,
|
||||
"exynos-sysmmu.13", NULL), /* FIMC-LITE1 */
|
||||
OF_DEV_AUXDATA("samsung,exynos-sysmmu", 0x10A60000,
|
||||
"exynos-sysmmu.14", NULL), /* G2D */
|
||||
{},
|
||||
};
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user