forked from Minki/linux
drm/amd/powerplay: add smu9 header files for Vega10
Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Eric Huang <JinHuiEric.Huang@amd.com> Reviewed-by: Ken Wang <Qingqing.Wang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Eric Huang
Alex Deucher
parent
d1de1ed3df
commit
25e2196cc8
147
drivers/gpu/drm/amd/powerplay/inc/smu9.h
Normal file
147
drivers/gpu/drm/amd/powerplay/inc/smu9.h
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@ -0,0 +1,147 @@
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
|
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SMU9_H
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#define SMU9_H
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#pragma pack(push, 1)
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#define ENABLE_DEBUG_FEATURES
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/* Feature Control Defines */
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#define FEATURE_DPM_PREFETCHER_BIT 0
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#define FEATURE_DPM_GFXCLK_BIT 1
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#define FEATURE_DPM_UCLK_BIT 2
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#define FEATURE_DPM_SOCCLK_BIT 3
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#define FEATURE_DPM_UVD_BIT 4
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#define FEATURE_DPM_VCE_BIT 5
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#define FEATURE_ULV_BIT 6
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#define FEATURE_DPM_MP0CLK_BIT 7
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#define FEATURE_DPM_LINK_BIT 8
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#define FEATURE_DPM_DCEFCLK_BIT 9
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#define FEATURE_AVFS_BIT 10
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#define FEATURE_DS_GFXCLK_BIT 11
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#define FEATURE_DS_SOCCLK_BIT 12
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#define FEATURE_DS_LCLK_BIT 13
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#define FEATURE_PPT_BIT 14
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#define FEATURE_TDC_BIT 15
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#define FEATURE_THERMAL_BIT 16
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#define FEATURE_GFX_PER_CU_CG_BIT 17
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#define FEATURE_RM_BIT 18
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#define FEATURE_DS_DCEFCLK_BIT 19
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#define FEATURE_ACDC_BIT 20
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#define FEATURE_VR0HOT_BIT 21
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#define FEATURE_VR1HOT_BIT 22
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#define FEATURE_FW_CTF_BIT 23
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#define FEATURE_LED_DISPLAY_BIT 24
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#define FEATURE_FAN_CONTROL_BIT 25
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#define FEATURE_VOLTAGE_CONTROLLER_BIT 26
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#define FEATURE_SPARE_27_BIT 27
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#define FEATURE_SPARE_28_BIT 28
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#define FEATURE_SPARE_29_BIT 29
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#define FEATURE_SPARE_30_BIT 30
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#define FEATURE_SPARE_31_BIT 31
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#define NUM_FEATURES 32
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#define FFEATURE_DPM_PREFETCHER_MASK (1 << FEATURE_DPM_PREFETCHER_BIT )
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#define FFEATURE_DPM_GFXCLK_MASK (1 << FEATURE_DPM_GFXCLK_BIT )
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#define FFEATURE_DPM_UCLK_MASK (1 << FEATURE_DPM_UCLK_BIT )
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#define FFEATURE_DPM_SOCCLK_MASK (1 << FEATURE_DPM_SOCCLK_BIT )
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#define FFEATURE_DPM_UVD_MASK (1 << FEATURE_DPM_UVD_BIT )
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#define FFEATURE_DPM_VCE_MASK (1 << FEATURE_DPM_VCE_BIT )
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#define FFEATURE_ULV_MASK (1 << FEATURE_ULV_BIT )
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#define FFEATURE_DPM_MP0CLK_MASK (1 << FEATURE_DPM_MP0CLK_BIT )
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#define FFEATURE_DPM_LINK_MASK (1 << FEATURE_DPM_LINK_BIT )
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#define FFEATURE_DPM_DCEFCLK_MASK (1 << FEATURE_DPM_DCEFCLK_BIT )
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#define FFEATURE_AVFS_MASK (1 << FEATURE_AVFS_BIT )
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#define FFEATURE_DS_GFXCLK_MASK (1 << FEATURE_DS_GFXCLK_BIT )
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#define FFEATURE_DS_SOCCLK_MASK (1 << FEATURE_DS_SOCCLK_BIT )
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#define FFEATURE_DS_LCLK_MASK (1 << FEATURE_DS_LCLK_BIT )
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#define FFEATURE_PPT_MASK (1 << FEATURE_PPT_BIT )
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#define FFEATURE_TDC_MASK (1 << FEATURE_TDC_BIT )
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#define FFEATURE_THERMAL_MASK (1 << FEATURE_THERMAL_BIT )
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#define FFEATURE_GFX_PER_CU_CG_MASK (1 << FEATURE_GFX_PER_CU_CG_BIT )
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#define FFEATURE_RM_MASK (1 << FEATURE_RM_BIT )
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#define FFEATURE_DS_DCEFCLK_MASK (1 << FEATURE_DS_DCEFCLK_BIT )
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#define FFEATURE_ACDC_MASK (1 << FEATURE_ACDC_BIT )
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#define FFEATURE_VR0HOT_MASK (1 << FEATURE_VR0HOT_BIT )
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#define FFEATURE_VR1HOT_MASK (1 << FEATURE_VR1HOT_BIT )
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#define FFEATURE_FW_CTF_MASK (1 << FEATURE_FW_CTF_BIT )
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#define FFEATURE_LED_DISPLAY_MASK (1 << FEATURE_LED_DISPLAY_BIT )
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#define FFEATURE_FAN_CONTROL_MASK (1 << FEATURE_FAN_CONTROL_BIT )
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#define FFEATURE_VOLTAGE_CONTROLLER_MASK (1 << FEATURE_VOLTAGE_CONTROLLER_BIT )
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#define FFEATURE_SPARE_27_MASK (1 << FEATURE_SPARE_27_BIT )
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#define FFEATURE_SPARE_28_MASK (1 << FEATURE_SPARE_28_BIT )
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#define FFEATURE_SPARE_29_MASK (1 << FEATURE_SPARE_29_BIT )
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#define FFEATURE_SPARE_30_MASK (1 << FEATURE_SPARE_30_BIT )
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#define FFEATURE_SPARE_31_MASK (1 << FEATURE_SPARE_31_BIT )
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/* Workload types */
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#define WORKLOAD_VR_BIT 0
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#define WORKLOAD_FRTC_BIT 1
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#define WORKLOAD_VIDEO_BIT 2
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#define WORKLOAD_COMPUTE_BIT 3
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#define NUM_WORKLOADS 4
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/* ULV Client Masks */
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#define ULV_CLIENT_RLC_MASK 0x00000001
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#define ULV_CLIENT_UVD_MASK 0x00000002
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#define ULV_CLIENT_VCE_MASK 0x00000004
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#define ULV_CLIENT_SDMA0_MASK 0x00000008
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#define ULV_CLIENT_SDMA1_MASK 0x00000010
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#define ULV_CLIENT_JPEG_MASK 0x00000020
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#define ULV_CLIENT_GFXCLK_DPM_MASK 0x00000040
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#define ULV_CLIENT_UVD_DPM_MASK 0x00000080
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#define ULV_CLIENT_VCE_DPM_MASK 0x00000100
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#define ULV_CLIENT_MP0CLK_DPM_MASK 0x00000200
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#define ULV_CLIENT_UCLK_DPM_MASK 0x00000400
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#define ULV_CLIENT_SOCCLK_DPM_MASK 0x00000800
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#define ULV_CLIENT_DCEFCLK_DPM_MASK 0x00001000
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typedef struct {
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/* MP1_EXT_SCRATCH0 */
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uint32_t CurrLevel_GFXCLK : 4;
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uint32_t CurrLevel_UVD : 4;
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uint32_t CurrLevel_VCE : 4;
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uint32_t CurrLevel_LCLK : 4;
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uint32_t CurrLevel_MP0CLK : 4;
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uint32_t CurrLevel_UCLK : 4;
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uint32_t CurrLevel_SOCCLK : 4;
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uint32_t CurrLevel_DCEFCLK : 4;
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/* MP1_EXT_SCRATCH1 */
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uint32_t TargLevel_GFXCLK : 4;
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uint32_t TargLevel_UVD : 4;
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uint32_t TargLevel_VCE : 4;
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uint32_t TargLevel_LCLK : 4;
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uint32_t TargLevel_MP0CLK : 4;
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uint32_t TargLevel_UCLK : 4;
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uint32_t TargLevel_SOCCLK : 4;
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uint32_t TargLevel_DCEFCLK : 4;
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/* MP1_EXT_SCRATCH2-7 */
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uint32_t Reserved[6];
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} FwStatus_t;
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#pragma pack(pop)
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#endif
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418
drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h
Normal file
418
drivers/gpu/drm/amd/powerplay/inc/smu9_driver_if.h
Normal file
@ -0,0 +1,418 @@
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/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
|
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SMU9_DRIVER_IF_H
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#define SMU9_DRIVER_IF_H
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#include "smu9.h"
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/**** IMPORTANT ***
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* SMU TEAM: Always increment the interface version if
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* any structure is changed in this file
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*/
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#define SMU9_DRIVER_IF_VERSION 0xa
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#define NUM_GFXCLK_DPM_LEVELS 8
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#define NUM_UVD_DPM_LEVELS 8
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#define NUM_VCE_DPM_LEVELS 8
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#define NUM_MP0CLK_DPM_LEVELS 8
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#define NUM_UCLK_DPM_LEVELS 4
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#define NUM_SOCCLK_DPM_LEVELS 8
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#define NUM_DCEFCLK_DPM_LEVELS 8
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#define NUM_LINK_LEVELS 2
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#define MAX_GFXCLK_DPM_LEVEL (NUM_GFXCLK_DPM_LEVELS - 1)
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#define MAX_UVD_DPM_LEVEL (NUM_UVD_DPM_LEVELS - 1)
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#define MAX_VCE_DPM_LEVEL (NUM_VCE_DPM_LEVELS - 1)
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#define MAX_MP0CLK_DPM_LEVEL (NUM_MP0CLK_DPM_LEVELS - 1)
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#define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
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#define MAX_SOCCLK_DPM_LEVEL (NUM_SOCCLK_DPM_LEVELS - 1)
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#define MAX_DCEFCLK_DPM_LEVEL (NUM_DCEFCLK_DPM_LEVELS - 1)
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#define MAX_LINK_DPM_LEVEL (NUM_LINK_LEVELS - 1)
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#define MIN_GFXCLK_DPM_LEVEL 0
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#define MIN_UVD_DPM_LEVEL 0
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#define MIN_VCE_DPM_LEVEL 0
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#define MIN_MP0CLK_DPM_LEVEL 0
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#define MIN_UCLK_DPM_LEVEL 0
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#define MIN_SOCCLK_DPM_LEVEL 0
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#define MIN_DCEFCLK_DPM_LEVEL 0
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#define MIN_LINK_DPM_LEVEL 0
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#define NUM_EVV_VOLTAGE_LEVELS 8
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#define MAX_EVV_VOLTAGE_LEVEL (NUM_EVV_VOLTAGE_LEVELS - 1)
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#define MIN_EVV_VOLTAGE_LEVEL 0
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#define NUM_PSP_LEVEL_MAP 4
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/* Gemini Modes */
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#define PPSMC_GeminiModeNone 0 /* Single GPU board */
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#define PPSMC_GeminiModeMaster 1 /* Master GPU on a Gemini board */
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#define PPSMC_GeminiModeSlave 2 /* Slave GPU on a Gemini board */
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/* Voltage Modes for DPMs */
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#define VOLTAGE_MODE_AVFS_INTERPOLATE 0
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#define VOLTAGE_MODE_AVFS_WORST_CASE 1
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#define VOLTAGE_MODE_STATIC 2
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typedef struct {
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uint32_t FbMult; /* Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac */
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uint32_t SsFbMult; /* Spread FB Mult: bit 8:0 int, bit 31:16 frac */
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uint16_t SsSlewFrac;
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uint8_t SsOn;
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uint8_t Did; /* DID */
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} PllSetting_t;
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typedef struct {
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int32_t a0;
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int32_t a1;
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int32_t a2;
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} GbVdroopTable_t;
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typedef struct {
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int32_t m1;
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int32_t m2;
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int32_t b;
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uint8_t m1_shift;
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uint8_t m2_shift;
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uint8_t b_shift;
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uint8_t padding;
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} QuadraticInt_t;
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#define NUM_DSPCLK_LEVELS 8
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typedef enum {
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DSPCLK_DCEFCLK = 0,
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DSPCLK_DISPCLK,
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DSPCLK_PIXCLK,
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DSPCLK_PHYCLK,
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DSPCLK_COUNT,
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} DSPCLK_e;
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typedef struct {
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uint16_t Freq; /* in MHz */
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uint16_t Vid; /* min voltage in SVI2 VID */
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} DisplayClockTable_t;
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typedef struct {
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/* PowerTune */
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uint16_t SocketPowerLimit; /* Watts */
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uint16_t TdcLimit; /* Amps */
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uint16_t EdcLimit; /* Amps */
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uint16_t TedgeLimit; /* Celcius */
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uint16_t ThotspotLimit; /* Celcius */
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uint16_t ThbmLimit; /* Celcius */
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uint16_t Tvr_socLimit; /* Celcius */
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uint16_t Tvr_memLimit; /* Celcius */
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uint16_t Tliquid1Limit; /* Celcius */
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uint16_t Tliquid2Limit; /* Celcius */
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uint16_t TplxLimit; /* Celcius */
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uint16_t LoadLineResistance; /* in mOhms */
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uint32_t FitLimit; /* Failures in time (failures per million parts over the defined lifetime) */
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/* External Component Communication Settings */
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uint8_t Liquid1_I2C_address;
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uint8_t Liquid2_I2C_address;
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uint8_t Vr_I2C_address;
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uint8_t Plx_I2C_address;
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uint8_t GeminiMode;
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uint8_t spare17[3];
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uint32_t GeminiApertureHigh;
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uint32_t GeminiApertureLow;
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uint8_t Liquid_I2C_LineSCL;
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uint8_t Liquid_I2C_LineSDA;
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uint8_t Vr_I2C_LineSCL;
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uint8_t Vr_I2C_LineSDA;
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uint8_t Plx_I2C_LineSCL;
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uint8_t Plx_I2C_LineSDA;
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uint8_t paddingx[2];
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/* ULV Settings */
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uint8_t UlvOffsetVid; /* SVI2 VID */
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uint8_t UlvSmnclkDid; /* DID for ULV mode. 0 means CLK will not be modified in ULV. */
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uint8_t UlvMp1clkDid; /* DID for ULV mode. 0 means CLK will not be modified in ULV. */
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uint8_t UlvGfxclkBypass; /* 1 to turn off/bypass Gfxclk during ULV, 0 to leave Gfxclk on during ULV */
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/* VDDCR_SOC Voltages */
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uint8_t SocVid[NUM_EVV_VOLTAGE_LEVELS];
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/* This is the minimum voltage needed to run the SOC. */
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uint8_t MinVoltageVid; /* Minimum Voltage ("Vmin") of ASIC */
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uint8_t MaxVoltageVid; /* Maximum Voltage allowable */
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uint8_t MaxVidStep; /* Max VID step that SMU will request. Multiple steps are taken if voltage change exceeds this value. */
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uint8_t padding8;
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uint8_t UlvPhaseSheddingPsi0; /* set this to 1 to set PSI0/1 to 1 in ULV mode */
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uint8_t UlvPhaseSheddingPsi1; /* set this to 1 to set PSI0/1 to 1 in ULV mode */
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uint8_t padding8_2[2];
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/* SOC Frequencies */
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PllSetting_t GfxclkLevel [NUM_GFXCLK_DPM_LEVELS];
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uint8_t SocclkDid [NUM_SOCCLK_DPM_LEVELS]; /* DID */
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uint8_t SocDpmVoltageIndex [NUM_SOCCLK_DPM_LEVELS];
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uint8_t VclkDid [NUM_UVD_DPM_LEVELS]; /* DID */
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uint8_t DclkDid [NUM_UVD_DPM_LEVELS]; /* DID */
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uint8_t UvdDpmVoltageIndex [NUM_UVD_DPM_LEVELS];
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uint8_t EclkDid [NUM_VCE_DPM_LEVELS]; /* DID */
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uint8_t VceDpmVoltageIndex [NUM_VCE_DPM_LEVELS];
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uint8_t Mp0clkDid [NUM_MP0CLK_DPM_LEVELS]; /* DID */
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uint8_t Mp0DpmVoltageIndex [NUM_MP0CLK_DPM_LEVELS];
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DisplayClockTable_t DisplayClockTable[DSPCLK_COUNT][NUM_DSPCLK_LEVELS];
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QuadraticInt_t DisplayClock2Gfxclk[DSPCLK_COUNT];
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uint8_t GfxDpmVoltageMode;
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uint8_t SocDpmVoltageMode;
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uint8_t UclkDpmVoltageMode;
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uint8_t UvdDpmVoltageMode;
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uint8_t VceDpmVoltageMode;
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uint8_t Mp0DpmVoltageMode;
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uint8_t DisplayDpmVoltageMode;
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uint8_t padding8_3;
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uint16_t GfxclkSlewRate;
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uint16_t padding;
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uint32_t LowGfxclkInterruptThreshold; /* in units of 10KHz */
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/* Alpha parameters for clock averages. ("255"=1) */
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uint8_t GfxclkAverageAlpha;
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uint8_t SocclkAverageAlpha;
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uint8_t UclkAverageAlpha;
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uint8_t GfxActivityAverageAlpha;
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/* UCLK States */
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uint8_t MemVid[NUM_UCLK_DPM_LEVELS]; /* VID */
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PllSetting_t UclkLevel[NUM_UCLK_DPM_LEVELS]; /* Full PLL settings */
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uint8_t MemSocVoltageIndex[NUM_UCLK_DPM_LEVELS];
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uint8_t LowestUclkReservedForUlv; /* Set this to 1 if UCLK DPM0 is reserved for ULV-mode only */
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uint8_t paddingUclk[3];
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uint16_t NumMemoryChannels; /* Used for memory bandwidth calculations */
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uint16_t MemoryChannelWidth; /* Used for memory bandwidth calculations */
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/* CKS Settings */
|
||||
uint8_t CksEnable[NUM_GFXCLK_DPM_LEVELS];
|
||||
uint8_t CksVidOffset[NUM_GFXCLK_DPM_LEVELS];
|
||||
|
||||
/* MP0 Mapping Table */
|
||||
uint8_t PspLevelMap[NUM_PSP_LEVEL_MAP];
|
||||
|
||||
/* Link DPM Settings */
|
||||
uint8_t PcieGenSpeed[NUM_LINK_LEVELS]; /* 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
|
||||
uint8_t PcieLaneCount[NUM_LINK_LEVELS]; /* 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
|
||||
uint8_t LclkDid[NUM_LINK_LEVELS]; /* Leave at 0 to use hardcoded values in FW */
|
||||
uint8_t paddingLinkDpm[2];
|
||||
|
||||
/* Fan Control */
|
||||
uint16_t FanStopTemp; /* Celcius */
|
||||
uint16_t FanStartTemp; /* Celcius */
|
||||
|
||||
uint16_t FanGainEdge;
|
||||
uint16_t FanGainHotspot;
|
||||
uint16_t FanGainLiquid;
|
||||
uint16_t FanGainVrVddc;
|
||||
uint16_t FanGainVrMvdd;
|
||||
uint16_t FanGainPlx;
|
||||
uint16_t FanGainHbm;
|
||||
uint16_t FanPwmMin;
|
||||
uint16_t FanAcousticLimitRpm;
|
||||
uint16_t FanThrottlingRpm;
|
||||
uint16_t FanMaximumRpm;
|
||||
uint16_t FanTargetTemperature;
|
||||
uint16_t FanTargetGfxclk;
|
||||
uint8_t FanZeroRpmEnable;
|
||||
uint8_t FanSpare;
|
||||
|
||||
/* The following are AFC override parameters. Leave at 0 to use FW defaults. */
|
||||
int16_t FuzzyFan_ErrorSetDelta;
|
||||
int16_t FuzzyFan_ErrorRateSetDelta;
|
||||
int16_t FuzzyFan_PwmSetDelta;
|
||||
uint16_t FuzzyFan_Reserved;
|
||||
|
||||
/* GPIO Settings */
|
||||
uint8_t AcDcGpio; /* GPIO pin configured for AC/DC switching */
|
||||
uint8_t AcDcPolarity; /* GPIO polarity for AC/DC switching */
|
||||
uint8_t VR0HotGpio; /* GPIO pin configured for VR0 HOT event */
|
||||
uint8_t VR0HotPolarity; /* GPIO polarity for VR0 HOT event */
|
||||
uint8_t VR1HotGpio; /* GPIO pin configured for VR1 HOT event */
|
||||
uint8_t VR1HotPolarity; /* GPIO polarity for VR1 HOT event */
|
||||
uint8_t Padding1; /* replace GPIO pin configured for CTF */
|
||||
uint8_t Padding2; /* replace GPIO polarity for CTF */
|
||||
|
||||
/* LED Display Settings */
|
||||
uint8_t LedPin0; /* GPIO number for LedPin[0] */
|
||||
uint8_t LedPin1; /* GPIO number for LedPin[1] */
|
||||
uint8_t LedPin2; /* GPIO number for LedPin[2] */
|
||||
uint8_t padding8_4;
|
||||
|
||||
/* AVFS */
|
||||
uint8_t OverrideBtcGbCksOn;
|
||||
uint8_t OverrideAvfsGbCksOn;
|
||||
uint8_t PaddingAvfs8[2];
|
||||
|
||||
GbVdroopTable_t BtcGbVdroopTableCksOn;
|
||||
GbVdroopTable_t BtcGbVdroopTableCksOff;
|
||||
|
||||
QuadraticInt_t AvfsGbCksOn; /* Replacement equation */
|
||||
QuadraticInt_t AvfsGbCksOff; /* Replacement equation */
|
||||
|
||||
uint8_t StaticVoltageOffsetVid[NUM_GFXCLK_DPM_LEVELS]; /* This values are added on to the final voltage calculation */
|
||||
|
||||
/* Ageing Guardband Parameters */
|
||||
uint32_t AConstant[3];
|
||||
uint16_t DC_tol_sigma;
|
||||
uint16_t Platform_mean;
|
||||
uint16_t Platform_sigma;
|
||||
uint16_t PSM_Age_CompFactor;
|
||||
|
||||
uint32_t Reserved[20];
|
||||
|
||||
/* Padding - ignore */
|
||||
uint32_t MmHubPadding[7]; /* SMU internal use */
|
||||
|
||||
} PPTable_t;
|
||||
|
||||
typedef struct {
|
||||
uint16_t MinClock; // This is either DCEFCLK or SOCCLK (in MHz)
|
||||
uint16_t MaxClock; // This is either DCEFCLK or SOCCLK (in MHz)
|
||||
uint16_t MinUclk;
|
||||
uint16_t MaxUclk;
|
||||
|
||||
uint8_t WmSetting;
|
||||
uint8_t Padding[3];
|
||||
} WatermarkRowGeneric_t;
|
||||
|
||||
#define NUM_WM_RANGES 4
|
||||
|
||||
typedef enum {
|
||||
WM_SOCCLK = 0,
|
||||
WM_DCEFCLK,
|
||||
WM_COUNT,
|
||||
} WM_CLOCK_e;
|
||||
|
||||
typedef struct {
|
||||
/* Watermarks */
|
||||
WatermarkRowGeneric_t WatermarkRow[WM_COUNT][NUM_WM_RANGES];
|
||||
|
||||
uint32_t MmHubPadding[7]; /* SMU internal use */
|
||||
} Watermarks_t;
|
||||
|
||||
#ifdef PPTABLE_V10_SMU_VERSION
|
||||
typedef struct {
|
||||
float AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS];
|
||||
float AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS];
|
||||
float AvfsGbCksOff[NUM_GFXCLK_DPM_LEVELS];
|
||||
float AcBtcGbCksOff[NUM_GFXCLK_DPM_LEVELS];
|
||||
float DcBtcGb;
|
||||
|
||||
uint32_t MmHubPadding[7]; /* SMU internal use */
|
||||
} AvfsTable_t;
|
||||
#else
|
||||
typedef struct {
|
||||
uint32_t AvfsGbCksOn[NUM_GFXCLK_DPM_LEVELS];
|
||||
uint32_t AcBtcGbCksOn[NUM_GFXCLK_DPM_LEVELS];
|
||||
uint32_t AvfsGbCksOff[NUM_GFXCLK_DPM_LEVELS];
|
||||
uint32_t AcBtcGbCksOff[NUM_GFXCLK_DPM_LEVELS];
|
||||
uint32_t DcBtcGb;
|
||||
|
||||
uint32_t MmHubPadding[7]; /* SMU internal use */
|
||||
} AvfsTable_t;
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
uint16_t avgPsmCount[30];
|
||||
uint16_t minPsmCount[30];
|
||||
uint16_t avgPsmVoltage[30]; /* in mV with 2 fractional bits */
|
||||
uint16_t minPsmVoltage[30]; /* in mV with 2 fractional bits */
|
||||
|
||||
uint32_t MmHubPadding[7]; /* SMU internal use */
|
||||
} AvfsDebugTable_t;
|
||||
|
||||
typedef struct {
|
||||
uint8_t AvfsEn;
|
||||
uint8_t AvfsVersion;
|
||||
uint8_t Padding[2];
|
||||
|
||||
uint32_t VFT0_m1; /* Q16.16 */
|
||||
uint32_t VFT0_m2; /* Q16.16 */
|
||||
uint32_t VFT0_b; /* Q16.16 */
|
||||
|
||||
uint32_t VFT1_m1; /* Q16.16 */
|
||||
uint32_t VFT1_m2; /* Q16.16 */
|
||||
uint32_t VFT1_b; /* Q16.16 */
|
||||
|
||||
uint32_t VFT2_m1; /* Q16.16 */
|
||||
uint32_t VFT2_m2; /* Q16.16 */
|
||||
uint32_t VFT2_b; /* Q16.16 */
|
||||
|
||||
uint32_t AvfsGb0_m1; /* Q16.16 */
|
||||
uint32_t AvfsGb0_m2; /* Q16.16 */
|
||||
uint32_t AvfsGb0_b; /* Q16.16 */
|
||||
|
||||
uint32_t AcBtcGb_m1; /* Q16.16 */
|
||||
uint32_t AcBtcGb_m2; /* Q16.16 */
|
||||
uint32_t AcBtcGb_b; /* Q16.16 */
|
||||
|
||||
uint32_t AvfsTempCold;
|
||||
uint32_t AvfsTempMid;
|
||||
uint32_t AvfsTempHot;
|
||||
|
||||
uint32_t InversionVoltage; /* in mV with 2 fractional bits */
|
||||
|
||||
uint32_t P2V_m1; /* Q16.16 */
|
||||
uint32_t P2V_m2; /* Q16.16 */
|
||||
uint32_t P2V_b; /* Q16.16 */
|
||||
|
||||
uint32_t P2VCharzFreq; /* in 10KHz units */
|
||||
|
||||
uint32_t EnabledAvfsModules;
|
||||
|
||||
uint32_t MmHubPadding[7]; /* SMU internal use */
|
||||
} AvfsFuseOverride_t;
|
||||
|
||||
/* These defines are used with the following messages:
|
||||
* SMC_MSG_TransferTableDram2Smu
|
||||
* SMC_MSG_TransferTableSmu2Dram
|
||||
*/
|
||||
#define TABLE_PPTABLE 0
|
||||
#define TABLE_WATERMARKS 1
|
||||
#define TABLE_AVFS 2
|
||||
#define TABLE_AVFS_PSM_DEBUG 3
|
||||
#define TABLE_AVFS_FUSE_OVERRIDE 4
|
||||
#define TABLE_PMSTATUSLOG 5
|
||||
#define TABLE_COUNT 6
|
||||
|
||||
/* These defines are used with the SMC_MSG_SetUclkFastSwitch message. */
|
||||
#define UCLK_SWITCH_SLOW 0
|
||||
#define UCLK_SWITCH_FAST 1
|
||||
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user