forked from Minki/linux
dmaengine: ti: New driver for K3 UDMA
Split patch for review containing: defines, structs, io and low level functions and interrupt callbacks. DMA driver for Texas Instruments K3 NAVSS Unified DMA – Peripheral Root Complex (UDMA-P) The UDMA-P is intended to perform similar (but significantly upgraded) functions as the packet-oriented DMA used on previous SoC devices. The UDMA-P module supports the transmission and reception of various packet types. The UDMA-P is architected to facilitate the segmentation and reassembly of SoC DMA data structure compliant packets to/from smaller data blocks that are natively compatible with the specific requirements of each connected peripheral. Multiple Tx and Rx channels are provided within the DMA which allow multiple segmentation or reassembly operations to be ongoing. The DMA controller maintains state information for each of the channels which allows packet segmentation and reassembly operations to be time division multiplexed between channels in order to share the underlying DMA hardware. An external DMA scheduler is used to control the ordering and rate at which this multiplexing occurs for Transmit operations. The ordering and rate of Receive operations is indirectly controlled by the order in which blocks are pushed into the DMA on the Rx PSI-L interface. The UDMA-P also supports acting as both a UTC and UDMA-C for its internal channels. Channels in the UDMA-P can be configured to be either Packet-Based or Third-Party channels on a channel by channel basis. The initial driver supports: - MEM_TO_MEM (TR mode) - DEV_TO_MEM (Packet / TR mode) - MEM_TO_DEV (Packet / TR mode) - Cyclic (Packet / TR mode) - Metadata for descriptors Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Tested-by: Keerthy <j-keerthy@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com> Link: https://lore.kernel.org/r/20191223110458.30766-11-peter.ujfalusi@ti.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Peter Ujfalusi
Vinod Koul
parent
d3cd299bb1
commit
25dcb5dd7b
@ -34,6 +34,19 @@ config DMA_OMAP
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Enable support for the TI sDMA (System DMA or DMA4) controller. This
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DMA engine is found on OMAP and DRA7xx parts.
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config TI_K3_UDMA
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bool "Texas Instruments UDMA support"
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depends on ARCH_K3 || COMPILE_TEST
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depends on TI_SCI_PROTOCOL
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depends on TI_SCI_INTA_IRQCHIP
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select DMA_ENGINE
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select DMA_VIRTUAL_CHANNELS
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select TI_K3_RINGACC
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select TI_K3_PSIL
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help
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Enable support for the TI UDMA (Unified DMA) controller. This
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DMA engine is used in AM65x and j721e.
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config TI_K3_PSIL
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bool
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@ -2,5 +2,6 @@
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obj-$(CONFIG_TI_CPPI41) += cppi41.o
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obj-$(CONFIG_TI_EDMA) += edma.o
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obj-$(CONFIG_DMA_OMAP) += omap-dma.o
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obj-$(CONFIG_TI_K3_UDMA) += k3-udma.o
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obj-$(CONFIG_TI_K3_PSIL) += k3-psil.o k3-psil-am654.o k3-psil-j721e.o
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obj-$(CONFIG_TI_DMA_CROSSBAR) += dma-crossbar.o
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3371
drivers/dma/ti/k3-udma.c
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3371
drivers/dma/ti/k3-udma.c
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File diff suppressed because it is too large
Load Diff
120
drivers/dma/ti/k3-udma.h
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120
drivers/dma/ti/k3-udma.h
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@ -0,0 +1,120 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com
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*/
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#ifndef K3_UDMA_H_
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#define K3_UDMA_H_
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#include <linux/soc/ti/ti_sci_protocol.h>
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/* Global registers */
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#define UDMA_REV_REG 0x0
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#define UDMA_PERF_CTL_REG 0x4
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#define UDMA_EMU_CTL_REG 0x8
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#define UDMA_PSIL_TO_REG 0x10
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#define UDMA_UTC_CTL_REG 0x1c
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#define UDMA_CAP_REG(i) (0x20 + ((i) * 4))
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#define UDMA_RX_FLOW_ID_FW_OES_REG 0x80
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#define UDMA_RX_FLOW_ID_FW_STATUS_REG 0x88
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/* TX chan RT regs */
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#define UDMA_TCHAN_RT_CTL_REG 0x0
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#define UDMA_TCHAN_RT_SWTRIG_REG 0x8
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#define UDMA_TCHAN_RT_STDATA_REG 0x80
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#define UDMA_TCHAN_RT_PEER_REG(i) (0x200 + ((i) * 0x4))
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#define UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG \
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UDMA_TCHAN_RT_PEER_REG(0) /* PSI-L: 0x400 */
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#define UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG \
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UDMA_TCHAN_RT_PEER_REG(1) /* PSI-L: 0x401 */
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#define UDMA_TCHAN_RT_PEER_BCNT_REG \
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UDMA_TCHAN_RT_PEER_REG(4) /* PSI-L: 0x404 */
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#define UDMA_TCHAN_RT_PEER_RT_EN_REG \
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UDMA_TCHAN_RT_PEER_REG(8) /* PSI-L: 0x408 */
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#define UDMA_TCHAN_RT_PCNT_REG 0x400
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#define UDMA_TCHAN_RT_BCNT_REG 0x408
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#define UDMA_TCHAN_RT_SBCNT_REG 0x410
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/* RX chan RT regs */
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#define UDMA_RCHAN_RT_CTL_REG 0x0
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#define UDMA_RCHAN_RT_SWTRIG_REG 0x8
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#define UDMA_RCHAN_RT_STDATA_REG 0x80
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#define UDMA_RCHAN_RT_PEER_REG(i) (0x200 + ((i) * 0x4))
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#define UDMA_RCHAN_RT_PEER_STATIC_TR_XY_REG \
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UDMA_RCHAN_RT_PEER_REG(0) /* PSI-L: 0x400 */
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#define UDMA_RCHAN_RT_PEER_STATIC_TR_Z_REG \
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UDMA_RCHAN_RT_PEER_REG(1) /* PSI-L: 0x401 */
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#define UDMA_RCHAN_RT_PEER_BCNT_REG \
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UDMA_RCHAN_RT_PEER_REG(4) /* PSI-L: 0x404 */
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#define UDMA_RCHAN_RT_PEER_RT_EN_REG \
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UDMA_RCHAN_RT_PEER_REG(8) /* PSI-L: 0x408 */
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#define UDMA_RCHAN_RT_PCNT_REG 0x400
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#define UDMA_RCHAN_RT_BCNT_REG 0x408
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#define UDMA_RCHAN_RT_SBCNT_REG 0x410
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/* UDMA_TCHAN_RT_CTL_REG/UDMA_RCHAN_RT_CTL_REG */
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#define UDMA_CHAN_RT_CTL_EN BIT(31)
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#define UDMA_CHAN_RT_CTL_TDOWN BIT(30)
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#define UDMA_CHAN_RT_CTL_PAUSE BIT(29)
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#define UDMA_CHAN_RT_CTL_FTDOWN BIT(28)
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#define UDMA_CHAN_RT_CTL_ERROR BIT(0)
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/* UDMA_TCHAN_RT_PEER_RT_EN_REG/UDMA_RCHAN_RT_PEER_RT_EN_REG (PSI-L: 0x408) */
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#define UDMA_PEER_RT_EN_ENABLE BIT(31)
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#define UDMA_PEER_RT_EN_TEARDOWN BIT(30)
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#define UDMA_PEER_RT_EN_PAUSE BIT(29)
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#define UDMA_PEER_RT_EN_FLUSH BIT(28)
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#define UDMA_PEER_RT_EN_IDLE BIT(1)
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/*
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* UDMA_TCHAN_RT_PEER_STATIC_TR_XY_REG /
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* UDMA_RCHAN_RT_PEER_STATIC_TR_XY_REG
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*/
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#define PDMA_STATIC_TR_X_MASK GENMASK(26, 24)
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#define PDMA_STATIC_TR_X_SHIFT (24)
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#define PDMA_STATIC_TR_Y_MASK GENMASK(11, 0)
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#define PDMA_STATIC_TR_Y_SHIFT (0)
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#define PDMA_STATIC_TR_Y(x) \
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(((x) << PDMA_STATIC_TR_Y_SHIFT) & PDMA_STATIC_TR_Y_MASK)
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#define PDMA_STATIC_TR_X(x) \
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(((x) << PDMA_STATIC_TR_X_SHIFT) & PDMA_STATIC_TR_X_MASK)
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#define PDMA_STATIC_TR_XY_ACC32 BIT(30)
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#define PDMA_STATIC_TR_XY_BURST BIT(31)
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/*
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* UDMA_TCHAN_RT_PEER_STATIC_TR_Z_REG /
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* UDMA_RCHAN_RT_PEER_STATIC_TR_Z_REG
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*/
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#define PDMA_STATIC_TR_Z(x, mask) ((x) & (mask))
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struct udma_dev;
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struct udma_tchan;
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struct udma_rchan;
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struct udma_rflow;
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enum udma_rm_range {
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RM_RANGE_TCHAN = 0,
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RM_RANGE_RCHAN,
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RM_RANGE_RFLOW,
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RM_RANGE_LAST,
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};
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struct udma_tisci_rm {
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const struct ti_sci_handle *tisci;
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const struct ti_sci_rm_udmap_ops *tisci_udmap_ops;
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u32 tisci_dev_id;
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/* tisci information for PSI-L thread pairing/unpairing */
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const struct ti_sci_rm_psil_ops *tisci_psil_ops;
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u32 tisci_navss_dev_id;
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struct ti_sci_resource *rm_ranges[RM_RANGE_LAST];
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};
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#endif /* K3_UDMA_H_ */
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