forked from Minki/linux
nEPT: Add nEPT violation/misconfigration support
Inject nEPT fault to L1 guest. This patch is original from Xinhao. Reviewed-by: Xiao Guangrong <xiaoguangrong@linux.vnet.ibm.com> Signed-off-by: Jun Nakajima <jun.nakajima@intel.com> Signed-off-by: Xinhao Xu <xinhao.xu@intel.com> Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> Signed-off-by: Gleb Natapov <gleb@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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@ -286,6 +286,7 @@ struct kvm_mmu {
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u64 *pae_root;
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u64 *lm_root;
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u64 rsvd_bits_mask[2][4];
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u64 bad_mt_xwr;
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/*
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* Bitmap: bit set = last pte in walk
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@ -512,6 +513,9 @@ struct kvm_vcpu_arch {
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* instruction.
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*/
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bool write_fault_to_shadow_pgtable;
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/* set at EPT violation at this point */
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unsigned long exit_qualification;
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};
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struct kvm_lpage_info {
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@ -3519,6 +3519,8 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
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int maxphyaddr = cpuid_maxphyaddr(vcpu);
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u64 exb_bit_rsvd = 0;
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context->bad_mt_xwr = 0;
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if (!context->nx)
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exb_bit_rsvd = rsvd_bits(63, 63);
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switch (context->root_level) {
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@ -3574,7 +3576,40 @@ static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
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}
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}
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static void update_permission_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
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static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
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struct kvm_mmu *context, bool execonly)
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{
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int maxphyaddr = cpuid_maxphyaddr(vcpu);
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int pte;
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context->rsvd_bits_mask[0][3] =
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rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7);
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context->rsvd_bits_mask[0][2] =
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rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
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context->rsvd_bits_mask[0][1] =
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rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6);
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context->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51);
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/* large page */
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context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
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context->rsvd_bits_mask[1][2] =
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rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29);
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context->rsvd_bits_mask[1][1] =
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rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20);
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context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
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for (pte = 0; pte < 64; pte++) {
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int rwx_bits = pte & 7;
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int mt = pte >> 3;
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if (mt == 0x2 || mt == 0x3 || mt == 0x7 ||
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rwx_bits == 0x2 || rwx_bits == 0x6 ||
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(rwx_bits == 0x4 && !execonly))
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context->bad_mt_xwr |= (1ull << pte);
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}
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}
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static void update_permission_bitmask(struct kvm_vcpu *vcpu,
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struct kvm_mmu *mmu, bool ept)
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{
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unsigned bit, byte, pfec;
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u8 map;
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@ -3592,12 +3627,16 @@ static void update_permission_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu
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w = bit & ACC_WRITE_MASK;
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u = bit & ACC_USER_MASK;
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/* Not really needed: !nx will cause pte.nx to fault */
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x |= !mmu->nx;
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/* Allow supervisor writes if !cr0.wp */
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w |= !is_write_protection(vcpu) && !uf;
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/* Disallow supervisor fetches of user code if cr4.smep */
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x &= !(smep && u && !uf);
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if (!ept) {
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/* Not really needed: !nx will cause pte.nx to fault */
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x |= !mmu->nx;
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/* Allow supervisor writes if !cr0.wp */
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w |= !is_write_protection(vcpu) && !uf;
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/* Disallow supervisor fetches of user code if cr4.smep */
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x &= !(smep && u && !uf);
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} else
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/* Not really needed: no U/S accesses on ept */
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u = 1;
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fault = (ff && !x) || (uf && !u) || (wf && !w);
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map |= fault << bit;
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@ -3632,7 +3671,7 @@ static int paging64_init_context_common(struct kvm_vcpu *vcpu,
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context->root_level = level;
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reset_rsvds_bits_mask(vcpu, context);
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update_permission_bitmask(vcpu, context);
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update_permission_bitmask(vcpu, context, false);
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update_last_pte_bitmap(vcpu, context);
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ASSERT(is_pae(vcpu));
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@ -3662,7 +3701,7 @@ static int paging32_init_context(struct kvm_vcpu *vcpu,
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context->root_level = PT32_ROOT_LEVEL;
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reset_rsvds_bits_mask(vcpu, context);
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update_permission_bitmask(vcpu, context);
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update_permission_bitmask(vcpu, context, false);
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update_last_pte_bitmap(vcpu, context);
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context->new_cr3 = paging_new_cr3;
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@ -3724,7 +3763,7 @@ static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
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context->gva_to_gpa = paging32_gva_to_gpa;
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}
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update_permission_bitmask(vcpu, context);
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update_permission_bitmask(vcpu, context, false);
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update_last_pte_bitmap(vcpu, context);
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return 0;
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@ -3803,7 +3842,7 @@ static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
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g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
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}
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update_permission_bitmask(vcpu, g_context);
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update_permission_bitmask(vcpu, g_context, false);
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update_last_pte_bitmap(vcpu, g_context);
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return 0;
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@ -129,10 +129,10 @@ static inline void FNAME(protect_clean_gpte)(unsigned *access, unsigned gpte)
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static bool FNAME(is_rsvd_bits_set)(struct kvm_mmu *mmu, u64 gpte, int level)
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{
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int bit7;
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int bit7 = (gpte >> 7) & 1, low6 = gpte & 0x3f;
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bit7 = (gpte >> 7) & 1;
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return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
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return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) |
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((mmu->bad_mt_xwr & (1ull << low6)) != 0);
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}
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static inline int FNAME(is_present_gpte)(unsigned long pte)
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@ -386,6 +386,25 @@ error:
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walker->fault.vector = PF_VECTOR;
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walker->fault.error_code_valid = true;
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walker->fault.error_code = errcode;
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#if PTTYPE == PTTYPE_EPT
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/*
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* Use PFERR_RSVD_MASK in error_code to to tell if EPT
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* misconfiguration requires to be injected. The detection is
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* done by is_rsvd_bits_set() above.
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*
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* We set up the value of exit_qualification to inject:
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* [2:0] - Derive from [2:0] of real exit_qualification at EPT violation
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* [5:3] - Calculated by the page walk of the guest EPT page tables
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* [7:8] - Derived from [7:8] of real exit_qualification
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*
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* The other bits are set to 0.
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*/
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if (!(errcode & PFERR_RSVD_MASK)) {
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vcpu->arch.exit_qualification &= 0x187;
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vcpu->arch.exit_qualification |= ((pt_access & pte) & 0x7) << 3;
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}
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#endif
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walker->fault.address = addr;
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walker->fault.nested_page_fault = mmu != vcpu->arch.walk_mmu;
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@ -5317,9 +5317,13 @@ static int handle_ept_violation(struct kvm_vcpu *vcpu)
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/* It is a write fault? */
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error_code = exit_qualification & (1U << 1);
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/* It is a fetch fault? */
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error_code |= (exit_qualification & (1U << 2)) << 2;
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/* ept page table is present? */
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error_code |= (exit_qualification >> 3) & 0x1;
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vcpu->arch.exit_qualification = exit_qualification;
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return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
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}
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@ -7348,6 +7352,21 @@ static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
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entry->ecx |= bit(X86_FEATURE_VMX);
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}
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static void nested_ept_inject_page_fault(struct kvm_vcpu *vcpu,
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struct x86_exception *fault)
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{
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struct vmcs12 *vmcs12;
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nested_vmx_vmexit(vcpu);
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vmcs12 = get_vmcs12(vcpu);
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if (fault->error_code & PFERR_RSVD_MASK)
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vmcs12->vm_exit_reason = EXIT_REASON_EPT_MISCONFIG;
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else
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vmcs12->vm_exit_reason = EXIT_REASON_EPT_VIOLATION;
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vmcs12->exit_qualification = vcpu->arch.exit_qualification;
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vmcs12->guest_physical_address = fault->address;
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}
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/*
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* prepare_vmcs02 is called when the L1 guest hypervisor runs its nested
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* L2 guest. L1 has a vmcs for L2 (vmcs12), and this function "merges" it
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