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drm/nouveau/gr/gf100-: virtualise init_fecs_exceptions + apply fixes from traces

Browse Source 
The value for GF100 has changed here, but it matches RM now.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs 2018-05-08 20:39:46 +10:00
parent 7c76ebb65a
commit 2585a1b131
17 changed files with 47 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View File

@ -1914,6 +1914,13 @@ gf100_gr_new_(const struct gf100_gr_func *func, struct nvkm_device *device,
return 0;
}
void
gf100_gr_init_fecs_exceptions(struct gf100_gr *gr)
{
const u32 data = gr->firmware ? 0x000e0000 : 0x000e0001;
nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, data);
}
void
gf100_gr_init_gpc_mmu(struct gf100_gr *gr)
{
@ -2010,7 +2017,8 @@ gf100_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, 0x40013c, 0xffffffff);
nvkm_wr32(device, 0x400124, 0x00000002);
nvkm_wr32(device, 0x409c24, 0x000f0000);
gr->func->init_fecs_exceptions(gr);
nvkm_wr32(device, 0x404000, 0xc0000000);
nvkm_wr32(device, 0x404600, 0xc0000000);
nvkm_wr32(device, 0x408030, 0xc0000000);
@ -2088,6 +2096,7 @@ gf100_gr = {
.init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
.init_zcull = gf100_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.mmio = gf100_gr_pack_mmio,
.fecs.ucode = &gf100_gr_fecs_ucode,
.gpccs.ucode = &gf100_gr_gpccs_ucode,

3
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
View File

@ -130,6 +130,7 @@ struct gf100_gr_func {
void (*init_rop_active_fbps)(struct gf100_gr *);
void (*init_bios_2)(struct gf100_gr *);
void (*init_swdx_pes_mask)(struct gf100_gr *);
void (*init_fecs_exceptions)(struct gf100_gr *);
void (*init_ppc_exceptions)(struct gf100_gr *);
void (*set_hww_esr_report_mask)(struct gf100_gr *);
const struct gf100_gr_pack *mmio;
@ -151,6 +152,7 @@ int gf100_gr_init(struct gf100_gr *);
void gf100_gr_init_vsc_stream_master(struct gf100_gr *);
void gf100_gr_init_zcull(struct gf100_gr *);
void gf100_gr_init_num_active_ltcs(struct gf100_gr *);
void gf100_gr_init_fecs_exceptions(struct gf100_gr *);
void gf117_gr_init_zcull(struct gf100_gr *);
@ -166,6 +168,7 @@ void gm200_gr_init_num_active_ltcs(struct gf100_gr *);
int gp100_gr_init(struct gf100_gr *);
void gp100_gr_init_rop_active_fbps(struct gf100_gr *);
void gp100_gr_init_fecs_exceptions(struct gf100_gr *);
void gp102_gr_init_swdx_pes_mask(struct gf100_gr *);

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf104.c
View File

@ -119,6 +119,7 @@ gf104_gr = {
.init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
.init_zcull = gf100_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.mmio = gf104_gr_pack_mmio,
.fecs.ucode = &gf100_gr_fecs_ucode,
.gpccs.ucode = &gf100_gr_gpccs_ucode,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf108.c
View File

@ -117,6 +117,7 @@ gf108_gr = {
.init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
.init_zcull = gf100_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.mmio = gf108_gr_pack_mmio,
.fecs.ucode = &gf100_gr_fecs_ucode,
.gpccs.ucode = &gf100_gr_gpccs_ucode,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf110.c
View File

@ -91,6 +91,7 @@ gf110_gr = {
.init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
.init_zcull = gf100_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.mmio = gf110_gr_pack_mmio,
.fecs.ucode = &gf100_gr_fecs_ucode,
.gpccs.ucode = &gf100_gr_gpccs_ucode,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf117.c
View File

@ -155,6 +155,7 @@ gf117_gr = {
.init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.mmio = gf117_gr_pack_mmio,
.fecs.ucode = &gf117_gr_fecs_ucode,
.gpccs.ucode = &gf117_gr_gpccs_ucode,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf119.c
View File

@ -182,6 +182,7 @@ gf119_gr = {
.init_vsc_stream_master = gf100_gr_init_vsc_stream_master,
.init_zcull = gf100_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.mmio = gf119_gr_pack_mmio,
.fecs.ucode = &gf100_gr_fecs_ucode,
.gpccs.ucode = &gf100_gr_gpccs_ucode,

14
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk104.c
View File

@ -380,6 +380,15 @@ gk104_clkgate_pack[] = {
* PGRAPH engine/subdev functions
******************************************************************************/
static void
gk104_gr_init_fecs_exceptions(struct gf100_gr *gr)
{
struct nvkm_device *device = gr->base.engine.subdev.device;
nvkm_wr32(device, 0x409ffc, 0x00000000);
nvkm_wr32(device, 0x409c14, 0x00003e3e);
nvkm_wr32(device, 0x409c24, 0x000f0001);
}
void
gk104_gr_init_rop_active_fbps(struct gf100_gr *gr)
{
@ -436,9 +445,7 @@ gk104_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, 0x40013c, 0xffffffff);
nvkm_wr32(device, 0x400124, 0x00000002);
nvkm_wr32(device, 0x409ffc, 0x00000000);
nvkm_wr32(device, 0x409c14, 0x00003e3e);
nvkm_wr32(device, 0x409c24, 0x000f0001);
gr->func->init_fecs_exceptions(gr);
nvkm_wr32(device, 0x404000, 0xc0000000);
nvkm_wr32(device, 0x404600, 0xc0000000);
nvkm_wr32(device, 0x408030, 0xc0000000);
@ -519,6 +526,7 @@ gk104_gr = {
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.init_fecs_exceptions = gk104_gr_init_fecs_exceptions,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.mmio = gk104_gr_pack_mmio,
.fecs.ucode = &gk104_gr_fecs_ucode,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c
View File

@ -342,6 +342,7 @@ gk110_gr = {
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.mmio = gk110_gr_pack_mmio,
.fecs.ucode = &gk110_gr_fecs_ucode,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110b.c
View File

@ -108,6 +108,7 @@ gk110b_gr = {
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.mmio = gk110b_gr_pack_mmio,
.fecs.ucode = &gk110_gr_fecs_ucode,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gk208.c
View File

@ -167,6 +167,7 @@ gk208_gr = {
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.mmio = gk208_gr_pack_mmio,
.fecs.ucode = &gk208_gr_fecs_ucode,

3
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm107.c
View File

@ -371,7 +371,7 @@ gm107_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, 0x400100, 0xffffffff);
nvkm_wr32(device, 0x40013c, 0xffffffff);
nvkm_wr32(device, 0x400124, 0x00000002);
nvkm_wr32(device, 0x409c24, 0x000e0000);
gr->func->init_fecs_exceptions(gr);
nvkm_wr32(device, 0x404000, 0xc0000000);
nvkm_wr32(device, 0x404600, 0xc0000000);
@ -455,6 +455,7 @@ gm107_gr = {
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_rop_active_fbps = gk104_gr_init_rop_active_fbps,
.init_bios_2 = gm107_gr_init_bios_2,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.mmio = gm107_gr_pack_mmio,
.fecs.ucode = &gm107_gr_fecs_ucode,

3
drivers/gpu/drm/nouveau/nvkm/engine/gr/gm200.c
View File

@ -91,7 +91,7 @@ gm200_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, 0x400100, 0xffffffff);
nvkm_wr32(device, 0x40013c, 0xffffffff);
nvkm_wr32(device, 0x400124, 0x00000002);
nvkm_wr32(device, 0x409c24, 0x000e0000);
gr->func->init_fecs_exceptions(gr);
nvkm_wr32(device, 0x405848, 0xc0000000);
nvkm_wr32(device, 0x40584c, 0x00000001);
nvkm_wr32(device, 0x404000, 0xc0000000);
@ -193,6 +193,7 @@ gm200_gr = {
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
.init_rop_active_fbps = gm200_gr_init_rop_active_fbps,
.init_fecs_exceptions = gf100_gr_init_fecs_exceptions,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.rops = gm200_gr_rops,
.ppc_nr = 2,

9
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp100.c
View File

@ -30,6 +30,12 @@
* PGRAPH engine/subdev functions
******************************************************************************/
void
gp100_gr_init_fecs_exceptions(struct gf100_gr *gr)
{
nvkm_wr32(gr->base.engine.subdev.device, 0x409c24, 0x000f0002);
}
void
gp100_gr_init_rop_active_fbps(struct gf100_gr *gr)
{
@ -63,7 +69,7 @@ gp100_gr_init(struct gf100_gr *gr)
nvkm_wr32(device, 0x400100, 0xffffffff);
nvkm_wr32(device, 0x40013c, 0xffffffff);
nvkm_wr32(device, 0x400124, 0x00000002);
nvkm_wr32(device, 0x409c24, 0x000f0002);
gr->func->init_fecs_exceptions(gr);
nvkm_wr32(device, 0x405848, 0xc0000000);
nvkm_mask(device, 0x40584c, 0x00000000, 0x00000001);
nvkm_wr32(device, 0x404000, 0xc0000000);
@ -127,6 +133,7 @@ gp100_gr = {
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.rops = gm200_gr_rops,
.ppc_nr = 2,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp102.c
View File

@ -49,6 +49,7 @@ gp102_gr = {
.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.rops = gm200_gr_rops,
.ppc_nr = 3,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp107.c
View File

@ -35,6 +35,7 @@ gp107_gr = {
.init_num_active_ltcs = gm200_gr_init_num_active_ltcs,
.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
.init_swdx_pes_mask = gp102_gr_init_swdx_pes_mask,
.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.rops = gm200_gr_rops,
.ppc_nr = 1,

1
drivers/gpu/drm/nouveau/nvkm/engine/gr/gp10b.c
View File

@ -33,6 +33,7 @@ gp10b_gr = {
.init_zcull = gf117_gr_init_zcull,
.init_num_active_ltcs = gf100_gr_init_num_active_ltcs,
.init_rop_active_fbps = gp100_gr_init_rop_active_fbps,
.init_fecs_exceptions = gp100_gr_init_fecs_exceptions,
.init_ppc_exceptions = gk104_gr_init_ppc_exceptions,
.rops = gm200_gr_rops,
.ppc_nr = 1,