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dt-bindings:iio:adc:fsl,vf610-adc conversion to yaml.

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A simple conversion of this freescale ADC binding from txt to yaml.
For maintainer I went with Fugang Duan as the original author of the
binding. Would be great to have confirmation of this.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Fugang Duan <fugang.duan@nxp.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20200909175946.395313-2-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2020-09-09 18:59:27 +01:00
parent 44a76de8ca
commit 22daffe295
2 changed files with 81 additions and 36 deletions
Documentation/devicetree/bindings/iio/adc
fsl,vf610-adc.yamlvf610-adc.txt

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Documentation/devicetree/bindings/iio/adc/fsl,vf610-adc.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/iio/adc/fsl,vf610-adc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ADC found on Freescale vf610 and similar SoCs
maintainers:
- Fugang Duan <fugang.duan@nxp.com>
description:
ADCs found on vf610/i.MX6slx and upward SoCs from Freescale.
properties:
compatible:
const: fsl,vf610-adc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
description: ADC source clock (ipg clock)
maxItems: 1
clock-names:
const: adc
vref-supply:
description: ADC reference voltage supply.
fsl,adck-max-frequency:
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 3
maxItems: 3
description: |
Maximum frequencies from datasheet operating requirements.
Three values necessary to cover the 3 conversion modes.
* Frequency in normal mode (ADLPC=0, ADHSC=0)
* Frequency in high-speed mode (ADLPC=0, ADHSC=1)
* Frequency in low-power mode (ADLPC=1, ADHSC=0)
min-sample-time:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Minimum sampling time in nanoseconds. This value has
to be chosen according to the conversion mode and the connected analog
source resistance (R_as) and capacitance (C_as). Refer the datasheet's
operating requirements. A safe default across a wide range of R_as and
C_as as well as conversion modes is 1000ns.
"#io-channel-cells":
const: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- vref-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/vf610-clock.h>
adc@4003b000 {
compatible = "fsl,vf610-adc";
reg = <0x4003b000 0x1000>;
interrupts = <0 53 0x04>;
clocks = <&clks VF610_CLK_ADC0>;
clock-names = "adc";
fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>;
vref-supply = <&reg_vcc_3v3_mcu>;
min-sample-time = <10000>;
};
...

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Documentation/devicetree/bindings/iio/adc/vf610-adc.txt
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@ -1,36 +0,0 @@
Freescale vf610 Analog to Digital Converter bindings
The devicetree bindings are for the new ADC driver written for
vf610/i.MX6slx and upward SoCs from Freescale.
Required properties:
- compatible: Should contain "fsl,vf610-adc"
- reg: Offset and length of the register set for the device
- interrupts: Should contain the interrupt for the device
- clocks: The clock is needed by the ADC controller, ADC clock source is ipg clock.
- clock-names: Must contain "adc", matching entry in the clocks property.
- vref-supply: The regulator supply ADC reference voltage.
Recommended properties:
- fsl,adck-max-frequency: Maximum frequencies according to datasheets operating
requirements. Three values are required, depending on conversion mode:
- Frequency in normal mode (ADLPC=0, ADHSC=0)
- Frequency in high-speed mode (ADLPC=0, ADHSC=1)
- Frequency in low-power mode (ADLPC=1, ADHSC=0)
- min-sample-time: Minimum sampling time in nanoseconds. This value has
to be chosen according to the conversion mode and the connected analog
source resistance (R_as) and capacitance (C_as). Refer the datasheet's
operating requirements. A safe default across a wide range of R_as and
C_as as well as conversion modes is 1000ns.
Example:
adc0: adc@4003b000 {
compatible = "fsl,vf610-adc";
reg = <0x4003b000 0x1000>;
interrupts = <0 53 0x04>;
clocks = <&clks VF610_CLK_ADC0>;
clock-names = "adc";
fsl,adck-max-frequency = <30000000>, <40000000>,
<20000000>;
vref-supply = <&reg_vcc_3v3_mcu>;
};