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staging: comedi: tests: ni_routes_test: Lines should not end with a '('

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Fix checkpatch.pl issues such as the following:

CHECK: Lines should not end with a '('
+	unittest(

Cc: Spencer E. Olson <olsonse@umich.edu>
Signed-off-by: Ian Abbott <abbotti@mev.co.uk>
Link: https://lore.kernel.org/r/20210407140142.447250-5-abbotti@mev.co.uk
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ian Abbott 2021-04-07 15:01:41 +01:00 committed by Greg Kroah-Hartman
parent 2628ca5f8e
commit 228e55617c
1 changed files with 10 additions and 13 deletions
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9
drivers/staging/comedi/drivers/tests/ni_routes_test.c
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@ -243,12 +243,10 @@ void test_ni_assign_device_routes(void)
unittest(route_set_sources_in_order(devroutes), unittest(route_set_sources_in_order(devroutes),
"all pci-6070e route_set->src's in order of signal source\n"); "all pci-6070e route_set->src's in order of signal source\n");
unittest( unittest(RVI(table, B(PXI_Star), B(NI_AI_SampleClock)) == V(17) &&
RVI(table, B(PXI_Star), B(NI_AI_SampleClock)) == V(17) &&
RVI(table, B(NI_10MHzRefClock), B(TRIGGER_LINE(0))) == 0 && RVI(table, B(NI_10MHzRefClock), B(TRIGGER_LINE(0))) == 0 &&
RVI(table, B(NI_AI_ConvertClock), B(NI_PFI(0))) == 0 && RVI(table, B(NI_AI_ConvertClock), B(NI_PFI(0))) == 0 &&
RVI(table, B(NI_AI_ConvertClock), B(NI_PFI(2))) == RVI(table, B(NI_AI_ConvertClock), B(NI_PFI(2))) == V(NI_PFI_OUTPUT_AI_CONVERT),
V(NI_PFI_OUTPUT_AI_CONVERT),
"pci-6070e finds e-series route_values table\n"); "pci-6070e finds e-series route_values table\n");
olddevroutes = devroutes; olddevroutes = devroutes;
@ -263,8 +261,7 @@ void test_ni_assign_device_routes(void)
"find device pci-6220\n"); "find device pci-6220\n");
unittest(oldtable != table, "pci-6220 find other route_values table\n"); unittest(oldtable != table, "pci-6220 find other route_values table\n");
unittest( unittest(RVI(table, B(PXI_Star), B(NI_AI_SampleClock)) == V(20) &&
RVI(table, B(PXI_Star), B(NI_AI_SampleClock)) == V(20) &&
RVI(table, B(NI_10MHzRefClock), B(TRIGGER_LINE(0))) == V(12) && RVI(table, B(NI_10MHzRefClock), B(TRIGGER_LINE(0))) == V(12) &&
RVI(table, B(NI_AI_ConvertClock), B(NI_PFI(0))) == V(3) && RVI(table, B(NI_AI_ConvertClock), B(NI_PFI(0))) == V(3) &&
RVI(table, B(NI_AI_ConvertClock), B(NI_PFI(2))) == V(3), RVI(table, B(NI_AI_ConvertClock), B(NI_PFI(2))) == V(3),