ARM: sun6i: dt: Fix mod0 compatible
The module 0 clock compatibles were changed between the time the patch was sent and it was merged. Update the compatibles. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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@ -200,7 +200,7 @@
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spi0_clk: clk@01c200a0 {
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spi0_clk: clk@01c200a0 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200a0 0x4>;
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reg = <0x01c200a0 0x4>;
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clocks = <&osc24M>, <&pll6>;
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clocks = <&osc24M>, <&pll6>;
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clock-output-names = "spi0";
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clock-output-names = "spi0";
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@ -208,7 +208,7 @@
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spi1_clk: clk@01c200a4 {
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spi1_clk: clk@01c200a4 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200a4 0x4>;
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reg = <0x01c200a4 0x4>;
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clocks = <&osc24M>, <&pll6>;
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clocks = <&osc24M>, <&pll6>;
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clock-output-names = "spi1";
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clock-output-names = "spi1";
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@ -216,7 +216,7 @@
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spi2_clk: clk@01c200a8 {
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spi2_clk: clk@01c200a8 {
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#clock-cells = <0>;
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200a8 0x4>;
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reg = <0x01c200a8 0x4>;
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clocks = <&osc24M>, <&pll6>;
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clocks = <&osc24M>, <&pll6>;
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clock-output-names = "spi2";
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clock-output-names = "spi2";
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@ -224,7 +224,7 @@
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spi3_clk: clk@01c200ac {
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spi3_clk: clk@01c200ac {
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#clock-cells = <0>;
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-mod0-clk";
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compatible = "allwinner,sun4i-a10-mod0-clk";
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reg = <0x01c200ac 0x4>;
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reg = <0x01c200ac 0x4>;
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clocks = <&osc24M>, <&pll6>;
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clocks = <&osc24M>, <&pll6>;
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clock-output-names = "spi3";
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clock-output-names = "spi3";
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