forked from Minki/linux
b43: bus: abstract 80211 core info
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
c0b4c00907
commit
21d889d433
@ -70,5 +70,8 @@ struct b43_bus_dev *b43_bus_dev_ssb_init(struct ssb_device *sdev)
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dev->block_read = b43_bus_ssb_block_read;
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dev->block_write = b43_bus_ssb_block_write;
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dev->core_id = sdev->id.coreid;
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dev->core_rev = sdev->id.revision;
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return dev;
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}
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@ -19,6 +19,9 @@ struct b43_bus_dev {
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size_t count, u16 offset, u8 reg_width);
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void (*block_write)(struct b43_bus_dev *dev, const void *buffer,
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size_t count, u16 offset, u8 reg_width);
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u16 core_id;
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u8 core_rev;
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};
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struct b43_bus_dev *b43_bus_dev_ssb_init(struct ssb_device *sdev);
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@ -1085,7 +1085,7 @@ int b43_dma_init(struct b43_wldev *dev)
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goto err_destroy_mcast;
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/* No support for the TX status DMA ring. */
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B43_WARN_ON(dev->sdev->id.revision < 5);
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B43_WARN_ON(dev->dev->core_rev < 5);
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b43dbg(dev->wl, "%u-bit DMA initialized\n",
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(unsigned int)type);
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@ -548,7 +548,7 @@ void b43_tsf_read(struct b43_wldev *dev, u64 *tsf)
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{
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u32 low, high;
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B43_WARN_ON(dev->sdev->id.revision < 3);
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B43_WARN_ON(dev->dev->core_rev < 3);
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/* The hardware guarantees us an atomic read, if we
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* read the low register first. */
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@ -586,7 +586,7 @@ static void b43_tsf_write_locked(struct b43_wldev *dev, u64 tsf)
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{
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u32 low, high;
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B43_WARN_ON(dev->sdev->id.revision < 3);
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B43_WARN_ON(dev->dev->core_rev < 3);
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low = tsf;
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high = (tsf >> 32);
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@ -714,7 +714,7 @@ void b43_dummy_transmission(struct b43_wldev *dev, bool ofdm, bool pa_on)
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b43_ram_write(dev, i * 4, buffer[i]);
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b43_write16(dev, 0x0568, 0x0000);
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if (dev->sdev->id.revision < 11)
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if (dev->dev->core_rev < 11)
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b43_write16(dev, 0x07C0, 0x0000);
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else
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b43_write16(dev, 0x07C0, 0x0100);
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@ -1132,7 +1132,7 @@ void b43_power_saving_ctl_bits(struct b43_wldev *dev, unsigned int ps_flags)
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b43_write32(dev, B43_MMIO_MACCTL, macctl);
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/* Commit write */
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b43_read32(dev, B43_MMIO_MACCTL);
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if (awake && dev->sdev->id.revision >= 5) {
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if (awake && dev->dev->core_rev >= 5) {
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/* Wait for the microcode to wake up. */
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for (i = 0; i < 100; i++) {
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ucstat = b43_shm_read16(dev, B43_SHM_SHARED,
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@ -1221,7 +1221,7 @@ static void drain_txstatus_queue(struct b43_wldev *dev)
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{
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u32 dummy;
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if (dev->sdev->id.revision < 5)
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if (dev->dev->core_rev < 5)
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return;
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/* Read all entries from the microcode TXstatus FIFO
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* and throw them away.
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@ -1689,7 +1689,7 @@ static void b43_update_templates(struct b43_wl *wl)
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static void b43_set_beacon_int(struct b43_wldev *dev, u16 beacon_int)
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{
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b43_time_lock(dev);
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if (dev->sdev->id.revision >= 3) {
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if (dev->dev->core_rev >= 3) {
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b43_write32(dev, B43_MMIO_TSF_CFP_REP, (beacon_int << 16));
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b43_write32(dev, B43_MMIO_TSF_CFP_START, (beacon_int << 10));
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} else {
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@ -2113,7 +2113,7 @@ static int b43_try_request_fw(struct b43_request_fw_context *ctx)
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{
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struct b43_wldev *dev = ctx->dev;
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struct b43_firmware *fw = &ctx->dev->fw;
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const u8 rev = ctx->dev->sdev->id.revision;
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const u8 rev = ctx->dev->dev->core_rev;
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const char *filename;
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u32 tmshigh;
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int err;
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@ -2448,7 +2448,7 @@ static int b43_upload_microcode(struct b43_wldev *dev)
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snprintf(wiphy->fw_version, sizeof(wiphy->fw_version), "%u.%u",
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dev->fw.rev, dev->fw.patch);
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wiphy->hw_version = dev->sdev->id.coreid;
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wiphy->hw_version = dev->dev->core_id;
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if (b43_is_old_txhdr_format(dev)) {
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/* We're over the deadline, but we keep support for old fw
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@ -2606,7 +2606,7 @@ static int b43_gpio_init(struct b43_wldev *dev)
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mask |= 0x0200;
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set |= 0x0200;
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}
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if (dev->sdev->id.revision >= 2)
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if (dev->dev->core_rev >= 2)
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mask |= 0x0010; /* FIXME: This is redundant. */
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gpiodev = b43_ssb_gpio_dev(dev);
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@ -2741,7 +2741,7 @@ static void b43_adjust_opmode(struct b43_wldev *dev)
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/* Workaround: On old hardware the HW-MAC-address-filter
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* doesn't work properly, so always run promisc in filter
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* it in software. */
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if (dev->sdev->id.revision <= 4)
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if (dev->dev->core_rev <= 4)
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ctl |= B43_MACCTL_PROMISC;
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b43_write32(dev, B43_MMIO_MACCTL, ctl);
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@ -2907,7 +2907,7 @@ static int b43_chip_init(struct b43_wldev *dev)
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b43_write16(dev, 0x005E, value16);
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}
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b43_write32(dev, 0x0100, 0x01000000);
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if (dev->sdev->id.revision < 5)
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if (dev->dev->core_rev < 5)
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b43_write32(dev, 0x010C, 0x01000000);
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b43_write32(dev, B43_MMIO_MACCTL, b43_read32(dev, B43_MMIO_MACCTL)
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@ -2922,7 +2922,7 @@ static int b43_chip_init(struct b43_wldev *dev)
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/* Initially set the wireless operation mode. */
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b43_adjust_opmode(dev);
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if (dev->sdev->id.revision < 3) {
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if (dev->dev->core_rev < 3) {
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b43_write16(dev, 0x060E, 0x0000);
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b43_write16(dev, 0x0610, 0x8000);
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b43_write16(dev, 0x0604, 0x0000);
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@ -3105,7 +3105,7 @@ static int b43_validate_chipaccess(struct b43_wldev *dev)
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b43_shm_write32(dev, B43_SHM_SHARED, 0, backup0);
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b43_shm_write32(dev, B43_SHM_SHARED, 4, backup4);
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if ((dev->sdev->id.revision >= 3) && (dev->sdev->id.revision <= 10)) {
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if ((dev->dev->core_rev >= 3) && (dev->dev->core_rev <= 10)) {
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/* The 32bit register shadows the two 16bit registers
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* with update sideeffects. Validate this. */
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b43_write16(dev, B43_MMIO_TSF_CFP_START, 0xAAAA);
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@ -4352,7 +4352,7 @@ static int b43_wireless_core_init(struct b43_wldev *dev)
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if (err)
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goto err_busdown;
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b43_shm_write16(dev, B43_SHM_SHARED,
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B43_SHM_SH_WLCOREREV, dev->sdev->id.revision);
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B43_SHM_SH_WLCOREREV, dev->dev->core_rev);
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hf = b43_hf_read(dev);
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if (phy->type == B43_PHYTYPE_G) {
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hf |= B43_HF_SYMW;
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@ -4756,7 +4756,7 @@ static int b43_wireless_core_attach(struct b43_wldev *dev)
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goto out;
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}
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/* Get the PHY type. */
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if (dev->sdev->id.revision >= 5) {
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if (dev->dev->core_rev >= 5) {
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u32 tmshigh;
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tmshigh = ssb_read32(dev->sdev, SSB_TMSHIGH);
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@ -168,7 +168,7 @@ void b43_phy_lock(struct b43_wldev *dev)
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B43_WARN_ON(dev->phy.phy_locked);
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dev->phy.phy_locked = 1;
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#endif
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B43_WARN_ON(dev->sdev->id.revision < 3);
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B43_WARN_ON(dev->dev->core_rev < 3);
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if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
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b43_power_saving_ctl_bits(dev, B43_PS_AWAKE);
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@ -180,7 +180,7 @@ void b43_phy_unlock(struct b43_wldev *dev)
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B43_WARN_ON(!dev->phy.phy_locked);
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dev->phy.phy_locked = 0;
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#endif
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B43_WARN_ON(dev->sdev->id.revision < 3);
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B43_WARN_ON(dev->dev->core_rev < 3);
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if (!b43_is_mode(dev->wl, NL80211_IFTYPE_AP))
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b43_power_saving_ctl_bits(dev, 0);
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@ -983,7 +983,7 @@ static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
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{
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u16 tmp;
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if (dev->sdev->id.revision == 16)
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if (dev->dev->core_rev == 16)
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b43_mac_suspend(dev);
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tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
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@ -993,7 +993,7 @@ static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
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tmp |= (val & mask);
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b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
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if (dev->sdev->id.revision == 16)
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if (dev->dev->core_rev == 16)
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b43_mac_enable(dev);
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return tmp;
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@ -111,7 +111,7 @@ static u16 index_to_pioqueue_base(struct b43_wldev *dev,
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B43_MMIO_PIO11_BASE5,
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};
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if (dev->sdev->id.revision >= 11) {
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if (dev->dev->core_rev >= 11) {
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B43_WARN_ON(index >= ARRAY_SIZE(bases_rev11));
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return bases_rev11[index];
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}
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@ -121,14 +121,14 @@ static u16 index_to_pioqueue_base(struct b43_wldev *dev,
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static u16 pio_txqueue_offset(struct b43_wldev *dev)
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{
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if (dev->sdev->id.revision >= 11)
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if (dev->dev->core_rev >= 11)
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return 0x18;
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return 0;
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}
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static u16 pio_rxqueue_offset(struct b43_wldev *dev)
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{
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if (dev->sdev->id.revision >= 11)
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if (dev->dev->core_rev >= 11)
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return 0x38;
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return 8;
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}
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@ -144,7 +144,7 @@ static struct b43_pio_txqueue *b43_setup_pioqueue_tx(struct b43_wldev *dev,
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if (!q)
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return NULL;
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q->dev = dev;
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q->rev = dev->sdev->id.revision;
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q->rev = dev->dev->core_rev;
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q->mmio_base = index_to_pioqueue_base(dev, index) +
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pio_txqueue_offset(dev);
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q->index = index;
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@ -178,7 +178,7 @@ static struct b43_pio_rxqueue *b43_setup_pioqueue_rx(struct b43_wldev *dev,
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if (!q)
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return NULL;
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q->dev = dev;
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q->rev = dev->sdev->id.revision;
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q->rev = dev->dev->core_rev;
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q->mmio_base = index_to_pioqueue_base(dev, index) +
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pio_rxqueue_offset(dev);
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