MIPS: TXX9: Remove rbtx4938 board support
No active MIPS user own this board, so let's remove it. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Reviewed-by: Geert Uytterhoeven <geert@linux-m68k.org> Tested-by: Geert Uytterhoeven <geert@linux-m68k.org>
This commit is contained in:
Thomas Bogendoerfer
parent
f2c6c22fa8
commit
21d638ef94
@ -10,9 +10,7 @@ CONFIG_EXPERT=y
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CONFIG_SLAB=y
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CONFIG_MACH_TX49XX=y
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CONFIG_TOSHIBA_RBTX4927=y
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CONFIG_TOSHIBA_RBTX4938=y
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CONFIG_TOSHIBA_RBTX4939=y
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CONFIG_TOSHIBA_RBTX4938_MPLEX_KEEP=y
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# CONFIG_SECCOMP is not set
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CONFIG_PCI=y
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CONFIG_MODULES=y
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@ -6,9 +6,6 @@ BOARD_VEC(jmr3927_vec)
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BOARD_VEC(rbtx4927_vec)
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BOARD_VEC(rbtx4937_vec)
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#endif
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#ifdef CONFIG_TOSHIBA_RBTX4938
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BOARD_VEC(rbtx4938_vec)
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#endif
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#ifdef CONFIG_TOSHIBA_RBTX4939
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BOARD_VEC(rbtx4939_vec)
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#endif
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@ -1,145 +0,0 @@
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/*
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* Definitions for TX4937/TX4938
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*
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* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
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*/
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#ifndef __ASM_TXX9_RBTX4938_H
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#define __ASM_TXX9_RBTX4938_H
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#include <asm/addrspace.h>
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#include <asm/txx9irq.h>
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#include <asm/txx9/tx4938.h>
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/* Address map */
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#define RBTX4938_FPGA_REG_ADDR (IO_BASE + TXX9_CE(2) + 0x00000000)
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#define RBTX4938_FPGA_REV_ADDR (IO_BASE + TXX9_CE(2) + 0x00000002)
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#define RBTX4938_CONFIG1_ADDR (IO_BASE + TXX9_CE(2) + 0x00000004)
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#define RBTX4938_CONFIG2_ADDR (IO_BASE + TXX9_CE(2) + 0x00000006)
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#define RBTX4938_CONFIG3_ADDR (IO_BASE + TXX9_CE(2) + 0x00000008)
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#define RBTX4938_LED_ADDR (IO_BASE + TXX9_CE(2) + 0x00001000)
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#define RBTX4938_DIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001002)
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#define RBTX4938_BDIPSW_ADDR (IO_BASE + TXX9_CE(2) + 0x00001004)
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#define RBTX4938_IMASK_ADDR (IO_BASE + TXX9_CE(2) + 0x00002000)
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#define RBTX4938_IMASK2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002002)
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#define RBTX4938_INTPOL_ADDR (IO_BASE + TXX9_CE(2) + 0x00002004)
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#define RBTX4938_ISTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x00002006)
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#define RBTX4938_ISTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x00002008)
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#define RBTX4938_IMSTAT_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200a)
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#define RBTX4938_IMSTAT2_ADDR (IO_BASE + TXX9_CE(2) + 0x0000200c)
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#define RBTX4938_SOFTINT_ADDR (IO_BASE + TXX9_CE(2) + 0x00003000)
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#define RBTX4938_PIOSEL_ADDR (IO_BASE + TXX9_CE(2) + 0x00005000)
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#define RBTX4938_SPICS_ADDR (IO_BASE + TXX9_CE(2) + 0x00005002)
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#define RBTX4938_SFPWR_ADDR (IO_BASE + TXX9_CE(2) + 0x00005008)
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#define RBTX4938_SFVOL_ADDR (IO_BASE + TXX9_CE(2) + 0x0000500a)
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#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000)
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#define RBTX4938_SOFTRESETLOCK_ADDR (IO_BASE + TXX9_CE(2) + 0x00007002)
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#define RBTX4938_PCIRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007004)
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#define RBTX4938_ETHER_BASE (IO_BASE + TXX9_CE(2) + 0x00020000)
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/* Ethernet port address (Jumperless Mode (W12:Open)) */
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#define RBTX4938_ETHER_ADDR (RBTX4938_ETHER_BASE + 0x280)
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/* bits for ISTAT/IMASK/IMSTAT */
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#define RBTX4938_INTB_PCID 0
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#define RBTX4938_INTB_PCIC 1
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#define RBTX4938_INTB_PCIB 2
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#define RBTX4938_INTB_PCIA 3
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#define RBTX4938_INTB_RTC 4
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#define RBTX4938_INTB_ATA 5
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#define RBTX4938_INTB_MODEM 6
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#define RBTX4938_INTB_SWINT 7
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#define RBTX4938_INTF_PCID (1 << RBTX4938_INTB_PCID)
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#define RBTX4938_INTF_PCIC (1 << RBTX4938_INTB_PCIC)
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#define RBTX4938_INTF_PCIB (1 << RBTX4938_INTB_PCIB)
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#define RBTX4938_INTF_PCIA (1 << RBTX4938_INTB_PCIA)
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#define RBTX4938_INTF_RTC (1 << RBTX4938_INTB_RTC)
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#define RBTX4938_INTF_ATA (1 << RBTX4938_INTB_ATA)
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#define RBTX4938_INTF_MODEM (1 << RBTX4938_INTB_MODEM)
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#define RBTX4938_INTF_SWINT (1 << RBTX4938_INTB_SWINT)
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#define rbtx4938_fpga_rev_addr ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR)
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#define rbtx4938_led_addr ((__u8 __iomem *)RBTX4938_LED_ADDR)
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#define rbtx4938_dipsw_addr ((__u8 __iomem *)RBTX4938_DIPSW_ADDR)
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#define rbtx4938_bdipsw_addr ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR)
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#define rbtx4938_imask_addr ((__u8 __iomem *)RBTX4938_IMASK_ADDR)
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#define rbtx4938_imask2_addr ((__u8 __iomem *)RBTX4938_IMASK2_ADDR)
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#define rbtx4938_intpol_addr ((__u8 __iomem *)RBTX4938_INTPOL_ADDR)
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#define rbtx4938_istat_addr ((__u8 __iomem *)RBTX4938_ISTAT_ADDR)
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#define rbtx4938_istat2_addr ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR)
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#define rbtx4938_imstat_addr ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR)
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#define rbtx4938_imstat2_addr ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR)
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#define rbtx4938_softint_addr ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR)
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#define rbtx4938_piosel_addr ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR)
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#define rbtx4938_spics_addr ((__u8 __iomem *)RBTX4938_SPICS_ADDR)
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#define rbtx4938_sfpwr_addr ((__u8 __iomem *)RBTX4938_SFPWR_ADDR)
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#define rbtx4938_sfvol_addr ((__u8 __iomem *)RBTX4938_SFVOL_ADDR)
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#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
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#define rbtx4938_softresetlock_addr \
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((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR)
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#define rbtx4938_pcireset_addr ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR)
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/*
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* IRQ mappings
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*/
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#define RBTX4938_SOFT_INT0 0 /* not used */
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#define RBTX4938_SOFT_INT1 1 /* not used */
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#define RBTX4938_IRC_INT 2
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#define RBTX4938_TIMER_INT 7
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/* These are the virtual IRQ numbers, we divide all IRQ's into
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* 'spaces', the 'space' determines where and how to enable/disable
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* that particular IRQ on an RBTX4938 machine. Add new 'spaces' as new
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* IRQ hardware is supported.
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*/
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#define RBTX4938_NR_IRQ_IOC 8
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#define RBTX4938_IRQ_IRC TXX9_IRQ_BASE
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#define RBTX4938_IRQ_IOC (TXX9_IRQ_BASE + TX4938_NUM_IR)
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#define RBTX4938_IRQ_END (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
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#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
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#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
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#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
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#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
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#define RBTX4938_IRQ_IRC_DMA(ch, n) (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n))
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#define RBTX4938_IRQ_IRC_PIO (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
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#define RBTX4938_IRQ_IRC_PDMAC (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
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#define RBTX4938_IRQ_IRC_PCIC (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
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#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
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#define RBTX4938_IRQ_IRC_NDFMC (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
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#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
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#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
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#define RBTX4938_IRQ_IRC_ACLC (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
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#define RBTX4938_IRQ_IRC_ACLCPME (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
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#define RBTX4938_IRQ_IRC_PCIC1 (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
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#define RBTX4938_IRQ_IRC_SPI (RBTX4938_IRQ_IRC + TX4938_IR_SPI)
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#define RBTX4938_IRQ_IOC_PCID (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID)
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#define RBTX4938_IRQ_IOC_PCIC (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC)
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#define RBTX4938_IRQ_IOC_PCIB (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB)
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#define RBTX4938_IRQ_IOC_PCIA (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA)
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#define RBTX4938_IRQ_IOC_RTC (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC)
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#define RBTX4938_IRQ_IOC_ATA (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA)
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#define RBTX4938_IRQ_IOC_MODEM (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM)
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#define RBTX4938_IRQ_IOC_SWINT (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT)
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/* IOC (PCI, etc) */
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#define RBTX4938_IRQ_IOCINT (TXX9_IRQ_BASE + TX4938_IR_INT(0))
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/* Onboard 10M Ether */
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#define RBTX4938_IRQ_ETHER (TXX9_IRQ_BASE + TX4938_IR_INT(1))
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#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
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#define RBTX4938_RTL_8019_IRQ (RBTX4938_IRQ_ETHER)
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void rbtx4938_prom_init(void);
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void rbtx4938_irq_setup(void);
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struct pci_dev;
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int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
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#endif /* __ASM_TXX9_RBTX4938_H */
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@ -1,34 +0,0 @@
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/*
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* Definitions for TX4937/TX4938 SPI
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*
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
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*/
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#ifndef __ASM_TXX9_SPI_H
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#define __ASM_TXX9_SPI_H
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#include <linux/errno.h>
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#ifdef CONFIG_SPI
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int spi_eeprom_register(int busid, int chipid, int size);
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int spi_eeprom_read(int busid, int chipid,
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int address, unsigned char *buf, int len);
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#else
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static inline int spi_eeprom_register(int busid, int chipid, int size)
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{
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return -ENODEV;
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}
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static inline int spi_eeprom_read(int busid, int chipid,
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int address, unsigned char *buf, int len)
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{
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return -ENODEV;
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}
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#endif
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#endif /* __ASM_TXX9_SPI_H */
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@ -51,7 +51,6 @@ obj-$(CONFIG_SOC_TX4927) += pci-tx4927.o
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obj-$(CONFIG_SOC_TX4938) += pci-tx4938.o
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obj-$(CONFIG_SOC_TX4939) += pci-tx4939.o
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obj-$(CONFIG_TOSHIBA_RBTX4927) += fixup-rbtx4927.o
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obj-$(CONFIG_TOSHIBA_RBTX4938) += fixup-rbtx4938.o
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obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
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obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
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obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
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@ -1,53 +0,0 @@
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/*
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* Toshiba rbtx4938 pci routines
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
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*/
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#include <linux/types.h>
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#include <asm/txx9/pci.h>
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#include <asm/txx9/rbtx4938.h>
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int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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int irq = tx4938_pcic1_map_irq(dev, slot);
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if (irq >= 0)
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return irq;
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irq = pin;
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/* IRQ rotation */
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irq--; /* 0-3 */
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if (slot == TX4927_PCIC_IDSEL_AD_TO_SLOT(23)) {
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/* PCI CardSlot (IDSEL=A23) */
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/* PCIA => PCIA (IDSEL=A23) */
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irq = (irq + 0 + slot) % 4;
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} else {
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/* PCI Backplane */
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if (txx9_pci_option & TXX9_PCI_OPT_PICMG)
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irq = (irq + 33 - slot) % 4;
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else
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irq = (irq + 3 + slot) % 4;
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}
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irq++; /* 1-4 */
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switch (irq) {
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case 1:
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irq = RBTX4938_IRQ_IOC_PCIA;
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break;
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case 2:
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irq = RBTX4938_IRQ_IOC_PCIB;
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break;
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case 3:
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irq = RBTX4938_IRQ_IOC_PCIC;
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break;
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case 4:
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irq = RBTX4938_IRQ_IOC_PCID;
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break;
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}
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return irq;
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}
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@ -39,14 +39,6 @@ config TOSHIBA_RBTX4927
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This Toshiba board is based on the TX4927 processor. Say Y here to
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support this machine type
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config TOSHIBA_RBTX4938
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bool "Toshiba RBTX4938 board"
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depends on MACH_TX49XX
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select SOC_TX4938
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help
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This Toshiba board is based on the TX4938 processor. Say Y here to
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support this machine type
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config TOSHIBA_RBTX4939
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bool "Toshiba RBTX4939 board"
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depends on MACH_TX49XX
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@ -105,25 +97,5 @@ config PICMG_PCI_BACKPLANE_DEFAULT
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depends on PCI && MACH_TXX9
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default y if !TOSHIBA_FPCIB0
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if TOSHIBA_RBTX4938
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comment "Multiplex Pin Select"
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choice
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prompt "PIO[58:61]"
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default TOSHIBA_RBTX4938_MPLEX_PIO58_61
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config TOSHIBA_RBTX4938_MPLEX_PIO58_61
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bool "PIO"
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config TOSHIBA_RBTX4938_MPLEX_NAND
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bool "NAND"
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config TOSHIBA_RBTX4938_MPLEX_ATA
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bool "ATA"
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config TOSHIBA_RBTX4938_MPLEX_KEEP
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bool "Keep firmware settings"
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endchoice
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endif
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config PCI_TX4927
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bool
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@ -14,5 +14,4 @@ obj-$(CONFIG_TOSHIBA_JMR3927) += jmr3927/
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# Toshiba RBTX49XX boards
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#
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obj-$(CONFIG_TOSHIBA_RBTX4927) += rbtx4927/
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obj-$(CONFIG_TOSHIBA_RBTX4938) += rbtx4938/
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obj-$(CONFIG_TOSHIBA_RBTX4939) += rbtx4939/
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@ -10,5 +10,4 @@ obj-$(CONFIG_SOC_TX4927) += mem_tx4927.o setup_tx4927.o irq_tx4927.o
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obj-$(CONFIG_SOC_TX4938) += mem_tx4927.o setup_tx4938.o irq_tx4938.o
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obj-$(CONFIG_SOC_TX4939) += setup_tx4939.o irq_tx4939.o
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obj-$(CONFIG_TOSHIBA_FPCIB0) += smsc_fdc37m81x.o
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obj-$(CONFIG_SPI) += spi_eeprom.o
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obj-$(CONFIG_TXX9_7SEGLED) += 7segled.o
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@ -315,11 +315,6 @@ static void __init select_board(void)
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txx9_board_vec = &rbtx4937_vec;
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break;
|
||||
#endif
|
||||
#ifdef CONFIG_TOSHIBA_RBTX4938
|
||||
case 0x4938:
|
||||
txx9_board_vec = &rbtx4938_vec;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_TOSHIBA_RBTX4939
|
||||
case 0x4939:
|
||||
txx9_board_vec = &rbtx4939_vec;
|
||||
|
||||
@ -1,104 +0,0 @@
|
||||
/*
|
||||
* spi_eeprom.c
|
||||
* Copyright (C) 2000-2001 Toshiba Corporation
|
||||
*
|
||||
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
|
||||
* terms of the GNU General Public License version 2. This program is
|
||||
* licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*
|
||||
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/export.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/eeprom.h>
|
||||
#include <asm/txx9/spi.h>
|
||||
|
||||
#define AT250X0_PAGE_SIZE 8
|
||||
|
||||
/* register board information for at25 driver */
|
||||
int __init spi_eeprom_register(int busid, int chipid, int size)
|
||||
{
|
||||
struct spi_board_info info = {
|
||||
.modalias = "at25",
|
||||
.max_speed_hz = 1500000, /* 1.5Mbps */
|
||||
.bus_num = busid,
|
||||
.chip_select = chipid,
|
||||
/* Mode 0: High-Active, Sample-Then-Shift */
|
||||
};
|
||||
struct spi_eeprom *eeprom;
|
||||
eeprom = kzalloc(sizeof(*eeprom), GFP_KERNEL);
|
||||
if (!eeprom)
|
||||
return -ENOMEM;
|
||||
strcpy(eeprom->name, "at250x0");
|
||||
eeprom->byte_len = size;
|
||||
eeprom->page_size = AT250X0_PAGE_SIZE;
|
||||
eeprom->flags = EE_ADDR1;
|
||||
info.platform_data = eeprom;
|
||||
return spi_register_board_info(&info, 1);
|
||||
}
|
||||
|
||||
/* simple temporary spi driver to provide early access to seeprom. */
|
||||
|
||||
static struct read_param {
|
||||
int busid;
|
||||
int chipid;
|
||||
int address;
|
||||
unsigned char *buf;
|
||||
int len;
|
||||
} *read_param;
|
||||
|
||||
static int __init early_seeprom_probe(struct spi_device *spi)
|
||||
{
|
||||
int stat = 0;
|
||||
u8 cmd[2];
|
||||
int len = read_param->len;
|
||||
char *buf = read_param->buf;
|
||||
int address = read_param->address;
|
||||
|
||||
dev_info(&spi->dev, "spiclk %u KHz.\n",
|
||||
(spi->max_speed_hz + 500) / 1000);
|
||||
if (read_param->busid != spi->master->bus_num ||
|
||||
read_param->chipid != spi->chip_select)
|
||||
return -ENODEV;
|
||||
while (len > 0) {
|
||||
/* spi_write_then_read can only work with small chunk */
|
||||
int c = len < AT250X0_PAGE_SIZE ? len : AT250X0_PAGE_SIZE;
|
||||
cmd[0] = 0x03; /* AT25_READ */
|
||||
cmd[1] = address;
|
||||
stat = spi_write_then_read(spi, cmd, sizeof(cmd), buf, c);
|
||||
buf += c;
|
||||
len -= c;
|
||||
address += c;
|
||||
}
|
||||
return stat;
|
||||
}
|
||||
|
||||
static struct spi_driver early_seeprom_driver __initdata = {
|
||||
.driver = {
|
||||
.name = "at25",
|
||||
},
|
||||
.probe = early_seeprom_probe,
|
||||
};
|
||||
|
||||
int __init spi_eeprom_read(int busid, int chipid, int address,
|
||||
unsigned char *buf, int len)
|
||||
{
|
||||
int ret;
|
||||
struct read_param param = {
|
||||
.busid = busid,
|
||||
.chipid = chipid,
|
||||
.address = address,
|
||||
.buf = buf,
|
||||
.len = len
|
||||
};
|
||||
|
||||
read_param = ¶m;
|
||||
ret = spi_register_driver(&early_seeprom_driver);
|
||||
if (!ret)
|
||||
spi_unregister_driver(&early_seeprom_driver);
|
||||
return ret;
|
||||
}
|
||||
@ -1,2 +0,0 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
obj-y += prom.o setup.o irq.o
|
||||
@ -1,157 +0,0 @@
|
||||
/*
|
||||
* Toshiba RBTX4938 specific interrupt handlers
|
||||
* Copyright (C) 2000-2001 Toshiba Corporation
|
||||
*
|
||||
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
|
||||
* terms of the GNU General Public License version 2. This program is
|
||||
* licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*
|
||||
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
|
||||
*/
|
||||
|
||||
/*
|
||||
* MIPS_CPU_IRQ_BASE+00 Software 0
|
||||
* MIPS_CPU_IRQ_BASE+01 Software 1
|
||||
* MIPS_CPU_IRQ_BASE+02 Cascade TX4938-CP0
|
||||
* MIPS_CPU_IRQ_BASE+03 Multiplexed -- do not use
|
||||
* MIPS_CPU_IRQ_BASE+04 Multiplexed -- do not use
|
||||
* MIPS_CPU_IRQ_BASE+05 Multiplexed -- do not use
|
||||
* MIPS_CPU_IRQ_BASE+06 Multiplexed -- do not use
|
||||
* MIPS_CPU_IRQ_BASE+07 CPU TIMER
|
||||
*
|
||||
* TXX9_IRQ_BASE+00
|
||||
* TXX9_IRQ_BASE+01
|
||||
* TXX9_IRQ_BASE+02 Cascade RBTX4938-IOC
|
||||
* TXX9_IRQ_BASE+03 RBTX4938 RTL-8019AS Ethernet
|
||||
* TXX9_IRQ_BASE+04
|
||||
* TXX9_IRQ_BASE+05 TX4938 ETH1
|
||||
* TXX9_IRQ_BASE+06 TX4938 ETH0
|
||||
* TXX9_IRQ_BASE+07
|
||||
* TXX9_IRQ_BASE+08 TX4938 SIO 0
|
||||
* TXX9_IRQ_BASE+09 TX4938 SIO 1
|
||||
* TXX9_IRQ_BASE+10 TX4938 DMA0
|
||||
* TXX9_IRQ_BASE+11 TX4938 DMA1
|
||||
* TXX9_IRQ_BASE+12 TX4938 DMA2
|
||||
* TXX9_IRQ_BASE+13 TX4938 DMA3
|
||||
* TXX9_IRQ_BASE+14
|
||||
* TXX9_IRQ_BASE+15
|
||||
* TXX9_IRQ_BASE+16 TX4938 PCIC
|
||||
* TXX9_IRQ_BASE+17 TX4938 TMR0
|
||||
* TXX9_IRQ_BASE+18 TX4938 TMR1
|
||||
* TXX9_IRQ_BASE+19 TX4938 TMR2
|
||||
* TXX9_IRQ_BASE+20
|
||||
* TXX9_IRQ_BASE+21
|
||||
* TXX9_IRQ_BASE+22 TX4938 PCIERR
|
||||
* TXX9_IRQ_BASE+23
|
||||
* TXX9_IRQ_BASE+24
|
||||
* TXX9_IRQ_BASE+25
|
||||
* TXX9_IRQ_BASE+26
|
||||
* TXX9_IRQ_BASE+27
|
||||
* TXX9_IRQ_BASE+28
|
||||
* TXX9_IRQ_BASE+29
|
||||
* TXX9_IRQ_BASE+30
|
||||
* TXX9_IRQ_BASE+31 TX4938 SPI
|
||||
*
|
||||
* RBTX4938_IRQ_IOC+00 PCI-D
|
||||
* RBTX4938_IRQ_IOC+01 PCI-C
|
||||
* RBTX4938_IRQ_IOC+02 PCI-B
|
||||
* RBTX4938_IRQ_IOC+03 PCI-A
|
||||
* RBTX4938_IRQ_IOC+04 RTC
|
||||
* RBTX4938_IRQ_IOC+05 ATA
|
||||
* RBTX4938_IRQ_IOC+06 MODEM
|
||||
* RBTX4938_IRQ_IOC+07 SWINT
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <asm/mipsregs.h>
|
||||
#include <asm/txx9/generic.h>
|
||||
#include <asm/txx9/rbtx4938.h>
|
||||
|
||||
static int toshiba_rbtx4938_irq_nested(int sw_irq)
|
||||
{
|
||||
u8 level3;
|
||||
|
||||
level3 = readb(rbtx4938_imstat_addr);
|
||||
if (unlikely(!level3))
|
||||
return -1;
|
||||
/* must use fls so onboard ATA has priority */
|
||||
return RBTX4938_IRQ_IOC + __fls8(level3);
|
||||
}
|
||||
|
||||
static void toshiba_rbtx4938_irq_ioc_enable(struct irq_data *d)
|
||||
{
|
||||
unsigned char v;
|
||||
|
||||
v = readb(rbtx4938_imask_addr);
|
||||
v |= (1 << (d->irq - RBTX4938_IRQ_IOC));
|
||||
writeb(v, rbtx4938_imask_addr);
|
||||
mmiowb();
|
||||
}
|
||||
|
||||
static void toshiba_rbtx4938_irq_ioc_disable(struct irq_data *d)
|
||||
{
|
||||
unsigned char v;
|
||||
|
||||
v = readb(rbtx4938_imask_addr);
|
||||
v &= ~(1 << (d->irq - RBTX4938_IRQ_IOC));
|
||||
writeb(v, rbtx4938_imask_addr);
|
||||
mmiowb();
|
||||
}
|
||||
|
||||
#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
|
||||
static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
|
||||
.name = TOSHIBA_RBTX4938_IOC_NAME,
|
||||
.irq_mask = toshiba_rbtx4938_irq_ioc_disable,
|
||||
.irq_unmask = toshiba_rbtx4938_irq_ioc_enable,
|
||||
};
|
||||
|
||||
static int rbtx4938_irq_dispatch(int pending)
|
||||
{
|
||||
int irq;
|
||||
|
||||
if (pending & STATUSF_IP7)
|
||||
irq = MIPS_CPU_IRQ_BASE + 7;
|
||||
else if (pending & STATUSF_IP2) {
|
||||
irq = txx9_irq();
|
||||
if (irq == RBTX4938_IRQ_IOCINT)
|
||||
irq = toshiba_rbtx4938_irq_nested(irq);
|
||||
} else if (pending & STATUSF_IP1)
|
||||
irq = MIPS_CPU_IRQ_BASE + 0;
|
||||
else if (pending & STATUSF_IP0)
|
||||
irq = MIPS_CPU_IRQ_BASE + 1;
|
||||
else
|
||||
irq = -1;
|
||||
return irq;
|
||||
}
|
||||
|
||||
static void __init toshiba_rbtx4938_irq_ioc_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = RBTX4938_IRQ_IOC;
|
||||
i < RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC; i++)
|
||||
irq_set_chip_and_handler(i, &toshiba_rbtx4938_irq_ioc_type,
|
||||
handle_level_irq);
|
||||
|
||||
irq_set_chained_handler(RBTX4938_IRQ_IOCINT, handle_simple_irq);
|
||||
}
|
||||
|
||||
void __init rbtx4938_irq_setup(void)
|
||||
{
|
||||
txx9_irq_dispatch = rbtx4938_irq_dispatch;
|
||||
/* Now, interrupt control disabled, */
|
||||
/* all IRC interrupts are masked, */
|
||||
/* all IRC interrupt mode are Low Active. */
|
||||
|
||||
/* mask all IOC interrupts */
|
||||
writeb(0, rbtx4938_imask_addr);
|
||||
|
||||
/* clear SoftInt interrupts */
|
||||
writeb(0, rbtx4938_softint_addr);
|
||||
tx4938_irq_init();
|
||||
toshiba_rbtx4938_irq_ioc_init();
|
||||
/* Onboard 10M Ether: High Active */
|
||||
irq_set_irq_type(RBTX4938_IRQ_ETHER, IRQF_TRIGGER_HIGH);
|
||||
}
|
||||
@ -1,22 +0,0 @@
|
||||
/*
|
||||
* rbtx4938 specific prom routines
|
||||
* Copyright (C) 2000-2001 Toshiba Corporation
|
||||
*
|
||||
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
|
||||
* terms of the GNU General Public License version 2. This program is
|
||||
* licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*
|
||||
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <asm/txx9/generic.h>
|
||||
#include <asm/txx9/rbtx4938.h>
|
||||
|
||||
void __init rbtx4938_prom_init(void)
|
||||
{
|
||||
memblock_add(0, tx4938_get_mem_size());
|
||||
txx9_sio_putchar_init(TX4938_SIO_REG(0) & 0xfffffffffULL);
|
||||
}
|
||||
@ -1,372 +0,0 @@
|
||||
/*
|
||||
* Setup pointers to hardware-dependent routines.
|
||||
* Copyright (C) 2000-2001 Toshiba Corporation
|
||||
*
|
||||
* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
|
||||
* terms of the GNU General Public License version 2. This program is
|
||||
* licensed "as is" without any warranty of any kind, whether express
|
||||
* or implied.
|
||||
*
|
||||
* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
|
||||
*/
|
||||
#include <linux/init.h>
|
||||
#include <linux/types.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/gpio/driver.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/mtd/physmap.h>
|
||||
|
||||
#include <asm/reboot.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/txx9/generic.h>
|
||||
#include <asm/txx9/pci.h>
|
||||
#include <asm/txx9/rbtx4938.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <asm/txx9/spi.h>
|
||||
#include <asm/txx9pio.h>
|
||||
|
||||
static void rbtx4938_machine_restart(char *command)
|
||||
{
|
||||
local_irq_disable();
|
||||
writeb(1, rbtx4938_softresetlock_addr);
|
||||
writeb(1, rbtx4938_sfvol_addr);
|
||||
writeb(1, rbtx4938_softreset_addr);
|
||||
/* fallback */
|
||||
(*_machine_halt)();
|
||||
}
|
||||
|
||||
static void __init rbtx4938_pci_setup(void)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
int extarb = !(__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCIARB);
|
||||
struct pci_controller *c = &txx9_primary_pcic;
|
||||
|
||||
register_pci_controller(c);
|
||||
|
||||
if (__raw_readq(&tx4938_ccfgptr->ccfg) & TX4938_CCFG_PCI66)
|
||||
txx9_pci_option =
|
||||
(txx9_pci_option & ~TXX9_PCI_OPT_CLK_MASK) |
|
||||
TXX9_PCI_OPT_CLK_66; /* already configured */
|
||||
|
||||
/* Reset PCI Bus */
|
||||
writeb(0, rbtx4938_pcireset_addr);
|
||||
/* Reset PCIC */
|
||||
txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
|
||||
if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
|
||||
TXX9_PCI_OPT_CLK_66)
|
||||
tx4938_pciclk66_setup();
|
||||
mdelay(10);
|
||||
/* clear PCIC reset */
|
||||
txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
|
||||
writeb(1, rbtx4938_pcireset_addr);
|
||||
iob();
|
||||
|
||||
tx4938_report_pciclk();
|
||||
tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
|
||||
if ((txx9_pci_option & TXX9_PCI_OPT_CLK_MASK) ==
|
||||
TXX9_PCI_OPT_CLK_AUTO &&
|
||||
txx9_pci66_check(c, 0, 0)) {
|
||||
/* Reset PCI Bus */
|
||||
writeb(0, rbtx4938_pcireset_addr);
|
||||
/* Reset PCIC */
|
||||
txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
|
||||
tx4938_pciclk66_setup();
|
||||
mdelay(10);
|
||||
/* clear PCIC reset */
|
||||
txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIRST);
|
||||
writeb(1, rbtx4938_pcireset_addr);
|
||||
iob();
|
||||
/* Reinitialize PCIC */
|
||||
tx4938_report_pciclk();
|
||||
tx4927_pcic_setup(tx4938_pcicptr, c, extarb);
|
||||
}
|
||||
|
||||
if (__raw_readq(&tx4938_ccfgptr->pcfg) &
|
||||
(TX4938_PCFG_ETH0_SEL|TX4938_PCFG_ETH1_SEL)) {
|
||||
/* Reset PCIC1 */
|
||||
txx9_set64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
|
||||
/* PCI1DMD==0 => PCI1CLK==GBUSCLK/2 => PCI66 */
|
||||
if (!(__raw_readq(&tx4938_ccfgptr->ccfg)
|
||||
& TX4938_CCFG_PCI1DMD))
|
||||
tx4938_ccfg_set(TX4938_CCFG_PCI1_66);
|
||||
mdelay(10);
|
||||
/* clear PCIC1 reset */
|
||||
txx9_clear64(&tx4938_ccfgptr->clkctr, TX4938_CLKCTR_PCIC1RST);
|
||||
tx4938_report_pci1clk();
|
||||
|
||||
/* mem:64K(max), io:64K(max) (enough for ETH0,ETH1) */
|
||||
c = txx9_alloc_pci_controller(NULL, 0, 0x10000, 0, 0x10000);
|
||||
register_pci_controller(c);
|
||||
tx4927_pcic_setup(tx4938_pcic1ptr, c, 0);
|
||||
}
|
||||
tx4938_setup_pcierr_irq();
|
||||
#endif /* CONFIG_PCI */
|
||||
}
|
||||
|
||||
/* SPI support */
|
||||
|
||||
/* chip select for SPI devices */
|
||||
#define SEEPROM1_CS 7 /* PIO7 */
|
||||
#define SEEPROM2_CS 0 /* IOC */
|
||||
#define SEEPROM3_CS 1 /* IOC */
|
||||
#define SRTC_CS 2 /* IOC */
|
||||
#define SPI_BUSNO 0
|
||||
|
||||
static int __init rbtx4938_ethaddr_init(void)
|
||||
{
|
||||
#ifdef CONFIG_PCI
|
||||
unsigned char dat[17];
|
||||
unsigned char sum;
|
||||
int i;
|
||||
|
||||
/* 0-3: "MAC\0", 4-9:eth0, 10-15:eth1, 16:sum */
|
||||
if (spi_eeprom_read(SPI_BUSNO, SEEPROM1_CS, 0, dat, sizeof(dat))) {
|
||||
pr_err("seeprom: read error.\n");
|
||||
return -ENODEV;
|
||||
} else {
|
||||
if (strcmp(dat, "MAC") != 0)
|
||||
pr_warn("seeprom: bad signature.\n");
|
||||
for (i = 0, sum = 0; i < sizeof(dat); i++)
|
||||
sum += dat[i];
|
||||
if (sum)
|
||||
pr_warn("seeprom: bad checksum.\n");
|
||||
}
|
||||
tx4938_ethaddr_init(&dat[4], &dat[4 + 6]);
|
||||
#endif /* CONFIG_PCI */
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init rbtx4938_spi_setup(void)
|
||||
{
|
||||
/* set SPI_SEL */
|
||||
txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_SPI_SEL);
|
||||
}
|
||||
|
||||
static struct resource rbtx4938_fpga_resource;
|
||||
|
||||
static void __init rbtx4938_time_init(void)
|
||||
{
|
||||
tx4938_time_init(0);
|
||||
}
|
||||
|
||||
static void __init rbtx4938_mem_setup(void)
|
||||
{
|
||||
unsigned long long pcfg;
|
||||
|
||||
if (txx9_master_clock == 0)
|
||||
txx9_master_clock = 25000000; /* 25MHz */
|
||||
|
||||
tx4938_setup();
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
txx9_alloc_pci_controller(&txx9_primary_pcic, 0, 0, 0, 0);
|
||||
txx9_board_pcibios_setup = tx4927_pcibios_setup;
|
||||
#else
|
||||
set_io_port_base(RBTX4938_ETHER_BASE);
|
||||
#endif
|
||||
|
||||
tx4938_sio_init(7372800, 0);
|
||||
|
||||
#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_PIO58_61
|
||||
pr_info("PIOSEL: disabling both ATA and NAND selection\n");
|
||||
txx9_clear64(&tx4938_ccfgptr->pcfg,
|
||||
TX4938_PCFG_NDF_SEL | TX4938_PCFG_ATA_SEL);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_NAND
|
||||
pr_info("PIOSEL: enabling NAND selection\n");
|
||||
txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
|
||||
txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_ATA
|
||||
pr_info("PIOSEL: enabling ATA selection\n");
|
||||
txx9_set64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_ATA_SEL);
|
||||
txx9_clear64(&tx4938_ccfgptr->pcfg, TX4938_PCFG_NDF_SEL);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_TOSHIBA_RBTX4938_MPLEX_KEEP
|
||||
pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg);
|
||||
pr_info("PIOSEL: NAND %s, ATA %s\n",
|
||||
(pcfg & TX4938_PCFG_NDF_SEL) ? "enabled" : "disabled",
|
||||
(pcfg & TX4938_PCFG_ATA_SEL) ? "enabled" : "disabled");
|
||||
#endif
|
||||
|
||||
rbtx4938_spi_setup();
|
||||
pcfg = ____raw_readq(&tx4938_ccfgptr->pcfg); /* updated */
|
||||
/* fixup piosel */
|
||||
if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
|
||||
TX4938_PCFG_ATA_SEL)
|
||||
writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x04,
|
||||
rbtx4938_piosel_addr);
|
||||
else if ((pcfg & (TX4938_PCFG_ATA_SEL | TX4938_PCFG_NDF_SEL)) ==
|
||||
TX4938_PCFG_NDF_SEL)
|
||||
writeb((readb(rbtx4938_piosel_addr) & 0x03) | 0x08,
|
||||
rbtx4938_piosel_addr);
|
||||
else
|
||||
writeb(readb(rbtx4938_piosel_addr) & ~(0x08 | 0x04),
|
||||
rbtx4938_piosel_addr);
|
||||
|
||||
rbtx4938_fpga_resource.name = "FPGA Registers";
|
||||
rbtx4938_fpga_resource.start = CPHYSADDR(RBTX4938_FPGA_REG_ADDR);
|
||||
rbtx4938_fpga_resource.end = CPHYSADDR(RBTX4938_FPGA_REG_ADDR) + 0xffff;
|
||||
rbtx4938_fpga_resource.flags = IORESOURCE_MEM | IORESOURCE_BUSY;
|
||||
if (request_resource(&txx9_ce_res[2], &rbtx4938_fpga_resource))
|
||||
pr_err("request resource for fpga failed\n");
|
||||
|
||||
_machine_restart = rbtx4938_machine_restart;
|
||||
|
||||
writeb(0xff, rbtx4938_led_addr);
|
||||
pr_info("RBTX4938 --- FPGA(Rev %02x) DIPSW:%02x,%02x\n",
|
||||
readb(rbtx4938_fpga_rev_addr),
|
||||
readb(rbtx4938_dipsw_addr), readb(rbtx4938_bdipsw_addr));
|
||||
}
|
||||
|
||||
static void __init rbtx4938_ne_init(void)
|
||||
{
|
||||
struct resource res[] = {
|
||||
{
|
||||
.start = RBTX4938_RTL_8019_BASE,
|
||||
.end = RBTX4938_RTL_8019_BASE + 0x20 - 1,
|
||||
.flags = IORESOURCE_IO,
|
||||
}, {
|
||||
.start = RBTX4938_RTL_8019_IRQ,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
};
|
||||
platform_device_register_simple("ne", -1, res, ARRAY_SIZE(res));
|
||||
}
|
||||
|
||||
static DEFINE_SPINLOCK(rbtx4938_spi_gpio_lock);
|
||||
|
||||
static void rbtx4938_spi_gpio_set(struct gpio_chip *chip, unsigned int offset,
|
||||
int value)
|
||||
{
|
||||
u8 val;
|
||||
unsigned long flags;
|
||||
spin_lock_irqsave(&rbtx4938_spi_gpio_lock, flags);
|
||||
val = readb(rbtx4938_spics_addr);
|
||||
if (value)
|
||||
val |= 1 << offset;
|
||||
else
|
||||
val &= ~(1 << offset);
|
||||
writeb(val, rbtx4938_spics_addr);
|
||||
mmiowb();
|
||||
spin_unlock_irqrestore(&rbtx4938_spi_gpio_lock, flags);
|
||||
}
|
||||
|
||||
static int rbtx4938_spi_gpio_dir_out(struct gpio_chip *chip,
|
||||
unsigned int offset, int value)
|
||||
{
|
||||
rbtx4938_spi_gpio_set(chip, offset, value);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct gpio_chip rbtx4938_spi_gpio_chip = {
|
||||
.set = rbtx4938_spi_gpio_set,
|
||||
.direction_output = rbtx4938_spi_gpio_dir_out,
|
||||
.label = "RBTX4938-SPICS",
|
||||
.base = 16,
|
||||
.ngpio = 3,
|
||||
};
|
||||
|
||||
static int __init rbtx4938_spi_init(void)
|
||||
{
|
||||
struct spi_board_info srtc_info = {
|
||||
.modalias = "rtc-rs5c348",
|
||||
.max_speed_hz = 1000000, /* 1.0Mbps @ Vdd 2.0V */
|
||||
.bus_num = 0,
|
||||
.chip_select = 16 + SRTC_CS,
|
||||
/* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */
|
||||
.mode = SPI_MODE_1 | SPI_CS_HIGH,
|
||||
};
|
||||
spi_register_board_info(&srtc_info, 1);
|
||||
spi_eeprom_register(SPI_BUSNO, SEEPROM1_CS, 128);
|
||||
spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM2_CS, 128);
|
||||
spi_eeprom_register(SPI_BUSNO, 16 + SEEPROM3_CS, 128);
|
||||
gpio_request(16 + SRTC_CS, "rtc-rs5c348");
|
||||
gpio_direction_output(16 + SRTC_CS, 0);
|
||||
gpio_request(SEEPROM1_CS, "seeprom1");
|
||||
gpio_direction_output(SEEPROM1_CS, 1);
|
||||
gpio_request(16 + SEEPROM2_CS, "seeprom2");
|
||||
gpio_direction_output(16 + SEEPROM2_CS, 1);
|
||||
gpio_request(16 + SEEPROM3_CS, "seeprom3");
|
||||
gpio_direction_output(16 + SEEPROM3_CS, 1);
|
||||
tx4938_spi_init(SPI_BUSNO);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void __init rbtx4938_mtd_init(void)
|
||||
{
|
||||
struct physmap_flash_data pdata = {
|
||||
.width = 4,
|
||||
};
|
||||
|
||||
switch (readb(rbtx4938_bdipsw_addr) & 7) {
|
||||
case 0:
|
||||
/* Boot */
|
||||
txx9_physmap_flash_init(0, 0x1fc00000, 0x400000, &pdata);
|
||||
/* System */
|
||||
txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
|
||||
break;
|
||||
case 1:
|
||||
/* System */
|
||||
txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
|
||||
/* Boot */
|
||||
txx9_physmap_flash_init(1, 0x1ec00000, 0x400000, &pdata);
|
||||
break;
|
||||
case 2:
|
||||
/* Ext */
|
||||
txx9_physmap_flash_init(0, 0x1f000000, 0x1000000, &pdata);
|
||||
/* System */
|
||||
txx9_physmap_flash_init(1, 0x1e000000, 0x1000000, &pdata);
|
||||
/* Boot */
|
||||
txx9_physmap_flash_init(2, 0x1dc00000, 0x400000, &pdata);
|
||||
break;
|
||||
case 3:
|
||||
/* Boot */
|
||||
txx9_physmap_flash_init(1, 0x1bc00000, 0x400000, &pdata);
|
||||
/* System */
|
||||
txx9_physmap_flash_init(2, 0x1a000000, 0x1000000, &pdata);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static void __init rbtx4938_arch_init(void)
|
||||
{
|
||||
txx9_gpio_init(TX4938_PIO_REG & 0xfffffffffULL, 0, TX4938_NUM_PIO);
|
||||
gpiochip_add_data(&rbtx4938_spi_gpio_chip, NULL);
|
||||
rbtx4938_pci_setup();
|
||||
rbtx4938_spi_init();
|
||||
}
|
||||
|
||||
static void __init rbtx4938_device_init(void)
|
||||
{
|
||||
rbtx4938_ethaddr_init();
|
||||
rbtx4938_ne_init();
|
||||
tx4938_wdt_init();
|
||||
rbtx4938_mtd_init();
|
||||
/* TC58DVM82A1FT: tDH=10ns, tWP=tRP=tREADID=35ns */
|
||||
tx4938_ndfmc_init(10, 35);
|
||||
tx4938_ata_init(RBTX4938_IRQ_IOC_ATA, 0, 1);
|
||||
tx4938_dmac_init(0, 2);
|
||||
tx4938_aclc_init();
|
||||
platform_device_register_simple("txx9aclc-generic", -1, NULL, 0);
|
||||
tx4938_sramc_init();
|
||||
txx9_iocled_init(RBTX4938_LED_ADDR - IO_BASE, -1, 8, 1, "green", NULL);
|
||||
}
|
||||
|
||||
struct txx9_board_vec rbtx4938_vec __initdata = {
|
||||
.system = "Toshiba RBTX4938",
|
||||
.prom_init = rbtx4938_prom_init,
|
||||
.mem_setup = rbtx4938_mem_setup,
|
||||
.irq_setup = rbtx4938_irq_setup,
|
||||
.time_init = rbtx4938_time_init,
|
||||
.device_init = rbtx4938_device_init,
|
||||
.arch_init = rbtx4938_arch_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pci_map_irq = rbtx4938_pci_map_irq,
|
||||
#endif
|
||||
};
|
||||
Loading…
Reference in New Issue
Block a user